JPH033264A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH033264A JPH033264A JP1136326A JP13632689A JPH033264A JP H033264 A JPH033264 A JP H033264A JP 1136326 A JP1136326 A JP 1136326A JP 13632689 A JP13632689 A JP 13632689A JP H033264 A JPH033264 A JP H033264A
- Authority
- JP
- Japan
- Prior art keywords
- power device
- insulating layer
- layer
- control circuit
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 abstract description 10
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 239000002184 metal Substances 0.000 description 31
- 229910052751 metal Inorganic materials 0.000 description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電力用デバイスと、その電力用デバイスを
制御するための制御回路部とを有する半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a power device and a control circuit section for controlling the power device.
第２図は従来の半導体装置Ａを示す断面図である。同図
に示すように、放熱板を構成するＡＪ２７Ｉ５板１上に
は板側上ばエポキシ系樹脂等で構成される第１絶縁層２
が形成される。さらに、第１絶縁層２上にはノイズを遮
断するための金属シールド層３が形成されるとともに、
その金属シールド層３上には例えばエポキシ系樹脂等で
構成される第２絶縁層４が形成される。さらに、第２絶
縁層４上には制御回路部５の金属配線パターン６および
電力用デバイス部８の金属配線パターン９が形成される
。FIG. 2 is a sectional view showing a conventional semiconductor device A. As shown in the figure, on the AJ27I5 board 1 constituting the heat sink, there is a first insulating layer 2 made of epoxy resin or the like on the board side.
is formed. Further, a metal shield layer 3 for blocking noise is formed on the first insulating layer 2, and
A second insulating layer 4 made of, for example, epoxy resin is formed on the metal shield layer 3. Further, on the second insulating layer 4, a metal wiring pattern 6 of the control circuit section 5 and a metal wiring pattern 9 of the power device section 8 are formed.
電力用デバイス部８において、金属配線パターン９上に
は銅ブロック１０が半田１１により取付けられるととも
に、その銅ブロツク１０上には、ＩＧＢＴ（縦型絶縁ゲ
ート型バイポーラトランジスタ）を構成する半導体チッ
プ等の電力用デバイス１２が半田１３により取付けられ
る。In the power device section 8, a copper block 10 is attached to the metal wiring pattern 9 by solder 11, and a semiconductor chip or the like constituting an IGBT (vertical insulated gate bipolar transistor) is mounted on the copper block 10. Power device 12 is attached by solder 13.
一方、制御回路部５の金属配線パターン６上には、半導
体、半導体チップまたはそれら以外の電子部品等の制御
回路部品７が取付けられる。さらに、金属配線パターン
６のグランド（ＧＮＤ）６ａは第２絶縁層４を貫通して
金属シールド層３に接地されている。また、制御回路部
５と電力用デバイス１２とは金属細線ワイヤ１４により
接続されており、制御回路部５からの電気信号に基づい
て電力用デバイス１２の駆動が制御され、所定の時間帯
に電力用デバイス部８に大電流が供給されるように構成
している。On the other hand, on the metal wiring pattern 6 of the control circuit section 5, a control circuit component 7 such as a semiconductor, a semiconductor chip, or other electronic components is attached. Further, a ground (GND) 6a of the metal wiring pattern 6 penetrates the second insulating layer 4 and is grounded to the metal shield layer 3. Further, the control circuit section 5 and the power device 12 are connected by a thin metal wire 14, and the drive of the power device 12 is controlled based on the electrical signal from the control circuit section 5, and the power device 12 is The configuration is such that a large current is supplied to the device section 8.
［発明が解決しようとする課題〕
ところで、一般に制御回路部５で取り扱われる電流・電
圧は小さく、ノイズによる影響は大きい。[Problems to be Solved by the Invention] Incidentally, the current and voltage handled by the control circuit section 5 are generally small, and the influence of noise is large.
このため、制御回路部５の下方に金属シールド層３を形
成して、制御回路部５へのノイズの侵入を遮断し、制御
回路部５の誤動作を防止するようにしている。For this reason, a metal shield layer 3 is formed below the control circuit section 5 to block noise from entering the control circuit section 5 and prevent the control circuit section 5 from malfunctioning.
一方、電力用デバイス部８で取り扱われる電流・電圧は
大きく、ノイズによる影響が小さいにもかかわらず、従
来の半導体装置Ａでは、電力用デバイス部８の下方にも
金属シールド層３が形成されている。このため、電力用
デバイス部８の下方には、金属シールド層３を挟んで伝
熱抵抗の太きい絶縁層２，４が２層配置されることにな
り、電力用デバイス１２に大電流が供給された際に発生
する熱が銅ブロック１０を介して、Ａ９基板１ヘスムー
ズに伝熱されず、放熱性に劣るという問題があった。こ
のように電力用デバイス１２の放熱がスムーズに行われ
ないと、温度上昇により電力用デバイス１２の熱抵抗が
大きくなり、電力用デバイス１２に供給された主電流を
充分に引き出すことができない等の支障を来たすことに
なる。On the other hand, although the current and voltage handled by the power device section 8 are large and the influence of noise is small, in the conventional semiconductor device A, the metal shield layer 3 is also formed below the power device section 8. There is. Therefore, two insulating layers 2 and 4 with large heat transfer resistance are arranged below the power device section 8 with the metal shield layer 3 in between, and a large current is supplied to the power device 12. There was a problem in that the heat generated when the copper block 10 was removed was not smoothly transferred to the A9 substrate 1 through the copper block 10, resulting in poor heat dissipation. If the heat dissipation of the power device 12 is not performed smoothly in this way, the thermal resistance of the power device 12 will increase due to temperature rise, and the main current supplied to the power device 12 will not be able to be drawn out sufficiently. This will cause trouble.
この発明は、上記従来技術の問題を解消し、制御回路部
をノイズから保護しながら、電力用デバイズ部の放熱性
を向上できる半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device that solves the problems of the prior art described above and can improve heat dissipation of a power device section while protecting a control circuit section from noise.
上記目的を達成するため、この発明の半導体装置は、放
熱板上に第１絶縁層が形成され、前記第１絶縁層上の一
領域に配線パターン層が形成されるとともに、その配線
パターン層上に電力用デバイスが設けられる一方、前記
第１絶縁層上の前記一領域を除く領域にシールド層が形
成され、そのシールド層上に第２絶縁層が形成されると
ともに、その第２絶縁層上に前記電力用デバイスを制御
するための制御回路部が設けられている。In order to achieve the above object, the semiconductor device of the present invention includes a first insulating layer formed on a heat sink, a wiring pattern layer formed in a region on the first insulating layer, and a wiring pattern layer on the wiring pattern layer. A power device is provided on the first insulating layer, a shield layer is formed on the first insulating layer except for the one area, a second insulating layer is formed on the shield layer, and a second insulating layer is formed on the second insulating layer. A control circuit section for controlling the power device is provided.
この発明における半導体装置は、第１絶縁層上の一領域
に配線パターンを介して電力用デバイスを設けることに
より、電力用デバイス下方の絶縁層が一層だけになり、
電力用デバイスに発生する熱が効率良く放熱板に伝熱さ
れる。また、制御回路部は、従来と同様シールド層によ
りノイズから保護される。In the semiconductor device of the present invention, by providing a power device in one area on the first insulating layer via a wiring pattern, there is only one insulating layer below the power device,
Heat generated in the power device is efficiently transferred to the heat sink. Further, the control circuit section is protected from noise by a shield layer as in the conventional case.
第１図はこの発明の一実施例である半導体装置Ｂを示す
断面図である。同図に示すように、放熱板を構成するＡ
ｌ基板２１上には、例えばエポキシ系樹脂等により構成
される第１絶縁層２２が形成される。さらに、第１絶縁
層２２上には金属パターンが形成されて、その金属パタ
ーンの一領域で電力用デバイス部２８の金属配線パター
ン２９が構成されるとともに、上記一領域を除く領域で
制御回路部２５の金属シールド層２３が構成される。FIG. 1 is a sectional view showing a semiconductor device B which is an embodiment of the present invention. As shown in the figure, A constituting the heat sink
A first insulating layer 22 made of, for example, epoxy resin is formed on the l substrate 21 . Furthermore, a metal pattern is formed on the first insulating layer 22, and one area of the metal pattern constitutes a metal wiring pattern 29 of the power device section 28, and the area other than the one area constitutes a control circuit section. 25 metal shield layers 23 are constructed.
電力用デバイス部２８において、金属配線パターン２９
上には、銅ブロック３０が半田３１により取付けられる
とともに、銅ブロツク３０上にＩＧＢＴを構成する半導
体チップ等の電力用デバイス３２が半田３３により取付
けられる。In the power device section 28, the metal wiring pattern 29
A copper block 30 is attached on top with solder 31, and a power device 32 such as a semiconductor chip constituting an IGBT is attached on the copper block 30 with solder 33.
一方、金属シールド層２３上には、例えばエポキシ系樹
脂等により構成される第２絶縁層２４が形成されるとと
もに、その第２絶縁層２４上には金属配線パターン２６
が形成される。さらに、金属配線パターン２６上には半
導体、半導体チップまたはそれら以外の電子部品等の制
御回路部品２７が取付けられるとともに、金属配線パタ
ーン２６のグランド（ＧＮＤ）２６ａが第２絶縁層２４
を貫通して金属シールド層２３に接地される。ここで、
金属配線パターン２６と制御回路部品２７とで制御回路
部２５が構成されている。On the other hand, a second insulating layer 24 made of, for example, epoxy resin is formed on the metal shield layer 23, and a metal wiring pattern 26 is formed on the second insulating layer 24.
is formed. Further, a control circuit component 27 such as a semiconductor, a semiconductor chip, or other electronic components is mounted on the metal wiring pattern 26, and a ground (GND) 26a of the metal wiring pattern 26 is connected to the second insulating layer 24.
It penetrates through the metal shield layer 23 and is grounded. here,
The control circuit section 25 is composed of the metal wiring pattern 26 and the control circuit component 27.
また、制御回路部２５と電力用デバイス３２とは金属細
線ワイヤ３４により接続されており、制御回路部２５か
らの電気信号に基づいて電力用デバイス３２の駆動が制
御され、所定の時間帯に電力用デバイス部２８に大電流
が供給されるように構成している。Further, the control circuit section 25 and the power device 32 are connected by a thin metal wire 34, and the drive of the power device 32 is controlled based on the electrical signal from the control circuit section 25, and the power The configuration is such that a large current is supplied to the device section 28.
この半導体装置Ｂによれば、電力用デバイス部２８の下
方に金属シールド層２３が形成されないため、電力用デ
バイス部２８とＡｆ１基板２１との間の絶縁層２２が一
層だけになり、電力用デバイス３２に大電流が供給され
た際に発生する熱がスムーズにＡｌｌ基板２１へ放熱さ
れる。According to this semiconductor device B, since the metal shield layer 23 is not formed below the power device section 28, there is only one insulating layer 22 between the power device section 28 and the Af1 substrate 21, and the power device Heat generated when a large current is supplied to 32 is smoothly radiated to the All-in-One substrate 21.
すなわち、上記第２図に示す従来の半導体装置Ａでは、
電力用デバイス部２８とＡＪ２基板１との間に伝熱抵抗
の大きい絶縁層２．４が二層配置されるのに対し、この
半導体装置Ｂでは絶縁層２２が一層だけになり、電力用
デバイス部２８とＡＩ基板２１との間の伝熱抵抗が減少
し、電力用デバイス１２の熱が銅ブロック３０を介して
効率良くＡＩ基板２１に伝熱される。具体的に説明する
と、このような半導体装置Ａ、Ｂにおいて、エポキシ系
樹脂の絶縁層２，４，２２．２４を形成する場合、−層
の膜厚はおよそ１００μｍ程度必要となり、−層の絶縁
層の伝熱抵抗はおよそ０．８°Ｃ／Ｗ程度となる。した
がって、第２図に示すように、従来の半導体装置Ａでは
、金属シールド層３の伝熱抵抗を考慮しなくとも、伝熱
抵抗がおよそ１゜６℃／Ｗとなる。これに対し、第１図
に示すように、この実施例の半導体装置Ｂでは、伝熱抵
抗がおよそ０．８℃／Ｗとなり、伝熱抵抗をかなり減少
させることができる。That is, in the conventional semiconductor device A shown in FIG. 2 above,
Two insulating layers 2.4 with high heat transfer resistance are arranged between the power device section 28 and the AJ2 substrate 1, whereas in this semiconductor device B, there is only one insulating layer 22, and the power device The heat transfer resistance between the portion 28 and the AI substrate 21 is reduced, and the heat of the power device 12 is efficiently transferred to the AI substrate 21 via the copper block 30. Specifically, when forming the insulating layers 2, 4, 22, and 24 of epoxy resin in such semiconductor devices A and B, the thickness of the - layer is required to be approximately 100 μm, and the thickness of the - layer is approximately 100 μm. The heat transfer resistance of the layer is approximately 0.8°C/W. Therefore, as shown in FIG. 2, in the conventional semiconductor device A, the heat transfer resistance is approximately 1.degree. 6.degree. C./W, even without considering the heat transfer resistance of the metal shield layer 3. On the other hand, as shown in FIG. 1, in the semiconductor device B of this embodiment, the heat transfer resistance is approximately 0.8° C./W, and the heat transfer resistance can be considerably reduced.
このようにこの半導体装置Ｂでは、放熱性に優れている
ので、電力用デバイス３２の熱抵抗が小さくなり、電力
用デバイス３２に供給される主電流を充分に引き出すこ
とができる。As described above, since this semiconductor device B has excellent heat dissipation, the thermal resistance of the power device 32 is reduced, and the main current supplied to the power device 32 can be sufficiently drawn out.
また、放熱性に優れているので、電力用デバイス３２の
他の部品への熱影響がなく、したがって集積度を高める
ことができ、装置の小型化が図れる。Further, since it has excellent heat dissipation, there is no heat influence on other parts of the power device 32, and therefore the degree of integration can be increased, and the device can be made smaller.
なお、制御回路部２５の下方には、金属シールド層２３
が形成されているため、制御回路部２５はノイズにより
影響されず誤動作が生じるようなことはない。さらに、
電力用デバイス部２８は、その下方に金属シールド層２
３が形成されていないが、上述したように取り扱われる
電流・電圧が大きいので、ノイズによる悪影響はない。Note that a metal shield layer 23 is provided below the control circuit section 25.
is formed, the control circuit section 25 is not affected by noise and will not malfunction. moreover,
The power device section 28 has a metal shield layer 2 below it.
3 is not formed, but since the current and voltage handled as described above are large, there is no adverse effect due to noise.
ところで、上記実施例においては、電力用デバイス３２
に用いられている半導体チップがＩＧＢＴにより構成さ
れているが、これはＩＧＢＴだけに限られることなく、
例えばＩＧＢＴ以外のバイポーラトランジスタ、ＭＯＳ
ＦＥＴ、ＭＣＴ （ＭＯＳ Ｃｏｎｔｒｏｌ、ｌｅｄ
Ｔｒａｎｓｉｓｔｏｒ）等でもよい。By the way, in the above embodiment, the power device 32
The semiconductor chip used in
For example, bipolar transistors other than IGBT, MOS
FET, MCT (MOS Control, led
Transistor) etc. may be used.
以上のように、この発明の半導体装置によれば、取り扱
われる？ｌｔ流・電圧が大きくてノイズによる影響が少
ない電力用デバイスの、その下方のシールド層を廃止す
るようにしているため、電力用デバイスの下方の絶縁層
が一層だけになり、電力用デバイスに発生する熱が効率
良く放熱板に伝熱されて放熱性に優れるとともに、制御
回路部はシールド層によりノイズから保護されるという
効果が得られる。As described above, according to the semiconductor device of the present invention, ? Since the shield layer below the power device, which has a large current/voltage and is less affected by noise, is removed, there is only one insulating layer below the power device, and noise can occur in the power device. The resulting heat is efficiently transferred to the heat sink, resulting in excellent heat dissipation, and the control circuit section is protected from noise by the shield layer.
第１図はこの発明の一実施例である半導体装置を示す断
面図、第２図は従来の半導体装置を示す断面図である。
図において、２１はＡ９基板、２２は第１絶縁層、２３
は金属シールド層、２４は第２絶縁層、２５は制御回路
部、２６は金属配線パターン、２７は制御回路部品、２
８は電力用デバイス部、２９は金属配線パターン、３２
は電力用デバイス、Ｂは半導体装置である。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, 21 is an A9 substrate, 22 is a first insulating layer, 23
2 is a metal shield layer, 24 is a second insulating layer, 25 is a control circuit section, 26 is a metal wiring pattern, 27 is a control circuit component, 2
8 is a power device section, 29 is a metal wiring pattern, 32
is a power device, and B is a semiconductor device. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
層上の一領域に配線パターン層が形成されるとともに、
その配線パターン層上に電力用デバイスが設けられる一
方、前記第１絶縁層上の前記一領域を除く領域にシール
ド層が形成され、そのシールド層上に第２絶縁層が形成
されるとともに、その第２絶縁層上に前記電力用デバイ
スを制御するための制御回路部が設けられたことを特徴
とする半導体装置。(1) A first insulating layer is formed on a heat sink, a wiring pattern layer is formed in a region on the first insulating layer, and
A power device is provided on the wiring pattern layer, while a shield layer is formed on the first insulating layer except for the one area, and a second insulating layer is formed on the shield layer. A semiconductor device characterized in that a control circuit section for controlling the power device is provided on the second insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1136326A JPH033264A (en) | 1989-05-30 | 1989-05-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1136326A JPH033264A (en) | 1989-05-30 | 1989-05-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033264A true JPH033264A (en) | 1991-01-09 |
Family
ID=15172609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1136326A Pending JPH033264A (en) | 1989-05-30 | 1989-05-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033264A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61206078A (en) * | 1985-03-08 | 1986-09-12 | Nippon Telegr & Teleph Corp <Ntt> | Part deleting and processing system for picture drawing image |
| JPH05129515A (en) * | 1991-11-05 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor device |
| JP2019021921A (en) * | 2017-07-13 | 2019-02-07 | 東莞市國瓷新材料科技有限公司 | Ceramic module for power semiconductor COB and preparation method thereof |
-
1989
- 1989-05-30 JP JP1136326A patent/JPH033264A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61206078A (en) * | 1985-03-08 | 1986-09-12 | Nippon Telegr & Teleph Corp <Ntt> | Part deleting and processing system for picture drawing image |
| JPH05129515A (en) * | 1991-11-05 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor device |
| JP2019021921A (en) * | 2017-07-13 | 2019-02-07 | 東莞市國瓷新材料科技有限公司 | Ceramic module for power semiconductor COB and preparation method thereof |
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