JPH03295312A - Drive circuit for power mos field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to a noise at the time of the operation of a power MOSFET, and in addition, to improve switching speed by using a drive circuit provided with three inverter circuits. CONSTITUTION:A first and a second inverter circuits constituted of the MOSFETs 2 to 5 and a third inverter circuit 6 are provided, And a capacitance component 8 and a resistance component 9 are connected between the output terminal 7 of the first inverter circuit and the earth. Thus, since three inverter circuits 2 to 6 are provided for driving the power MOSFET 1, a hysteresis characteristic can be given to threshold voltage for operating and stopping the power MOSFET 1, and the malfunction due to the noise at the time of the operation of the power MOSFET 1 is prevented, and besides, its stopping operation is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a drive circuit for a power MOS field effect transistor (hereinafter referred to as power MOSFET) which is widely used in motor drives, switching power supplies, and the like.

BACKGROUND OF THE INVENTION In recent years, power MO5FET drive circuits based on a direct drive method from a logic circuit have become mainstream.

The configuration will be explained below with reference to FIG. In the figure, 41 is a power MO8FET.

42 is an inverter circuit. A plurality of inverter circuits 42 are connected in parallel to form a power MOSFET.
This is to improve the ability to supply current to the gate of T41.

In this drive circuit, when the input signal reaches a level exceeding the threshold voltage of the inverter circuit 42, the power MOSFE
When T41 stops and becomes a level lower than the threshold voltage of the inverter circuit 42, the power MO8FET41
will work.

Problems to be Solved by the Invention In such a drive circuit, since the inverter circuit 42 is connected before the power MO8FET 41, the power M
The OSFET 41 is activated and stopped at the threshold of the inverter circuit 42 at the previous stage. Therefore, if the threshold value is lowered, the noise signal will cause the power MOSF to
There is a possibility that the ET41 malfunctions, and if the threshold voltage is increased, the switching speed becomes slow.

The present invention solves the above problems, and aims to provide a drive circuit with high switching speed and no malfunction.

Means for Solving the Problems A drive circuit for a power MOSFET according to the present invention includes a first MOSFET configured with MOSFETs to which input signals having mutually different phases are supplied. comprising a second inverter circuit and a third inverter circuit controlled by output signals of these inverter circuits, a capacitive component and a resistive component are connected between the output terminal of the first inverter circuit and ground, Further, the output terminal of the first inverter circuit is connected to a MOSFET whose source is grounded among the MOSFETs constituting the second inverter circuit.
A third inverter circuit is connected to the semiconductor substrate of the OSFET and further connected between the second inverter circuit and the power MOSFET, and the operation of the power MOSFET is controlled by the output signal of the third inverter circuit. It is configured like this.

Function: Since the drive circuit of the present invention includes three inverter circuits to drive the power MO8FET, the power M
The operating and stopping threshold voltage of the OSFET has hysteresis characteristics, which prevents malfunctions due to noise during the operation of the power MO5FET, and also speeds up the stopping operation.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2.

As shown in the figure, this example uses a power MO5FET
A first inverter circuit composed of MOSFET2.3 and MOSFET4. .

5, a second inverter circuit configured with a third inverter circuit,
It is equipped with an inverter circuit 6. This inverter circuit 6
Although the illustration of its specific configuration is omitted, this is also configured with a MOSFET.

The output terminal 7 of the first inverter circuit is grounded via a parallel connection of a capacitive component 8 and a resistive component 9. Further, this output terminal 7 is connected to the MOSFET of the second inverter circuit.
It is also connected to the semiconductor substrate No. 5. In addition, MOSFE
The source of T5 is grounded. And power MO
A third inverter circuit 6 is connected between SFETI and the output terminal of the second inverter circuit.

With such a configuration, the first. Control signals having mutually different phases, that is, mutually inverted control signals are applied to input terminals (gate terminals) 10 and 11 of the second inverter circuit.

First, when the Lebel signal is applied to the input terminal 11, the second inverter circuit generates an O level output signal. Therefore, the third inverter circuit 6 supplies a level output signal to the gate of the power MO8FETI, and the power MO8FETI operates.

On the other hand, at this time, since the O level signal is applied to the input terminal 10, the level level signal is output to the output terminal 7 of the first inverter circuit, and charges are accumulated in the capacitive component 8. Therefore, MOSFET5 of the second inverter circuit
A Lebel voltage is applied to the semiconductor substrate on which the

Next, when the input signal at the input terminal 11 becomes O level, the output signal of the second inverter circuit becomes O level, but since a positive bias voltage is applied to the semiconductor substrate of MOSFET 5, the threshold value The voltage has shifted to the positive side,
In other words, it has become high.

On the contrary, the input signal at the input terminal 10 becomes a level, so the output signal obtained at the output terminal 7 of the first inverter circuit becomes O level, and the charge accumulated in the capacitance component 8 is released, and the voltage between both ends of the signal becomes O level. The voltage between the However, the speed of this voltage drop depends on the apparent resistance between the drain and source of MOSFET 3, the capacitance component 8, and the resistance component 9.
Since it depends on the time constant determined by the second inverter circuit, the third inverter circuit 6 and the power MO8
If the switching speed of FETl is made sufficiently smaller than this time constant, the threshold voltage shift as described above will occur. Then, before the next signal is applied, the discharge of the charge from the capacitive component 8 ends, and the signal level at the output terminal 7 becomes O level.

Next, when the input signal at the input terminal 11 becomes a level, the input signal at the input terminal 10 is at O level, so that an output signal at a level is obtained at the output terminal 7 of the first inverter circuit. At this time, the voltage across the capacitance component 8 begins to rise, but the voltage across the MOSFE of the second inverter circuit is faster than that.
T5 operates, which causes power MOSFET I to operate. At this time, since the silicon substrate potential of MOSFET 5 is at 0 level, the threshold voltage remains low.

From the above, the operation of power MOSFETI.

A hysteresis characteristic occurs in the threshold voltage for stopping, and the threshold voltage when operating is high (the threshold voltage is low when stopping).

Note that the power MO8FET that is the output element is a vertical MO8FET (DMO8FET), and the constituent elements of each inverter circuit are N-channel horizontal MOSFETs.
By using an oxide film capacitor as the capacitor, this circuit can be constructed within one chip without using a special separation process within the same semiconductor substrate.

FIG. 2 is a sectional view of the drive circuit of the present invention shown in FIG. 1 implemented on one chip.

In the figure, 21 is an N-type semiconductor substrate, 22 is a high concentration N-type semiconductor substrate, and 23 is a power DMOS FET.
24 is the same drain terminal, 25 is the same gate insulating film, 26 is the same gate electrode, 27 is the same P type channel region,
28 is the source of horizontal MO8FET, 29 is the same train,
30 is the same P-type well, 31 is the same gate insulating film, 32 is the same gate electrode, 33.34 is the capacitive component extraction terminal, 35
3 is a heavily doped P-type region, and 36 is an oxide film.

In this embodiment, a resistive component 9 is used as shown in FIG. 1, but instead of this resistive component 9, a P-channel MO5FET may be used, which is a so-called complementary MOSFET (CMO5FET). You can also do it.

Effects of the Invention The present invention provides a method for operating a power MO8FET.
The first . A second and a third inverter circuit are connected, a capacitance component and a resistance component are connected between the output terminal of the first inverter circuit and the ground, and the first
The output terminal of the inverter circuit is connected to the semiconductor substrate of the IO3FET whose source is grounded among the MOSFETs constituting the second inverter circuit, and the second inverter circuit and the aforementioned power MO8FET are connected to each other. Since it consists of a drive circuit with a third inverter circuit connected between the
A driving circuit for an OS type field effect transistor can be provided.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a drive circuit for a power MO8 type field effect transistor according to an embodiment of the present invention, FIG. 2 is a partial cross-sectional view of the drive circuit realized as a single chip, and FIG. 3 is a conventional FIG. 3 is an equivalent circuit diagram of a drive circuit. 1.=-power MO5FET (power MO5 type field effect transistor), 2.3... MOSFET forming the first inverter circuit, 4.5...
MOSFET 6, which constitutes the second inverter circuit.
...Third inverter circuit, 7...Output terminal of first inverter circuit, 8...Capacitance component, 9...Resistance component, 21・・・・・・Semiconductor substrate.

Claims (2)

[Claims] (1) MO to which input signals with different phases are supplied
The first inverter circuit includes first and second inverter circuits configured with S-type field effect transistors, and a third inverter circuit controlled by output signals of the first and second inverter circuits. A capacitance component and a resistance component are connected between the output terminal of the first inverter circuit and the ground, and the output terminal of the first inverter circuit is connected to the source of the MOS field effect transistor constituting the second inverter circuit. The third inverter circuit is connected to the semiconductor substrate of the MOS type field effect transistor, and the third
A driving circuit for a power MOS field effect transistor, characterized in that an inverter circuit is connected thereto, and the operation of the power MOS field effect transistor is controlled by an output signal of the third inverter circuit. (2) The power MOS type electric field according to claim 1, wherein the resistance component connected between the output terminal of the first inverter circuit and the ground is constituted by a P-channel MOS type field effect transistor. Effect transistor drive circuit.