JPH09167950A - Analog switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively eliminate switching noise with a small space factor of a chip by applying a signal inverted to a gate drive signal whose level between an input signal level and a GND level to a back gate of a main switch. SOLUTION: A gate drive circuit 6 uses a drive signal C to drive a gate G 101 of a main switch 1 being an nMOS transistor(TR) at a voltage between a voltage VK and a voltage VIN (VK>VIN). Furthermore, a back gate(BG) drive circuit 7 drives a BG 104 at a voltage between the voltage VIN and a GND level (VIN>GND) inversely to the voltage of the gate G101 so as to switch on/off the switch 1. The BG 104 is electrostatically coupled with a source 103 and a drain 102 via a junction capacitance and with a channel via a depletion layer at channel generation so as to cancel a level change in the source 103 and the channel. Thus, switching noise is effectively eliminated with a small chip space factor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing switching noise generated when an analog switch using a MOS transistor is turned on and off.

[0002]

2. Description of the Related Art As a conventional technique for reducing the switching noise of an analog switch using a MOS transistor, there is, for example, the one shown in FIG. 5 disclosed in JP-A-3-17131. In this conventional example, the main switch 1
An auxiliary switch 2 having the same size and structure as the main switch 1 is added to and connected to the signal line 3 on the output side of. The auxiliary switch 2 has an electrode A whose gate 201 is connected to the signal line 3 and whose source 203 and drain 202 are short-circuited.
9 is connected to the drive circuit. The electrode A9 has a signal A having a phase opposite to that of the gate drive signal G for the main switch 1.
G is applied.

The cause of switching noise is that the electric charge accumulated in the parasitic capacitance changes as the circuit state changes, and
This is due to the phenomenon that the main switch 1 flows into the parasitic capacitance or flows out from the signal line 3 into the parasitic capacitance.
Since one of the auxiliary switch 2 and the auxiliary switch 2 is always in the ON state, the parasitic charge is exchanged between the two switches and does not appear in the signal line 3. Therefore, although the noise reduction effect of this conventional example can be expected considerably, there is a problem that the occupied area increases considerably because the auxiliary switch 2 is required. In order to reduce the conductance between the input and output, it is necessary to make the area of the main switch 1 considerably large, but since the auxiliary switch 2 has the most noise canceling effect when it has the same configuration as the main switch 1, the total main switch An area that can accommodate two is required. This becomes a serious problem in an image pickup device or a multiplexer that requires a large number of MOS switches.

As a second conventional example, Japanese Patent Laid-Open No. 1-27 is known.
There is one as shown in FIG. 6 disclosed in Japanese Patent No. 6920. In the figure, 1 is an (nMOS) main switch, 4 is an input terminal, 5 is an output terminal, 6 is a gate drive circuit, 7 is a back gate drive circuit, 10 is a pMOS main switch, 101 is a main switch gate, and 102 is a main switch. Drain, 103
Is a main switch source, 104 is a main switch back gate, 301 is a pMOS switch gate, and 302 is a pMO.
S-switch drain, 303 is a pMOS switch source, and 304 is a pMOS switch back gate. n
This is an example in which the back gate voltage of each of the MOS analog main switch 1 and the pMOS analog main switch 10 is changed at the time of switching, but this is intended to improve the conductance characteristics, and the driving method is also in phase with the gate drive signal. It is applied to the gate.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
An auxiliary switch with the same configuration as the main switch is added to the signal line,
The method of connecting and driving the gate of the auxiliary switch in the opposite phase to the gate drive signal of the main switch requires an area where at least two main switches, which tend to occupy a large area, are included to reduce the conductance. In particular, in an element such as an image pickup element that uses a lot of switches, there is a problem that the chip area is significantly increased.

An object of the present invention is to solve the above problems and to provide an analog switch having a switching noise suppressing effect equivalent to that of the conventional example while significantly reducing the chip area as compared with the conventional example. .

[0007]

In order to solve the above problems, in the present invention, the back gate of the main switch is driven in a phase opposite to that of the gate drive signal. Specifically, the amplitude is reversed between the input signal value and the GND level and in the opposite phase to the gate drive signal.

[0008]

According to the above-mentioned means, the gate drive voltage is at the low level and the back gate drive voltage is at the input terminal voltage level when the switch is off, and the gate voltage changes from the low level to the high level during switching. Then, the back gate voltage is changed from the input signal level to the GND level, and when the switch is turned on, the gate drive voltage becomes the high level and the back gate drive voltage becomes the GND level.

The back gate is electrostatically coupled to the source-drain electrode via the junction capacitance and further to the channel via the depletion layer capacitance when forming the channel. Therefore, by changing the back gate voltage in the opposite phase to the change in the gate voltage, the change in the signal line potential, that is, the potential of the source electrode of the main switch and the potential of the channel can be canceled and the switching noise can be reduced.

FIG. 1 is a diagram showing a first embodiment of an analog switch according to the present invention. In the figure, 1 is a main switch, 3 is a signal line, 4 is an input terminal, 5 is an output terminal, 6 is a gate drive circuit, 7 is a back gate drive circuit, 8 is a drive signal input terminal, 101 is a main switch gate, and 102. Is a main switch drain, 103 is a main switch source, and 104 is a main switch back gate. Main switch 1 is nM
The source 103 of the OS transistor is the input terminal 4
The drain 102 is connected to the output terminal 5, the gate 101 is connected to the gate drive circuit 6, and the back gate 104 is connected to the back gate drive circuit 7. The gate drive circuit 6 is composed of one stage of inverter,
Amplitude is made between K and the input voltage VIN. The back gate drive circuit 7 includes two stages of inverters and causes the back gate 104 to swing between VIN and GND. The inputs of these two drive circuits are connected to a common input terminal C8.

Here, in order to explain the operation of the present invention, the parasitic capacitance of each portion will be briefly calculated with reference to FIG. Hereinafter, the gate oxide film thickness of the main switch 1 is d, the relative permittivity is ε _1, and the relative permittivity of silicon is ε ₂ . Capacitance C of the gate 101 and the drain 102 of the main switch 1
gd is a gate overlap capacitance, and Cgd = Agd × ε ₁ × ε ₀ / d where Agd is the area where the gate 101 faces the drain 102. Since the electrostatic capacitance Cbd between the drain 102 and the back gate 104 is a one-sided step junction capacitance, if the substrate impurity concentration is Nb, the diffusion voltage Vb, the drain-back gate voltage is Vbd, and the drain junction area is Adj, then Cbd = Adj × √ [q × ε ₂ × ε ₀ × Nb / {2 (Vb + Vb
d)}].

When a channel is not formed, the electrostatic capacitance Cgb between the gate 101 and the back gate 104 is Cgb = ε ₁ × ε ₀ / [d × √ {1 + 2 × when the gate applied voltage is Vg. ε ₁ ∧ 2 × ε ₀ × (Vg + Vb)
/ (ε ₂ × Nb × d ∧ ₂ )}]. At the time of forming the channel, the charge of the inversion layer changes the electrostatic capacitance Cgb between the gate 101 and the back gate 104 to the Cgc between the gate 101 and the channel 105 and the back gate 1.
04-channel 105 and Cbc.

Next, the operation will be described step by step based on the input waveform shown in FIG. In the figure, G is a gate input signal and BG is a back gate input signal. (A) When Switched Off The gate 101 and the back gate 104 are short-circuited with the input terminal 4 and are in a switched off state. (B) Transient state from switch-off to on When the voltage applied to the gate 101 is less than or equal to the threshold value, since no channel is formed, the potential fluctuation of the back gate affects only the drain 102. Drain 102
Are canceled out by the above-mentioned Cgd and Cbd being subjected to potential fluctuations in mutually opposite directions, and the potential fluctuations are reduced. In other words, the charge accumulated in Cgd is absorbed by Cbd by the gate 101 input signal. At that time, a part of the potential fluctuation of the back gate is absorbed by the change of the depletion layer width of the drain 102, but the remaining part is transmitted to the drain 102. When the voltage exceeds the threshold value, a channel is formed, so that the potential variation of the back gate extends not only to the drain but also to the channel, and acts to suppress the potential variation of the channel via Cbc described above. .

(C) When the switch is turned on In this state, the gate potential becomes VK and the back gate potential becomes a constant value at the GND level, and the switch is turned on. (D) Transient state from switch ON to OFF At this timing, the fluctuation of the drain potential is suppressed in the reverse process of (b). That is, as the gate potential drops from VK to the input signal value VIN, the back gate potential becomes GN.
Since the voltage is increased from the D level to VIN, the drain potential and the potential variation of the signal line 3 due to the parasitic capacitance can be suppressed for the same reason as in the case of (b).

FIG. 4 is a diagram showing a second embodiment according to the present invention. In the second embodiment, the nMOS main switch 1 and the pMOS main switch 1 are different from the first embodiment in which only the nMOS is used as the main switch.
Since both 0s are used, the conductance is improved and signals from both directions can be passed. The drive circuit is the same as that of the first embodiment, but the gate 301 of the pMOS main switch 10 has nM
The back gate drive waveform BG of the OS main switch 1 is set to pM
The back gate 304 of the OS main switch 10 has an nMOS
The gate drive waveform G of the main switch 1 is applied.

[0016]

The effects obtained by the representative one of the inventions of the present application will be briefly described as follows. That is, in the analog switch that changes the conductance according to the signal value given to the gate of the MOS transistor and creates two states of ON and OFF,
By applying a signal opposite in phase to the gate drive signal to the back gate, it is possible to effectively eliminate the switching noise that occurs during switching with a significantly smaller chip area than in the conventional example. It was

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the first embodiment.

FIG. 3 is a characteristic diagram for explaining the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a first conventional example.

FIG. 6 is a circuit diagram of a second conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main switch 2 ... Auxiliary switch 3 ... Signal line 4 ... Input terminal 5 ... Output terminal 6 ... Gate drive circuit 7 ... Back gate drive circuit 8 ... Drive signal input terminal 10 ... pMOS main switch 101 ... Main switch gate 102 ... Main Switch drain 103 ... Main switch source 104 ... Main switch back gate 201 ... Auxiliary switch gate 202 ... Auxiliary switch drain 203 ... Auxiliary switch source 204 ... Auxiliary switch back gate 301 ... pMO
S switch gate 302 ... pMOS switch drain 303 ... pMO
S switch source 304 ... pMOS switch back gate

Claims (3)

[Claims] 1. An analog switch in which a gate applied voltage of a MOS transistor is controlled to control a conductance between an input terminal and an output terminal, wherein the MOS
An analog switch characterized in that a back gate drive signal having a phase opposite to that of the gate drive signal applied to the gate of the MOS transistor is applied to the back gate of the transistor. 2. The MOS transistor is an n-channel type, and when the input terminal and the output terminal are in a non-conducting state, the same voltage as the input terminal voltage is applied to its gate and back gate. A predetermined voltage higher than the input terminal voltage is applied to the gate and a predetermined voltage lower than the input terminal voltage is applied to the back gate when the terminals and the output terminals are in a conductive state. 1. The analog switch described in 1. 3. The MOS transistor is a p-channel type, and when the input terminal and the output terminal are in a non-conductive state, the same voltage as the input terminal voltage is applied to its gate and back gate, The predetermined voltage lower than the input terminal voltage is applied to the gate and the predetermined voltage higher than the input terminal voltage is applied to the back gate when the terminals and the output terminals are in a conductive state. 1. The analog switch described in 1.