JPH03292773A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

Info

Publication number
JPH03292773A
JPH03292773A JP2094612A JP9461290A JPH03292773A JP H03292773 A JPH03292773 A JP H03292773A JP 2094612 A JP2094612 A JP 2094612A JP 9461290 A JP9461290 A JP 9461290A JP H03292773 A JPH03292773 A JP H03292773A
Authority
JP
Japan
Prior art keywords
thin film
insulating film
insulating
laminated
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2094612A
Other languages
Japanese (ja)
Inventor
Wakao Miyazawa
和加雄 宮沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2094612A priority Critical patent/JPH03292773A/en
Publication of JPH03292773A publication Critical patent/JPH03292773A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make the interface of an insulating thin film clean and to restrain the interface level of the thin film so as to enable a thin film transistor to be lowered in power consumption and to operate at a high speed by a method wherein an insulating film is formed and then irradiated with ozone. CONSTITUTION:A semiconductor thin film layer highly doped with impurities is laminated on all the surface of an insulating substrate 101 and patterned into a source region and a drain region 102. Then, an intrinsic semiconductor layer 103 with no impurity is laminated through the thermal decomposition of silane or the like apd patterned. In succession, an insulating film 104 serving as a gate insulating film is laminated on the whole surface. The insulating film 104 is subjected to an ozone irradiation treatment, then a conductor thin film layer serving as a gate electrode is formed through a sputtering method and etched into a gate electrode 105 by removing the disused part of the conductor thin film, an interlaminar insulating film 106 is laminated thereon, the insulating thin film 104 and the interlaminar insulating film 106 on a region where a source and a drain electrode are built are removed to provide a contact hole 107, and a source electrode 108 and a drain electrode 109 are provided there.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、薄膜トランジスタの製造方法に関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to a method for manufacturing a thin film transistor.

[従来の技術] 従来の絶縁性基板上に薄膜トランジスタを形成する際の
、−船釣な製造方法の例を第3図に示す。
[Prior Art] FIG. 3 shows an example of a conventional manufacturing method for forming a thin film transistor on an insulating substrate.

まず、透明絶縁性基板301上に、ソース・ドレイン領
域として高温度不純物を添加した半導体薄膜層302を
形成し、バターニングした後、能動領域として不純物を
含まない真性半導体層303を積層・パターニングし、
その後ゲート絶縁膜304とゲート電極305、層間絶
縁膜306を積層し、コンタクトホール307を開口し
た後、ソース電極端子308、ドレイン電極端子309
を形成して薄膜トランジスタが完成する。
First, a semiconductor thin film layer 302 doped with high-temperature impurities is formed on a transparent insulating substrate 301 as a source/drain region, and after patterning, an intrinsic semiconductor layer 303 containing no impurities is laminated and patterned as an active region. ,
After that, a gate insulating film 304, a gate electrode 305, and an interlayer insulating film 306 are laminated, and after opening a contact hole 307, a source electrode terminal 308 and a drain electrode terminal 309 are formed.
is formed to complete the thin film transistor.

[発明が解決しようとする課題] しかし、前述の従来の技術では、絶縁膜を形成する方法
として、常圧CVD法、減圧CVD法、プラズマCVD
法、ECRプラズマCVD法、光CVD法などの気層成
長法が用いられてきたが、上記の方法では、形成された
絶縁膜の界面を清浄に保つことが雌しく、そのため界面
準位が大きくなり、動作特性の優れた薄膜トランジスタ
を形成することが困難であった。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, as a method for forming an insulating film, atmospheric pressure CVD method, low pressure CVD method, plasma CVD method is used.
However, in the above methods, it is important to keep the interface of the formed insulating film clean, so the interface state is large. Therefore, it has been difficult to form a thin film transistor with excellent operating characteristics.

本発明は、この様な従来の薄膜トランジスタの問題点を
解決するもので、その目的とするところは、より低消費
電力化、高速化が可能な薄膜トランジスタおよびその製
造方法を提供するところにある。
The present invention solves the problems of conventional thin film transistors, and its purpose is to provide a thin film transistor that can achieve lower power consumption and higher speed, and a method for manufacturing the same.

[課題を解決するための手段] 本発明の薄膜トランジスタの製造方法は、絶縁性基板上
にソース・ドレイン電極として、高温度不純物を添加し
た半導体層と、能動領域としての真性半導体層とを有し
、ゲート絶縁膜とゲート電極とを順次積層した構造を有
する薄膜トランジスタの製造方法において、 薄膜トランジスタのゲート絶縁膜にオゾンを照射する工
程を含む事を特徴とする、薄膜トランジスタの製造方法
[Means for Solving the Problems] The method for manufacturing a thin film transistor of the present invention includes a semiconductor layer doped with high-temperature impurities as a source/drain electrode on an insulating substrate, and an intrinsic semiconductor layer as an active region. A method for manufacturing a thin film transistor having a structure in which a gate insulating film and a gate electrode are sequentially laminated, the method comprising: irradiating the gate insulating film of the thin film transistor with ozone.

[作用] 本発明の上記の方法によれば、絶縁膜を形成後オゾン照
射処理を施す事により、絶縁薄膜と下地薄膜との界面を
清浄にすることができ、界面準位を抑えることによって
 低消費電力化、高速化が可能な薄膜トランジスタを構
成できる。
[Function] According to the above method of the present invention, by performing ozone irradiation treatment after forming the insulating film, the interface between the insulating thin film and the underlying thin film can be cleaned, and by suppressing the interface state, the It is possible to construct thin film transistors that can reduce power consumption and increase speed.

[実施例コ 第1図は、本発明の実施例を、工程順に示す図である。[Example code] FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps.

まず第1図(a)に示すように、絶縁性基板101の表
面全体に高濃度不純物を添加した半導体薄膜層を積層、
バターニングしソース、ドレイン領域102とする。高
温度不純物が添加された半導体薄膜層の形成には、直接
ホスフィンまたはジシランとシランを混合したガスでの
減圧CVD法や、イオン打ち込み法などが使用される。
First, as shown in FIG. 1(a), a semiconductor thin film layer doped with high concentration impurities is laminated over the entire surface of an insulating substrate 101.
The source and drain regions 102 are patterned. To form a semiconductor thin film layer to which high-temperature impurities are added, a low-pressure CVD method using direct phosphine or a mixed gas of disilane and silane, an ion implantation method, or the like is used.

次に不純物を含まない真性半導体層103を、シランの
熱分解などによって250A程度の厚さに積層し、パタ
ーニングする。この状態が第1図(b)である、シラン
は300℃以上で分解するが、理想的には600℃前後
が望ましい、ついで、全面にゲート絶縁膜となる絶縁薄
膜104を、約1500人程度の厚さに積層し、第1図
(c)とする。前記絶縁薄膜には、二酸化珪素膜や窒化
珪素膜などが、常圧CVD法、減圧CVD法、ブラズ7
CVD法、ECRブラズ7CVD法、光CVD法、また
はこれらの組合せにより、形成され、使用される。
Next, an intrinsic semiconductor layer 103 containing no impurities is laminated to a thickness of about 250 Å by thermal decomposition of silane or the like, and patterned. This state is shown in Figure 1(b). Silane decomposes at temperatures above 300°C, but ideally around 600°C. Next, about 1,500 people coated the entire surface with an insulating thin film 104 that will become the gate insulating film. 1(c). The insulating thin film is made of a silicon dioxide film, a silicon nitride film, etc., using a normal pressure CVD method, a low pressure CVD method, or a Blaze 7 film.
It is formed and used by a CVD method, an ECR Blaze 7CVD method, a photo-CVD method, or a combination thereof.

ついでオゾン照射処理を施したのちにゲート電極となる
導体薄膜層をスパッタ法などにより形成した後、ゲート
電極105となる部分を除きエツチングして、第1図(
d)を得る。ゲート電極には、アルミニュウムあるいは
クロム等の金属や、多結晶シリコン膜が使用される。次
に、層間絶縁膜106を積層、ついで、ソース・ドレイ
ン電極を形成する部分の絶縁薄膜104と層間絶縁膜1
06を除去し、コンタクトホール107としその部分に
ソース電極108、 ドレイン電極109を形成し、第
1図(e)となる。上記層間絶縁膜106には、前記絶
縁薄膜104と同じ方法で形成された絶縁膜の他に、ポ
リイミド等の有機膜が使用されることもある。
Next, after performing ozone irradiation treatment, a conductive thin film layer that will become the gate electrode is formed by sputtering or the like, and then etched except for the part that will become the gate electrode 105, as shown in FIG.
d). A metal such as aluminum or chromium or a polycrystalline silicon film is used for the gate electrode. Next, an interlayer insulating film 106 is laminated, and then the insulating thin film 104 and the interlayer insulating film 1 in the portions where source/drain electrodes are to be formed are laminated.
06 is removed, a contact hole 107 is formed, and a source electrode 108 and a drain electrode 109 are formed in the contact hole 107, as shown in FIG. 1(e). In addition to an insulating film formed by the same method as the insulating thin film 104, an organic film such as polyimide may be used for the interlayer insulating film 106.

第2図は、この発明の実施例で作成した薄膜トランジス
タのゲート電圧−ソース電流特性を示したものである。
FIG. 2 shows the gate voltage-source current characteristics of a thin film transistor manufactured in an example of the present invention.

Aの実線は、絶縁膜形成前にオゾン照射しないものであ
り、Bの破線は絶縁膜形成後にオゾン照射したものであ
る。  第2図より、絶縁膜形成後前のオゾン照射によ
って、薄膜トランジスタの特性が向上していることがわ
かる。
The solid line A indicates that ozone irradiation was not performed before forming the insulating film, and the broken line B indicates that ozone irradiation was performed after forming the insulating film. From FIG. 2, it can be seen that the characteristics of the thin film transistor are improved by ozone irradiation before and after forming the insulating film.

これらは、ゲート絶縁膜形後にオゾン照射することによ
って、能動領域である不純物を含まない真性半導体層と
ゲート絶縁膜との界面準位を、抑えることができるため
である。
This is because the interface level between the gate insulating film and the intrinsic semiconductor layer that does not contain impurities, which is the active region, can be suppressed by irradiating ozone after forming the gate insulating film.

以上のような製造工程を経て、できあがった薄膜トラン
ジスタは、従来の薄膜トランジスタに比べて清浄な界面
を持ち、従って界面準位が小さく、それによって低消費
電力化、高速化を可能にする事ができた。
Through the manufacturing process described above, the resulting thin film transistor has a cleaner interface than conventional thin film transistors, and therefore has smaller interface states, making it possible to reduce power consumption and increase speed. .

[発明の効果] 以上述べた本発明の薄膜トランジスタの製造方法によれ
ば、絶縁膜を形成した後、オゾンを照射することにより
、絶縁薄膜の界面を清浄にすることができ、界面準位を
抑えることによって 低消費電力化、高速化が可能な薄
膜トランジスタを提供できる。この様な薄膜トランジス
タは、その製造工程に、600℃以上の高温プロセスを
含まないため、絶縁基板として、ガラス基板などを使用
した液晶表示装置の各画素の駆動回路などの応用に非常
に有効である。
[Effects of the Invention] According to the method for manufacturing a thin film transistor of the present invention described above, by irradiating ozone after forming an insulating film, the interface of the insulating thin film can be cleaned, and the interface state can be suppressed. This makes it possible to provide thin film transistors with lower power consumption and higher speed. Since the manufacturing process of such thin film transistors does not involve high-temperature processes of 600°C or higher, they are very effective for applications such as drive circuits for each pixel of liquid crystal display devices that use glass substrates as insulating substrates. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図′(a)〜(e)は、本発明の実施例を示す薄膜
トランジスタの製造工程ごとの素子断面図。 第2図は絶縁膜形成後に、オゾン照射を施した場合と、
施さない場合の薄膜トランジスタの特性を比較した、比
較図。第3図は従来の薄膜トランジスタの素子断面図。 101.301・・・絶縁性基板 102.302・・・ソース・ドレイン領域103.3
03・・・真性半導体層 104.304・・・ゲート絶縁膜 105.305・・・ゲート電極 106.306・・・層間絶縁膜 107.307・・・コンタクトホール108.308
・・・ソース電極 109.309・・・ドレイン電極 以上
FIGS. 1'(a) to 1(e) are sectional views of a thin film transistor according to an embodiment of the present invention at each manufacturing process. Figure 2 shows the case where ozone irradiation is applied after the insulating film is formed.
A comparison diagram comparing the characteristics of thin film transistors when no treatment is applied. FIG. 3 is a cross-sectional view of a conventional thin film transistor. 101.301... Insulating substrate 102.302... Source/drain region 103.3
03... Intrinsic semiconductor layer 104.304... Gate insulating film 105.305... Gate electrode 106.306... Interlayer insulating film 107.307... Contact hole 108.308
...Source electrode 109.309...Drain electrode or higher

Claims (1)

【特許請求の範囲】  絶縁性基板上にソース・ドレイン電極として、高濃度
不純物を添加した半導体層と、能動領域としての真性半
導体層とを有し、ゲート絶縁膜とゲート電極とを順次積
層した構造を有する薄膜トランジスタの製造方法におい
て、 薄膜トランジスタのゲート絶縁膜にオゾンを照射する工
程を含む事を特徴とする、薄膜トランジスタの製造方法
[Scope of claims] A semiconductor layer doped with high concentration impurities as source/drain electrodes on an insulating substrate and an intrinsic semiconductor layer as an active region, and a gate insulating film and a gate electrode are sequentially laminated. A method for manufacturing a thin film transistor having a structure comprising: irradiating a gate insulating film of the thin film transistor with ozone.
JP2094612A 1990-04-10 1990-04-10 Manufacture of thin film transistor Pending JPH03292773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2094612A JPH03292773A (en) 1990-04-10 1990-04-10 Manufacture of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2094612A JPH03292773A (en) 1990-04-10 1990-04-10 Manufacture of thin film transistor

Publications (1)

Publication Number Publication Date
JPH03292773A true JPH03292773A (en) 1991-12-24

Family

ID=14115072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2094612A Pending JPH03292773A (en) 1990-04-10 1990-04-10 Manufacture of thin film transistor

Country Status (1)

Country Link
JP (1) JPH03292773A (en)

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