KR970006256B1 - Fabrication of tft - Google Patents
Fabrication of tft Download PDFInfo
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- KR970006256B1 KR970006256B1 KR1019940008116A KR19940008116A KR970006256B1 KR 970006256 B1 KR970006256 B1 KR 970006256B1 KR 1019940008116 A KR1019940008116 A KR 1019940008116A KR 19940008116 A KR19940008116 A KR 19940008116A KR 970006256 B1 KR970006256 B1 KR 970006256B1
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- insulating film
- amorphous semiconductor
- metal electrode
- film
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000007743 anodising Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 3
- FEWJPZIEWOKRBE-JCYAYHJZSA-N Dextrotartaric acid Chemical compound OC(=O)[C@H](O)[C@@H](O)C(O)=O FEWJPZIEWOKRBE-JCYAYHJZSA-N 0.000 claims description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 2
- KDYFGRWQOYBRFD-UHFFFAOYSA-N Succinic acid Natural products OC(=O)CCC(O)=O KDYFGRWQOYBRFD-UHFFFAOYSA-N 0.000 claims description 2
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- KDYFGRWQOYBRFD-NUQCWPJISA-N butanedioic acid Chemical compound O[14C](=O)CC[14C](O)=O KDYFGRWQOYBRFD-NUQCWPJISA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000011975 tartaric acid Substances 0.000 claims description 2
- 235000002906 tartaric acid Nutrition 0.000 claims description 2
- 239000008096 xylene Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 4
- 239000010407 anodic oxide Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000002048 anodisation reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
제1도는 종래 박막트랜지스터의 단면구조도.1 is a cross-sectional view of a conventional thin film transistor.
제2a도 내지 d도는 제1도에 대한 제조공정도.2a to d are manufacturing process diagrams for FIG.
제3도는 본 발명 박막트랜지스터의 단면구조도.3 is a cross-sectional view of the thin film transistor of the present invention.
제4a도 내지 e도는 제3도에 대한 제조공정도.4a to e are manufacturing process diagrams for FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 절연기판 12 : 제1금속전극층11: insulating substrate 12: first metal electrode layer
13 : 양근산화막 14 : 산화실리콘막13: both oxide oxide film 14: silicon oxide film
15 : 질소처리막 16 : 비정질반도체층15: nitrogen treated film 16: amorphous semiconductor layer
17 : 도핑된비정질반도체층 18 : 제2금속전극층17: doped amorphous semiconductor layer 18: second metal electrode layer
본 발명은 박막트랜지스터 제조방법에 관한 것으로, 특히 게이트절연막으로 종래의 질화실리콘 절연막 대신에 양극산화막과 산회실리콘(SiO2)을 적용할 수 있도록 하여 소자의 특성을 향상시키고 수율 및 생산성을 향상시키도록 하는 박막트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor, and in particular, it is possible to apply an anodized film and an acidic silicon (SiO 2 ) in place of the conventional silicon nitride insulating film as a gate insulating film to improve the characteristics of the device and improve the yield and productivity It relates to a thin film transistor manufacturing method.
제1도는 종래 박막트랜지스터의 단면구조도로서, 이 도시된 바와 같이 절연기판(1)상에 게이트전극인 제1금속전극층(2)과 양극산화막(3)이 차례롤 형성되고, 상기 양극산화막(3)위에 게이트 절연막(4)이 형성되며, 상기 게이트절연막(4)위에 비정질반도체층(5)과 도핑된비정질반도체층(6)과 오믹접촉을 이루는 소오스/드레인전극인 제2금속전극층(7)이 형성되어 구성되는 것으로, 이의 제조방법을 첨부한 제2도를 참조하여 설명하면 다음과 같다.FIG. 1 is a cross-sectional structure diagram of a conventional thin film transistor, in which a first metal electrode layer 2 and an anodization film 3, which are gate electrodes, are sequentially formed on an insulating substrate 1, and the anodic oxide film 3 is formed. The gate insulating film 4 is formed on the second metal electrode layer 7 which is a source / drain electrode in ohmic contact with the amorphous semiconductor layer 5 and the doped amorphous semiconductor layer 6 on the gate insulating film 4. This is formed and configured, with reference to Figure 2 attached to the manufacturing method thereof is as follows.
제2a도 내지 d도는 종래 박막트랜지스터의 제조공정도로서, 제2a도에 도시된 바와 같이 깨끗하게 세척한 후 건조된 기판(1)상에 게이트전극용 금속인 순수한 알루미늄(Al)을 스퍼터링(Sputtering)방법으로 증착한 다음 사진식각(Photolithography)방법으로 식각처리하여 제1금속전극층(2)을 형성한다.2a to d are manufacturing process diagrams of a conventional thin film transistor, and as shown in FIG. 2a, pure aluminum (Al), which is a metal for a gate electrode, is sputtered on the dried substrate 1 after being cleaned cleanly. After deposition, the first metal electrode layer 2 is formed by etching by photolithography.
이후, 제2b도에 도시된 바와 같이 상기 제1금속전극층(2)의 일부분을 양극산화하여 양극산화막(3)을 형성한 다음 그 위에 플라즈마화학기상증착(PECVD)방법으로 게이트절연막(4)으로 사용되는 질화실리콘(SiNx)층, 수소화된 비정질반도체층(a-Si : H)(5), 도핑된비정질반도체층(6)을 연속으로 증착한다.Subsequently, as shown in FIG. 2B, a portion of the first metal electrode layer 2 is anodized to form an anodized film 3, and then the gate insulating film 4 is formed thereon by a plasma chemical vapor deposition (PECVD) method. A silicon nitride (SiNx) layer, a hydrogenated amorphous semiconductor layer (a-Si: H) (5), and a doped amorphous semiconductor layer 6 are deposited successively.
다음으로 제2c도에 도시된 바와 같이 상기 비정질반도체층(5)과 도핑된비정질반도체층(6)을 사진식각공정을 통해 패터닝하여 상기 제1금속전극(2)위에만 남도록 한 다음 상기 도핑된비정질반도체층(6)위에 스퍼터링(Sputtering)방법으로 소오스/드레인 전극용 금속층을 증착한 후 패터닝하여 제2금속전극층(7)패턴을 형성한다.Next, as shown in FIG. 2c, the amorphous semiconductor layer 5 and the doped amorphous semiconductor layer 6 are patterned by photolithography so as to remain only on the first metal electrode 2, and then the doped A second metal electrode layer 7 pattern is formed by depositing and patterning a source / drain electrode metal layer on the amorphous semiconductor layer 6 by a sputtering method.
이후, 제2d도와 같이 상기 제2금속전극층(7)을 마스크로 사용하여 제2금속전극층(7)인 소오스.드레인전극 사이의 채널부위에 남아있는 상기 도핑된비정질반도체층(6)을 전식식삭(Dry Etch)방법으로 제거함으로써 종래 박막트랜지스터를 제조하였다.Then, as shown in FIG. 2D, the doped amorphous semiconductor layer 6 remaining on the channel portion between the source and drain electrodes of the second metal electrode layer 7, which is the second metal electrode layer 7, is used as a mask. The thin film transistor was manufactured by removing by a dry etching method.
그러나, 상기와 같이 제조되는 종래 박막트랜지스트에 있어서 질화실리콘(SiNx)을 절연막으로 사용함으로써 상기 질화실리콘(SiNx)형성시 플라즈마화학기상증착(PECVD)방법으로 형성하는데, 플라즈마(Plasma)형성에 따른 이물질(Particles)발생과 증착시간이 길어짐에 따라 수율감소 및 생산성이 저하된다.However, in the conventional thin film transistor fabricated as described above, silicon nitride (SiNx) is used as an insulating film to form the silicon nitride (SiNx) by plasma chemical vapor deposition (PECVD). As particle generation and deposition time increase, yield decreases and productivity decreases.
또한 박막트랜지스터의 특성인 이동도가 감소하게 되고, 신뢰성에 불안정성을 보여준다.In addition, mobility, which is a characteristic of thin film transistors, is reduced, and instability is shown in reliability.
그리고, 순수한 알루미늄(Al)을 게이트전극으로 사용할 경우 제작공정 온도가 증가함에 따라 힐락(Hillock)이 발생하게 되므로 상압에서 증착되는 산화실리콘(SiO2)을 사용할 수 없는 문제점이 있었다.In addition, when pure aluminum (Al) is used as the gate electrode, as the fabrication process temperature increases, hilarity occurs, and thus silicon oxide (SiO 2 ) deposited at atmospheric pressure cannot be used.
본 발명은 이러한 문제점을 해결하기 위하여 질화실리콘대신에 양극산화에 의한 양극산화막과 산화실리콘(SiO2)을 적용하고, 그 산화실리콘과 비정질반도체막 계면사이에 질소처리하여 소자의 특성향상 및 신뢰성을 향상시키도록 하고, 양극산화막 형성을 위한 금속층에 불순물을 첨가하여 고온공정시 힐락 발생을 방지토록 하는 박막트랜지스터 제조방법을 제공하는 것이다.In order to solve these problems, the present invention applies anodization film and silicon oxide (SiO 2 ) by anodization instead of silicon nitride, and improves the characteristics and reliability of the device by nitrogen treatment between the silicon oxide and the amorphous semiconductor film interface. To improve and to provide a method for manufacturing a thin film transistor to add an impurity to the metal layer for forming the anodized oxide to prevent the occurrence of hillock during the high temperature process.
본 발명은 절연기판상에 게이트전극용 제1금속전극층을 형성하는 공정과, 상기 제1금속전극층을 양극산화하여 제1절연막을 형성하는 공정과, 상기 제1절연막위에 제2절연막을 형성하는 공정과, 상기 제2절연막계면을 질소처리하는 공정과, 질소처리된 상기 제2절연막에 비정질반도체층과 도핑된비정질반도체층을 형성하는 공정과, 상기 도핑된비정질반도체층에 소오스/드레인전극요 제2금속전극층을 형성하는 공정과, 상기 소오스/드레인전극사이의 도핑된비정질반도체층을 제거하는 공정을 포함하여 이루어지도록 구성한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention provides a process of forming a first metal electrode layer for a gate electrode on an insulating substrate, anodizing the first metal electrode layer to form a first insulating film, and forming a second insulating film on the first insulating film. And nitrogen-processing the second insulating film interface, forming an amorphous semiconductor layer and a doped amorphous semiconductor layer in the nitrogen-treated second insulating film, and source / drain electrode active material in the doped amorphous semiconductor layer. It is configured to include a process of forming a second metal electrode layer and a step of removing the doped amorphous semiconductor layer between the source / drain electrode, it will be described in detail with reference to the accompanying drawings.
제3도는 본 발명 박막트랜지스터의 단면구조도로서, 이에 도시한 바와 같이 절연기판(11)상에 게이트 전극인 제1금속전극층(12)과 양극산화막(13)에 차례로 형성되고, 상기 양극산화막(13)위에 산화실리콘막(SiO2)(14)이 형성되며, 상기 산화실리콘막(14)위에 질소처리막(15)이 형성되며, 상기 질소처리막(15)위에 비정질반도체층(16)과 도핑된비정질반도체층(17)이 차례로 형성되고, 상기 도핑된비정질반도체층(17)위에 그 도핑된비정질반도체층(17)과 오믹접촉을 이루는 소오스/드레인전극인 제2금속전극층(18)이 형성되어 구성되는 것으로, 이의 제조방법을 첨부한 제4도를 참조하여 상세히 설명하면 다음과 같다.FIG. 3 is a cross-sectional structure diagram of the thin film transistor of the present invention. As shown therein, the first metal electrode layer 12 and the anodic oxide film 13, which are gate electrodes, are sequentially formed on the insulating substrate 11, and the anodic oxide film 13 is formed. A silicon oxide film (SiO 2 ) 14 is formed on the silicon oxide film 14, a nitrogen treatment film 15 is formed on the silicon oxide film 14, and an amorphous semiconductor layer 16 is doped on the nitrogen treatment film 15. The amorphous semiconductor layer 17 is sequentially formed, and a second metal electrode layer 18 is formed on the doped amorphous semiconductor layer 17 as a source / drain electrode in ohmic contact with the doped amorphous semiconductor layer 17. It will be described in detail with reference to Figure 4 attached to the manufacturing method thereof as follows.
제4a도 내지 e도는 본 발명 박막트랜지스터의 제조공정도서, 제4a도에 도시한 바와 같이 깨끗하게 세척 및 건조한 절연기판(11)상에 스퍼터링(Sputtering)방법을 이용하여 불순물이 첨가된 알루미늄(Al)을 3000∼3500Å정도로 증착한 후 사진식각(Photolithograhy)공정을 통해 게이트전극인 제1금속전극층(12)을 형성한다.4a to e are manufacturing process drawings of the thin film transistor of the present invention, as shown in FIG. 4a, aluminum (Al) having impurities added thereto by sputtering on a clean and dried insulating substrate 11. Is deposited to about 3000 to 35003 and then the first metal electrode layer 12, which is a gate electrode, is formed through a photolithograhy process.
이때, 일반적으로 순수 알루미늄(Al)은 170∼200℃이상의 열처리 공정에서 힐락현상이 발생됨으로 고온처리 공정에서 사용하기는 곤란하다.At this time, in general, pure aluminum (Al) is difficult to use in the high temperature treatment process because the heel lock phenomenon occurs in the heat treatment process of 170 ~ 200 ℃ or more.
따라서, 상기 제1금속전극층(12)의 알루미늄에 불순물을 포함시키는데, 그 불순물은 Ti, Ta, Sc 등으로 구성되며 1.5 at%이상 함유하게 된다.Therefore, the aluminum of the first metal electrode layer 12 includes an impurity, and the impurity is composed of Ti, Ta, Sc, and the like and contains 1.5 at% or more.
상기와 같이 형성된 제1금속전극층(12)은 호박산, 구연산, 주석산 등을 이용하여 양극산화 처리하여 제4b도와 같이 일부분을 양극산화막(13)으로 형성하는데, 그 양극산화막(13)의 두께는 1000∼2000Å정도로 형성해준다.The first metal electrode layer 12 formed as described above is anodized using succinic acid, citric acid, tartaric acid, and the like to form a portion of the anodized film 13 as shown in FIG. 4B, and the thickness of the anodized film 13 is 1000. Form it at about 2000Å.
이후, 제4c도에 도시한 바와 같이 상기 양극산화막(13)위에 제2절연막인 산화실리콘(SiO2)막(14)을 2000∼4000Å정도로 형성한다.Thereafter, as shown in FIG. 4C, a silicon oxide (SiO 2 ) film 14, which is a second insulating film, is formed on the anodic oxide film 13 at about 2000 to 4000 mW.
이때, 상기 산화실리콘막(14)은 살일렌(SiH4)과 산소(O2)가스를 이용하여 60 0Torr이상의 압력과 400℃이상의 온도에서 증착하게 된다.In this case, the silicon oxide film 14 is deposited at a pressure of 60 0 Torr or more and a temperature of 400 ° C. or more by using a xylene (SiH 4 ) and oxygen (O 2 ) gas.
이와같이 하여 산화실리콘막(14)이 형성되면 질소(N)가 포함된 질소, 암모니아 등의 가스를 플라즈마(Plasma)방전한 후 질소처리하여 그 산화실리콘막(14)표면에 질소처리층(150을 만들어 준다.When the silicon oxide film 14 is formed in this manner, the plasma is discharged after plasma discharge of nitrogen, ammonia, or other gas containing nitrogen (N), and the nitrogen treatment layer 150 is formed on the surface of the silicon oxide film 14. Make it.
이후, 제4d에 도시한 바와 같이 상기 질소처리층(15)이 형성된 산화실리콘막(14)표면에 플라즈마화학기상증착(PECVD)방법으로 수소화된 비정질반도체층(16)과 도핑된비정질반도체층(17)을 연속으로 증착한 다음 상기와 같이 형성된 질소처리층(15), 비정질반도체층(16), 도핑된비정질반도체층(17)을 사진식각공정을 거쳐 건식식각방법으로 동시에 패턴하게 된다.Subsequently, as shown in FIG. 4D, the amorphous semiconductor layer 16 and the doped amorphous semiconductor layer 16 are hydrogenated on the surface of the silicon oxide film 14 on which the nitrogen treatment layer 15 is formed by plasma chemical vapor deposition (PECVD). 17) is continuously deposited, and then the nitrogen treatment layer 15, the amorphous semiconductor layer 16, and the doped amorphous semiconductor layer 17 formed as described above are simultaneously patterned by a dry etching method through a photolithography process.
다음으로 제4e에 도시한 바와 같이, 상기 도핑된비정질반도체(17)위에 스퍼터링(Sputtering)방법으로 금속을 증착한 후 사진식각법을 통해 식각처리하여 소오스/드레인전극인 제2금속전극층(18)패턴을 형성하고, 상기 제2금속전극층(18)이 형성된 후 그 제2금속전극층(18)을 마스크로 사용하여 소오스, 드레인 사이의 상기 도핑된비정질반도체층(17)을 건식식각방법으로 제거하여 본 발명 박막트랜지스터를 제조한다.Next, as shown in FIG. 4E, the metal is deposited on the doped amorphous semiconductor 17 by a sputtering method, and then etched by photolithography to form a second metal electrode layer 18 as a source / drain electrode. After the pattern was formed and the second metal electrode layer 18 was formed, the doped amorphous semiconductor layer 17 between the source and the drain was removed by dry etching using the second metal electrode layer 18 as a mask. The thin film transistor of the present invention is prepared.
이와 같은 제조방법에 있어 다른 실시예로서, 상기 질소처리층(15)을 포함한 산화실리콘막(14)과 양극산화막(13)으로 구성되는 절연막을 양극산화막(13), 상기의 조건으로 형성되는 산화실리콘막(14), 그리고 질화실리콘막(SiNx)으로 3중구성을 갖게 제조할 수도 있다.In another embodiment of the manufacturing method, an insulating film composed of the silicon oxide film 14 including the nitrogen treatment layer 15 and the anodizing film 13 is formed by the anodizing film 13 and oxidation formed under the above conditions. The silicon film 14 and the silicon nitride film (SiNx) may be manufactured to have a triple configuration.
이상에서 설명한 바와 같이 본 발명은 질화실리콘 형성공정을 없애고 양극산화막에 상압에서 증착되는 산화실리콘(SiO2)을 채용함으로써, 박막트랜지스터의 이동도를 1.0㎠/.v.sec 이상 향상됨은 물론 문턱 전압의 안정된 신뢰성향상 효과와, 진공장비를 이용하지 않고 절연막을 형성함으로써, 이물질(Particles)발생이 현저하게 줄어들어 수율 및 생산성이 증가하는 효과가 있다.As described above, the present invention eliminates the silicon nitride forming process and employs silicon oxide (SiO 2 ) deposited at normal pressure in the anodized film, thereby improving the mobility of the thin film transistor by more than 1.0 cm 2 /.v.sec as well as the threshold voltage. The stable reliability of the effect and by forming an insulating film without using a vacuum equipment, the generation of particles (particles) is significantly reduced, thereby increasing the yield and productivity.
Claims (7)
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