JPH02186641A - Manufacture of thin film field-effect transistor element - Google Patents

Abstract

PURPOSE:To improve the yield of the present element by a method wherein a metal protective film is formed on an upper insulating film, the films other than the films, which are located on a gate electrode, are removed and after source and drain electrodes are formed, the metal protective film is removed. CONSTITUTION:A gate electrode 12 is formed of a metal on an insulative substrate 11 and a gate insulating film 13 is formed by a plasma CVD method. Moreover, an amorphous Si layer 14 which is used as an amorphous semiconductor layer and an upper insulating film 15 are deposited in order. Then, unnecessary parts of a metal protective film 1 formed on the film 15 and the film 15 are etched away leaving a pattern only on the gate electrode 12. Here, the exposed surface of the layer 14 is cleaned using hydrofluoric acid and after a source 18 and a drain 19 are formed by performing an etching work on a metal film 17 and an n<+> amorphous Si film 16, which are immediately formed, a part, which is exposed between the source and the drain, of the film 1 is etched. Lastly, an unnecessary part of the layer 14 is etched away. Thereby, an ohmic contact of the source with the drain csn be formed with good reproducibility in the whole substrate and the good uniformity of an ON-current is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film field effect transistor element provided on an insulating substrate, and in particular to a method for manufacturing a thin film field effect transistor element that is easy to manufacture and is suitable for active matrix liquid crystal displays. The present invention relates to a method for manufacturing a field effect transistor element.

[Conventional technology]

Wall-mounted displays are thin panel displays such as color TVs, and research and development is actively being conducted on active matrix liquid crystal displays, in which thin-film field-effect transistors are arrayed on one glass substrate, each as a switch for each pixel. There is. In order to put this display into practical use, it is important to develop a manufacturing method with a large process margin so that manufacturing yield does not decrease even during mass production.

FIG. 2 shows a manufacturing process for a conventional inverted staggered thin film field effect transistor. This conventional manufacturing process will be explained below. A gate electrode 22 made of metal is formed on an insulating substrate 21 (FIG. 2(a)). Next, an insulating film such as silicon nitride or silicon oxide is formed as the gate insulating film 23 by plasma CVD. moreover,
For example, an amorphous semiconductor film 5i24 and an upper insulating film 25 are sequentially deposited (FIG. 2(b)). This upper insulating film 25 is made of a silicon nitride film or a silicon oxide film, similar to the gate insulating film. Next, unnecessary portions of the upper insulating film 25 are removed by etching, leaving a portion on the gate electrode 22 (FIG. 2(C)). Here, the surface of the exposed amorphous Si 24 is cleaned using hydrofluoric acid, and the n+ amorphous 5i 26 and metal film 27 are immediately formed (FIG. 2(d)). Metal film 27 and n+ amorphous Si
By etching 26, a source 28 and two trains are formed (FIG. 2(e)). Finally, the unnecessary portions of the amorphous layer 5i24 are removed by etching to complete the 1 helangister.

[Problem to be solved by the invention]

There are two problems with the conventional manufacturing process for reverse staggered thin film field effect transistors. The first problem is
This is a hydrofluoric acid treatment for cleaning the surface of the amorphous Si 24 before forming the n+ amorphous 5i 26. This is done in order to remove the oxide film etc. formed on the amorphous Si surface and improve the ohmic properties of the source/train contact. However, since the upper insulating film 25 is etched by hydrofluoric acid in this step, the concentration of hydrofluoric acid must be reduced and the processing time must be shortened. Therefore, depending on the surface condition of the amorphous Si, the hydrofluoric acid treatment may be insufficient, making it impossible to form an ohmic contact, resulting in problems with poor reproducibility and yield.

The second problem is that the n+ amorphous Si shown in Fig. 2(e)
26 is in the process of etching to form the source train. N+ amorphous Si etching is normally performed by dry etching, but at this time the upper insulating film 25 is also etched. Therefore, if the control and uniformity of the etching process during dry etching is poor, the upper insulating film 2
There was a problem where all 5's were etched.

The present invention aims to solve these problems and manufacture thin film field effect transistors with high yield.

[Means to solve the problem]

The method for manufacturing a thin film field effect transistor element of the present invention includes sequentially forming a gate electrode, a gate insulating film, an amorphous semiconductor film, and an upper insulating film on an insulating substrate, and In the method for manufacturing a thin film field effect transistor device in which source and drain electrodes are formed after removing an insulating film, a metal protective film is formed on the upper insulating film, and the metal protective film is removed at a portion other than on the gate electrode. The method is characterized in that the film and the upper insulating film are removed, the source and drain electrodes are formed, and finally the metal protective film is removed.

[Effect]

The present invention is to form a metal protective film on the upper insulating film in order to prevent the upper insulating film from being etched during the hydrofluoric acid treatment or dry etching process, and to use this metal protective film as an etching stopper. There are characteristics.

First, the manufacturing process of the inverted staggered thin film field effect transistor of the present invention will be explained. FIG. 1 shows the manufacturing process of the present invention. A gate electrode 12 is formed of metal on an insulating substrate 11 (FIG. 1 (a)). Next, an insulating film such as silicon nitride or silicon oxide is formed as a gate insulating film 13 by plasma CVD. ,
Amorphous 5i14. as the amorphous semiconductor layer. The upper insulating film 15 is sequentially deposited (FIG. 1(b)). This upper insulating film 15 is made of a silicon nitride film or a silicon oxide film, similar to the gate insulating film. In the present invention, the upper insulating film 15
In order to prevent etching by hydrofluoric acid treatment or dry etching, a metal protective film 1 is formed on the upper insulating film 15. Next, unnecessary portions of the metal protective film 1 and the upper insulating film 25 are removed by etching, leaving only the pattern on the gate electrode 22 (FIG. 1C). This etching can be performed with good reproducibility and controllability, for example, by etching the metal protective film by wet etching and etching the upper insulating film by dry etching.

Here, the surface of the exposed amorphous Sil 4 was cleaned using hydrofluoric acid, and the surface of the n+ amorphous Sil 4 was immediately cleaned.
A source 18 and a drain are formed by etching the metal film 17 and the n+ amorphous layer 16 (FIG. 1(d)).
Figure (e)). Further, in order to prevent a short circuit between the source and the drain, the exposed portion of the metal protective film 1 between the source and the drain is etched. Finally, unnecessary portions of the amorphous layer 5i14 are removed by etching to complete the transistor.

Here, the role of the metal protective film 1 will be explained in detail.

In FIG. 1(c), the amorphous Si surface that appears after removing the upper insulating film 15 has organic contamination and an oxide film formed by the photoresist process. For this reason, if source and train electrodes are formed without special surface treatment, the contact resistance will increase even if an n+ layer is used.
It does not become an ohmic electrode. The cleaning process of the surface of the amorphous 5i14 is essential for obtaining good transistor characteristics with good reproducibility. Hydrofluoric acid treatment is a reliable cleaning process suitable for mass production. This is a very effective process because surface contamination can be removed by etching the oxide film on the surface with hydrofluoric acid at an appropriate concentration.

However, since the etching rate of silicon nitride films and silicon oxide films produced by plasma CVD with hydrofluoric acid is very high, the upper insulating film is etched even when the hydrofluoric acid treatment is sufficient to clean the Si surface. Up to now, the cleaning process has been carried out by reducing the concentration of hydrofluoric acid to the extent that the upper insulating film is not lost and by shortening the processing time. Therefore, the reproducibility of contact characteristics is poor and non-uniformity occurs within the surface, resulting in a decrease in yield. Therefore, by forming a metal protective film, which is difficult to be etched with hydrofluoric acid, on the upper insulating film, the hydrofluoric acid treatment can be carried out sufficiently. As a result, the uniformity and reproducibility of transistor characteristics are improved, which is extremely effective in improving yield.

This metal protective film may be made of any material as long as it has a slow etching rate with respect to hydrofluoric acid, such as chromium.

In addition, n+ amorphous 5 shown in FIG. 1(e)
This metal protective film is also effective in the process of etching i16. Although dry etching is used in this process, the upper insulating film is also etched. Therefore,
If the etching time is too long, a defect occurs in which the upper insulating film is also removed. However, in general, metals are difficult to be etched by CF4 gas, which etches Si.
Stop at. Therefore, since the upper insulating film is not etched at all, the etching time may be long even if there is non-uniformity in the etching. This process also improves yield.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

A borosilicate glass plate was used as the insulating substrate 11. After cleaning, a chromium film with a thickness of 1100 nm is formed on the insulating substrate 11 by sputtering, and a gate electrode 12 is formed by photolithography. Although chromium is used here as the gate electrode material, other materials such as aluminum, tantalum, and other metals may be used.

Next, a gate insulating film 13, an amorphous film 14, and an upper insulating film 15 are sequentially formed using a plasma CVD method.

A silicon nitride film with a thickness of 400 nm was used as the gate insulating film 13. The film forming conditions were as follows: SiH4 and NH3 were used as source gases, flow rate ratio was 1Nia, vacuum degree was 100 Pa, high frequency power density was 0.2 W/cm2, and substrate temperature was 250°C. Under these conditions, a good optical band gap of 5.4 eV was obtained. A silicon nitride film having insulating properties is obtained. Although a silicon nitride film is used here, an insulating film made of other insulating materials such as silicon nitride, tantalum pentoxide, etc. may also be used. amorphous 5t14
uses SiH4 gas as raw material, vacuum degree 100 Pa, high frequency power density 0.02 W/cm2, substrate temperature 250 Pa.
A film with a thickness of 1100 nm was formed under conditions of .degree. Next, as the upper insulating film 15, a silicon nitride film with a thickness of 1100 nm was formed under the same conditions as the gate insulating film 13. The upper insulating film 15 may be made of other insulating materials. Here, we used a plasma CVD method to form three layers: gate insulating film, amorphous Si, and upper insulating film.
Although a layer is formed, other film forming methods such as a photo-CVD method and a sputtering method may be used.

Next, as an etching prevention layer for the upper insulating film, which is a feature of the present invention, chromium 1 was etched to a thickness of 30 mm using a sputtering method.
0 nm is formed. The material may also be other metals such as tantalum, tungsten, etc. The film may be formed by other methods such as vapor deposition.

Next, a photoresist film is formed in the shape of the gate electrode using photolithography, and using this photoresist film as a mask, chromium 1 is etched using a wet etching method, followed by dry etching using CF4 gas. The upper insulating film 15 is patterned by an etching method.

After peeling off the photoresist film, in order to clean the surface of the amorphous 5i14, a hydrofluoric acid treatment is performed by immersing it in a 1% HF solution for 1 minute. Conventionally, in order to avoid etching the upper insulating film 15, it was only possible to immerse the upper insulating film 15 in a 0.05% IF solution for 30 seconds.

Immediately after this hydrofluoric acid treatment, a metal film 17 made of n+ amorphous Sil 6 is deposited using a plasma CVD method, and a metal film 17 made of chromium, which will become the source/drain electrode, is deposited using a sputtering method.
form. The deposition of n+ amorphous Sil 6 was performed using P
Si tl 4 mixed with 0.5% H3 was used as the raw material waste, vacuum degree was 100 Pa, and high frequency power density was 0.02 W.
/cm2, thickness 50nm at a substrate temperature of 250℃
A film was formed. The film thickness of chromium-17 is 150 nm.

Here, a photoresist film is formed in the shape of a source/drain by photolithography, and first, chromium 17, which will become an electrode, is wet-etched. Next, the n+ amorphous 5i16 is patterned by dry etching. At this time, there is no fear that the upper insulating film 15 will be etched even if the etching time is increased somewhat. Then, the chromium film 1 protecting the upper insulating film 15 is removed by wet etching, and the source/drain 18.1 is etched.
9 is formed. Finally, unnecessary portions of the amorphous 5i14 are removed by etching to complete the transistor.

A thin film field effect transistor manufactured by such a manufacturing process can be formed with a high yield while leaving an upper insulating film. Furthermore, the ON current distribution was within 30% within a 250 mm square area within the substrate, and good uniformity was obtained.

〔Effect of the invention〕

In the present invention, by using a metal protective film as an etching prevention layer for the upper insulating film, the hydrofluoric acid treatment before forming the n+ layer can be carried out sufficiently. As a result, the source and
It becomes possible to form an ohmic contact with the train, and good uniformity of ON current can be obtained. Further, the process margin for etching the n+ amorphous Si on the upper insulating film is increased, and the yield is also improved.

FIG. 2 shows a manufacturing process diagram of a conventional thin film field effect transistor.

11.21... Insulating substrate, 12.22... Gate electrode, 13.23... Gate insulating film, 14.24...
・Amorphous Si, 15.25... Upper insulating film, 1
...Metal protective film, 16.26...n+ amorphous Si, 17.27...Metal film, 18.28...Source, 19.29...Drain.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

FIG. 1 shows a thin film field effect transistor door of the present invention. figure shoulder ?

Claims (1)

[Claims] A gate electrode, a gate insulating film, an amorphous semiconductor film, and an upper insulating film are sequentially formed on an insulating substrate, and after removing the upper insulating film in a portion other than on the gate electrode, a source and a drain electrode are formed. In the method for manufacturing a thin film field effect transistor element, a metal protective film is formed on the upper insulating film, the metal protective film and the upper insulating film are removed in a portion other than over the gate electrode, and the metal protective film and the upper insulating film are removed from the source and drain regions. A method for manufacturing a thin film field effect transistor element, comprising the steps of forming an electrode and finally removing the metal protective film.