KR20080105322A - Method of fabricating thin film transistor substrate and method of fabricating liquid crystal display using the same - Google Patents

Abstract

A method for manufacturing TFT substrate, and a method for manufacturing an LCD panel using the same are provided to improve the production yield and display characteristics. Gate wiring parts(121,GL,CL,SE1) include a gate line(GL) in the top of the substrate and gate electrode(121). A step for processing with plasma for 1 20 second or 120 second The surface of the gate wiring part is processed with plasma for 20 seconds to 120 seconds for removing the oxide layer on the gate wiring part. A gate insulating layer which covers the gate wiring part is formed on the substrate. The data line, source electrode(124), and a drain electrode(125) are formed on the gate isolation layer.

Description

Thin film transistor substrate manufacturing method and liquid crystal display panel manufacturing method using the same {METHOD OF FABRICATING THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING LIQUID CRYSTAL DISPLAY USING THE SAME}

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3A to 3I are process diagrams illustrating a process of manufacturing the thin film transistor substrate illustrated in FIG. 2.

4 is a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor substrate illustrated in FIG. 1.

FIG. 5 is a flowchart illustrating a method of manufacturing the liquid crystal display panel illustrated in FIG. 4.

* Description of the symbols for the main parts of the drawings *

100-thin film transistor substrate 300-color filter substrate

400-Liquid Crystal Layer 500-Liquid Crystal Display Panel

The present invention relates to a thin film transistor substrate manufacturing method and a liquid crystal display panel manufacturing method using the same, and more particularly, to a thin film transistor substrate manufacturing method and a liquid crystal display panel manufacturing method using the same can improve the yield of the product.

In general, a liquid crystal display panel includes a thin film transistor (TFT) substrate in which thin film transistors are formed in an array, a color filter substrate on which a color filter is formed, and a liquid crystal layer interposed between the TFT substrate and the color filter substrate. It includes.

The TFT substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of TFTs electrically connected to the gate lines and the data lines. The TFT includes a gate electrode extending from the gate line, an active layer, a source electrode and a drain electrode extending from the data line. The gate wiring layer including the gate electrode and the gate line includes one of a single layer structure, a double layer structure, and a triple layer structure.

The gate wiring layer of the double layer structure includes a first layer formed of molybdenum (Mo) or molybdenum alloy and a second layer formed of copper (Cu). Copper has a higher specific resistance to hillock than aluminum because it has a specific resistance of 30% or more lower than that of aluminum (Al), and is more resistant to electromigration than aluminum. However, copper is used as the second layer formed on the upper surface of the first layer because of its low adhesion to glass and very high reactivity with silicon.

However, since copper has a high degree of reaction with oxygen, oxides are easily formed, and thus, copper is easily oxidized by air or water in the process of forming the gate wiring layer, thereby losing the specific resistivity of copper. Therefore, the retention time must be managed for each unit process of forming the TFT substrate, and much attention must be paid to the wet etching process or the cleaning process using water. In addition, copper and monosilane (SiH ₄ ) gases react with each other to form a silicon compound (Cu-Silicide) on the surface of copper during the process of forming a gate insulating film and a protective film formed on the gate wiring layer. In particular, since the high temperature process increases the thickness of the silicon compound, the resistance of the gate wiring layer also increases.

On the other hand, the gate wiring layer of the triple layer structure further includes a third layer made of molybdenum or molybdenum alloy on the upper surface of the second layer made of copper. As a result, contamination of the second layer made of copper is prevented, and formation of a silicon compound is prevented, so that the resistivity of the gate wiring layer can be maintained, and a low resistance gate wiring layer can be formed.

However, since the third layer is added to the gate wiring layer of the triple layer structure, the process time increases and it is difficult to control the etching degree during the wet etching.

An object of the present invention is to provide a method for manufacturing a thin film transistor substrate that can improve the yield of the product and the display characteristics.

It is also an object of the present invention to provide a method for manufacturing a liquid crystal display panel using the above-described method for manufacturing a thin film transistor substrate.

A thin film transistor substrate manufacturing method according to one feature for realizing the object of the present invention described above is as follows. First, a gate wiring portion including a gate line and a gate electrode is formed on a substrate. The surface of the gate wiring portion is plasma treated for 20 to 120 seconds to remove the oxide layer on the gate wiring portion. A gate insulating film covering the gate wiring part is formed on the substrate. Forming a data line and a source and a drain electrode on the gate insulating layer.

Specifically, the gate wiring part is formed through the following process. First, a first gate layer is formed on the substrate, and a second gate layer is formed on the first gate layer. The gate wiring part is formed by patterning the first and second gate layers. Here, the first gate layer includes any one of molybdenum and molybdenum alloy, and the second gate layer includes copper.

Meanwhile, the plasma treatment is performed using hydrogen (H ₂ ) gas, and the plasma treatment time is more than 60 seconds and 120 seconds or less, and the power density provided for the plasma treatment is 300 mW / cm 2 to 500 mW / cm 2. to be.

In addition, the liquid crystal display panel manufacturing method according to one feature for realizing the above object of the present invention is as follows. First, a thin film transistor substrate is formed, and a common electrode is formed on the second base substrate. The thin film transistor substrate and the second base substrate are coupled to face each other. A liquid crystal layer is formed between the thin film transistor substrate and the second base substrate.

Specifically, the thin film transistor substrate is made through the following process. First, a gate wiring part including a gate line and a gate electrode is formed on a first base substrate. The surface of the gate wiring portion is plasma treated for 20 to 120 seconds to remove the oxide layer on the gate wiring portion. A gate insulating layer covering the gate wiring part is formed on the substrate, and a data line, a source, and a drain electrode are formed on the gate insulating layer.

According to the method of manufacturing the thin film transistor substrate and the method of manufacturing the liquid crystal display panel using the same, an oxide formed by oxidizing copper may be removed by plasma treatment when forming the gate wiring part. Accordingly, the thin film transistor substrate can prevent the specific resistance of the gate wiring portion from rising, improve the yield of the product, and improve display characteristics.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the thin film transistor substrate 100 of the present invention includes a first base substrate 110, a gate line GL, a data line DL, and a thin film transistor (hereinafter, referred to as TFT). And a gate electrode 130, a gate insulating layer 130, a passivation layer 140, an organic insulating layer 150, and a pixel electrode 160.

The first base substrate 110 is a substrate made of a material capable of transmitting light. The gate line GL is formed on an upper surface of the first base substrate 110. The gate line GL extends in the first direction D1 and transmits a gate signal.

The data line DL is formed on the first base substrate 110 on which the gate line GL is formed. The data line DL extends in a second direction D2 perpendicular to the first direction D1. The data line DL is insulated from and crosses the gate line GL and transmits a data signal.

The TFT 120 is positioned in the pixel area PA defined by the gate line GL and the data line DL, and switches the pixel voltage. In detail, the TFT 120 includes a gate electrode 121 branched from the gate line GL, an active layer 122 and an ohmic contact layer 123 sequentially disposed on the gate electrode 121. And a source electrode 124 and a drain electrode 125 provided on an upper surface of the ohmic contact layer 123. The gate electrode 121 includes a first gate electrode 121a formed on an upper surface of the first base substrate 110 and a second gate electrode 121b formed on an upper surface of the first gate electrode 121a. The first gate electrode 121a is made of molybdenum (Mo) or molybdenum alloy, and the second gate electrode 121b is made of copper (Cu).

Although not shown in the drawing, the gate line GL is also formed of a double layer in the same manner as the gate electrode 121, and is formed together in the process of forming the gate electrode 121.

In this embodiment, the source and drain electrodes 124 and 125 may be formed as a single layer, but may be formed as a double layer or a triple layer, and the data line DL may be the source and drain electrodes 124 and 125. Have the same structure as

The drain electrode 125 of the TFT 120 is electrically connected to the pixel electrode 130. The pixel electrode 130 is provided in the pixel area PA and receives the pixel voltage.

Meanwhile, the TFT substrate 100 further includes a common voltage line CL for transmitting a common voltage and first and second storage electrodes SE1 and SE2 forming a storage capacitance. The common voltage line CL extends in the same first direction D1 as the gate line GL, is formed on the same layer as the gate line GL, and is spaced apart from the gate line GL. Located.

The first storage electrode SE1 is branched from the common voltage line CL to be formed in the pixel area PA. The first storage electrode SE1 is formed of a double layer like the gate electrode 121. That is, the first storage electrode SE1 includes a first electrode layer SE1a formed on an upper surface of the first base substrate 110 and a second electrode layer SE1b formed on an upper surface of the first electrode layer SE1a. Although not shown in the drawing, the common voltage line CL is formed as a double layer like the first storage electrode SE1 and is formed together in the process of forming the first storage electrode SE1.

The second storage electrode SE2 is provided on the first storage electrode SE1. The second storage electrode SE2 extends from the drain electrode 125 of the TFT 120 and is spaced apart from the first storage electrode SE1. The second storage electrode SE2 is electrically connected to the pixel electrode 130, and forms the storage capacitance between the first storage electrode SE1 and the second storage electrode SE2.

In addition, the TFT substrate 100 further includes the gate insulating layer 140, the passivation layer 150, and the organic insulating layer 160. The gate insulating layer 140 may include a first gate insulating layer 141 having a first uniformity, a second gate insulating layer 142 having a second uniformity lower than the first uniformity, and a third gate having the first uniformity. An insulating layer 141 is included. The first gate insulating layer 141 is formed on the first base substrate 110 to cover the gate electrode 121, the gate line GL, and the common voltage line CL. The second gate insulating layer 142 is formed on an upper surface of the first gate insulating layer 141, and the third gate insulating layer 143 is formed on an upper surface of the second gate insulating layer 142.

The passivation layer 150 is formed on the third gate insulating layer 143 to cover the TFT 120, and the organic insulation layer 160 is formed on the passivation layer 150. The passivation layer 150 and the organic insulating layer 160 are partially removed to form a contact hole CH, and the pixel electrode 130 formed on the organic insulating layer 160 is formed through the contact hole CH. The second storage electrode SE2 is electrically connected to the second storage electrode SE2.

Hereinafter, a process of forming the TFT substrate 100 will be described in detail with reference to the accompanying drawings.

3A to 3I are process diagrams illustrating a process of manufacturing the thin film transistor substrate illustrated in FIG. 2.

3A and 3B, first and second metal layers 211 and 212 are sequentially formed on an upper surface of the first base substrate 110. Here, the first metal layer 211 is made of molybdenum or molybdenum alloy, and the second metal layer 212 is made of copper.

The gate line GL, the gate electrode 121, the common voltage line CL, and the first storage electrode SE1 are formed by patterning the first and second metal layers 211 and 212. Hereinafter, the gate line GL, the gate electrode 121, the common voltage line CL, and the first storage electrode SE1 may be connected to the gate wiring part 121, GL, CL, and SE1 for convenience of description. It is called).

Referring to FIGS. 3A and 3C, since the second metal layer 212 is made of copper, native oxide NO may be formed on the upper surface of the gate line 121, GL, CL, and SE1. Easy to form That is, an upper layer of the gate wiring parts 121, GL, CL, and SE1, for example, the second gate electrode 121b of the gate electrode 121 and the second electrode layer SE1b of the first storage electrode SE1. Since silver is made of copper, oxide (NO) made of CuO or Cu ₂ O may be formed on the top surface of the gate wiring part 121, GL, CL, and SE1. In order to remove the oxide NO, the gate wirings 121, GL, CL, and SE1 are plasma treated.

Referring to FIG. 3C, the plasma treatment process is performed. First, the electrode unit 221 is disposed on the first base substrate 110 on which the gate wiring units 121, GL, CL, and SE1 are formed. The electrode unit 221 is connected to the power supply unit 222, and receives a negative voltage from the power supply unit 222.

Although not shown in the drawing, the first base substrate 110 is mounted on a susceptor, and the first base substrate 110 and the electrode part 221 are provided in a sealed chamber.

The plasma gas PG is injected into the chamber, and the electrode unit 221 generates the plasma P in response to the plasma gas PG. As the plasma gas PG, ammonia (NH ₃ ) gas or hydrogen (H ₂ ) gas is used.

When the ammonia gas is used as the plasma gas PG, the plasma treatment time is about 20 seconds to about 120 seconds, and the power density provided to the electrode portion 221 is about 150 kW / cm 2 to about 200 kW /. Cm 2. The ammonia gas reacts with the oxide (NO) to reduce oxygen contained in the oxide (NO). Accordingly, the oxide NO is removed and the specific resistance values of the upper layers 121b and SE1b of the gate wiring parts 121, GL, CL, and SE1 are reduced.

Referring to FIG. 3D, a first gate insulating layer 141 having a first uniformity is formed on the first base substrate 110, and the second gate is formed on an upper surface of the first gate insulating layer 141. After the insulating layer 142 is formed, the third gate insulating layer 143 is formed on an upper surface of the second gate insulating layer 142. Here, the first and third gate insulating layers 141 and 143 have a denser density than the second gate insulating layer 142. The density of each of the first to third gate insulating layers 141 to 143 may be controlled by the formation conditions of the first to third gate insulating layers 141 to 143, for example, a deposition rate.

Table 1 below shows the change in the resistivity of the gate lines 121, GL, CL, and SE1 according to the plasma treatment and the deposition of the first to third gate insulating layers 141 to 143.

Mosquito board number Specific resistance of gate wiring part After the gate wiring part is formed After TFT Substrate Formation One 2.56 2.72 2 2.56 2.70 3 2.56 2.27 4 2.58 2.28 5 2.57 2.63 6 2.58 2.65 7 2.58 2.26 8 2.59 2.26

Table 1 shows the results obtained by varying the process conditions for each mother substrate for forming the TFT substrate 100, and then dividing the specific resistance of the upper layer of the gate wiring portion by immediately after forming the gate wiring portion and immediately after completing the TFT substrate. .

Referring to FIGS. 3C, 3D, and 1, the first and second mother substrates may have a first uniformity having the first uniformity without the plasma treatment after the gate wirings 121, GL, CL, and SE1 are formed. Mother substrates sequentially formed with a gate insulating layer and a second gate insulating layer having a second uniformity lower than the first uniformity. The third and fourth mother substrates are subjected to plasma treatment of the gate wirings 121, GL, CL, and SE1 using the ammonia gas for about 20 seconds, and then the first to third gate insulating layers 141 to 143 are disposed. The mother substrates formed. The fifth and sixth mother substrates are mother substrates in which the first to third gate insulating layers 141 to 143 are formed without the plasma processing of the gate wirings 121, GL, CL, and SE1. The seventh and eighth mother substrates process the gate wirings 121, GL, CL, and SE1 by plasma for about 120 seconds using the ammonia gas, and then cover the first to third gate insulating layers 141 to 143. The mother substrates formed.

The change of the specific resistance value corresponding to the upper layer of the gate wiring part for each mother substrate is described. After forming the gate wiring parts 121, GL, CL, and SE1, the first, second, fifth, and fifth plasma treatments are not performed. In the sixth mother substrate, the resistivity of the gate wiring parts 121, GL, CL, and SE1 increased by about 10% from the initial stage. On the other hand, the third, fourth, seventh, and eighth mother substrates in which the gate wirings 121, GL, CL, and SE1 are plasma treated have a specific resistance of the gate wirings 121, GL, CL, and SE1. It is about 15% less than this initial period.

As described above, since the plasma treatment prevents the formation of oxide N0 on the upper surface of the gate wiring parts 121, GL, CL, and SE1, the specific resistance value of the gate wiring parts 121, GL, CL, and SE1 is prevented. Can be reduced.

However, when the plasma treatment is performed using the ammonia gas, staining may occur on the gate lines 121, GL, CL, and SE1 according to the plasma treatment time. That is, in the process of reducing the ammonia to copper oxide (NO), nitrogen of the ammonia reacts with oxygen to form copper nitride (CuN), and thus, the volume of the gate wirings 121, GL, CL, and SE1 is reduced. Increases and staining occurs.

On the other hand, since hydrogen has a smaller atom size than nitrogen, when the hydrogen gas is used as the plasma gas PG, the stain of the gate wirings 121, GL, CL, and SE1 may be prevented. Specifically, since the hydrogen atom is smaller than the nitrogen atom, it is possible to prevent the volume of the gate wirings 121, GL, CL, and SE1 from expanding during the plasma processing. When the hydrogen gas is used as the plasma gas PG, the plasma treatment time is greater than about 60 seconds and about 120 seconds or less, and the power density provided to the electrode part 221 is about 300 kW / cm 2 to about 500 kW. / Cm 2.

Table 2 below shows a change in the resistivity of the gate wirings 121, GL, CL, and SE1 according to the plasma treatment using the hydrogen gas.

Mosquito board number Specific resistance of gate wiring part After the gate wiring part is formed After TFT Substrate Formation 9 2.57 2.63 10 2.58 2.65 11 2.58 2.26 12 2.59 2.26

Referring to FIGS. 3C, 3D, and 2, the ninth and tenth mother substrates plasma the gate wirings 121, GL, CL, and SE1 for about 60 seconds, and then, the first to third gates. The mother substrates having the insulating layers 141 to 143 formed thereon. The eleventh and twelfth mother substrates are mother substrates on which the first to third gate insulating layers 141 to 143 are formed after plasma processing the gate wiring portion for about 120 seconds. Here, the power density provided to the electrode portion 221 for the plasma treatment is about 500 mW / cm 2.

Looking at the specific resistance change of the gate wirings 121, GL, CL, and SE1 for each of the ninth to 12th mother substrates, the ninth to 10th mother substrates may include the gate wirings 121, GL, CL, and SE1. The specific resistance value of increased from the initial stage. On the other hand, in the eleventh and twelfth mother substrates, specific resistance values of the gate wiring parts 121, GL, CL, and SE1 are reduced by about 15%. As a result similar to the case of plasma treatment using the ammonia gas, it is possible to prevent an increase in the specific resistance of the gate wirings 121, GL, CL, and SE1 due to the oxidation of copper.

As described above, since the TFT substrate 100 can remove copper oxide through plasma processing of the gate wiring parts 121, GL, CL, and SE1, the gate wiring part 121, GL, CL, SE1) can prevent the heel lock, improve the yield of the product, and improve the display characteristics.

Referring to FIG. 3E, the active layer 122 and the ohmic contact layer 123 are sequentially formed on the gate insulating layer 140 to correspond to the gate electrode 121.

3F and 3G, a third metal layer 230 is formed on the gate insulating layer 140 on which the ohmic contact layer 123 is formed, and the third metal layer 230 is patterned to form the source electrode. 124, the drain electrode 125, and the second storage electrode SE2 are formed. As a result, the TFT 120 is formed on the first base substrate 110. Although not shown, the data line DL (see FIG. 1) is also formed in the process of forming the source electrode 124 by patterning the third metal layer 230.

Referring to FIG. 3H, the passivation layer 150 and the organic insulating layer 160 are sequentially formed on the gate insulating layer 140. The protective layer 150 and the organic insulating layer 160 are partially removed to form the contact hole CH partially exposing the second storage electrode SE2.

2 and 3I, the transparent electrode layer 240 is deposited on the upper surface of the organic insulating layer 160, and the pixel electrode 130 is formed by patterning the transparent electrode layer 240.

4 is a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor substrate illustrated in FIG. 1.

Referring to FIG. 4, the liquid crystal display panel 500 of the present invention includes a TFT substrate 100, a color filter substrate 300 facing the TFT substrate 100, and the TFT substrate 100 and the color filter substrate. It includes a liquid crystal layer 400 interposed between the (300).

The TFT substrate 100 has the same configuration as the TFT substrate 100 shown in Figs. 1 and 2, and the formation method thereof is also the same. Therefore, the reference numerals are written together, and the detailed description thereof is omitted.

The color filter substrate 300 is provided on the TFT substrate 100. The color filter substrate 300 includes a second base substrate 310, a color filter layer 320, an overcoat layer 330, and a common electrode 340. The color filter layer 320 includes a color filter 321 that expresses a predetermined color using light and a black matrix 322 that blocks the light, and is formed on the second base substrate 310. The overcoat layer 330 is formed on the upper surface of the color filter layer 320 to planarize the color filter substrate 300. The common electrode 340 is formed on an upper surface of the overcoat layer 330, faces the pixel electrode 130 with the liquid crystal layer 400 therebetween, and receives a common voltage.

The liquid crystal layer 400 is interposed between the TFT substrate 100 and the color filter substrate 300 and according to an electric field formed between the TFT substrate 100 and the color filter substrate 300. Adjust the transmittance of the light.

FIG. 5 is a flowchart illustrating a method of manufacturing the liquid crystal display panel illustrated in FIG. 4.

4 and 5, first, the TFT substrate 100 is formed (step S110). The process of forming the TFT substrate 100 is the same as the process of forming the TFT substrate 100 shown in FIGS. 3A to 3I.

The color filter 321 and the black matrix 322 are formed on the second base substrate 310 (step S120).

Subsequently, the overcoat layer 330 is formed on the second base substrate 310 to cover the color filter 321 and the black matrix 322 (step S130).

The color filter substrate 300 is completed by forming the common electrode 340 on the overcoat layer 330 (step S140).

After the TFT substrate 100 and the color filter substrate 300 are disposed to face each other, the TFT substrate 100 and the color filter substrate 300 are combined (step S150).

Subsequently, the liquid crystal layer 400 is formed between the TFT substrate 100 and the color filter substrate 300 (step S160). As a result, the liquid crystal display panel 500 is completed.

According to the present invention described above, the oxide film formed on the upper surface of the gate wiring portion is removed by performing plasma treatment when forming the gate wiring portion of the double layer structure including copper. Accordingly, it is possible to prevent the specific resistance of the gate wiring portion from rising due to the oxidation of copper, to improve the yield of the product, and to improve the display quality.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (10)

Forming a gate wiring portion including a gate line and a gate electrode on the substrate; Plasma treating the surface of the gate wiring portion for 20 to 120 seconds to remove the oxide layer on the gate wiring portion; Forming a gate insulating film covering the gate wiring part on the substrate; And Forming a data line and a source and a drain electrode on the gate insulating layer. The method of claim 1, wherein the forming of the gate wiring part comprises: Forming a first gate layer on the substrate; Forming a second gate layer on an upper surface of the first gate layer; And And forming the gate wiring part by patterning the first and second gate layers. The method of claim 2, wherein the first gate layer comprises any one of molybdenum and molybdenum alloy, and the second gate layer comprises copper. The method of claim 3, wherein the plasma processing is performed using hydrogen (H ₂ ) gas. The method of claim 4, wherein the plasma processing time is greater than 60 seconds and less than 120 seconds. The method of claim 4, wherein the power density provided for the plasma treatment is 300 kW / cm 2 to 500 kW / cm 2. The method of claim 3, wherein the plasma treatment is performed using ammonia (NH ₃ ) gas. The method of claim 3, wherein the power density provided for the plasma treatment is 150 kW / cm 2 to 200 kW / cm 2. The method of claim 3, wherein the forming of the gate insulating layer is performed by: Forming a first insulating layer having a first uniformity on the substrate on which the gate electrode and the gate line are formed; Forming a second insulating layer having a second uniformity lower than the first uniformity on an upper surface of the first insulating layer; And And forming a third insulating layer having the first uniformity on an upper surface of the second insulating layer. Forming a thin film transistor substrate; Forming a common electrode on the second base substrate; Coupling the thin film transistor substrate and the second base substrate to face each other; And Forming a liquid crystal layer between the thin film transistor substrate and the second base substrate; Forming the thin film transistor substrate, Forming a gate wiring part including a gate line and a gate electrode on the first base substrate; Plasma treating the surface of the gate wiring portion for 20 to 120 seconds to remove the oxide layer on the gate wiring portion; Forming a gate insulating layer covering the gate wiring part on the substrate; And Forming a data line, a source, and a drain electrode on the gate insulating layer.

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