JPH03292558A - Shared memory controller - Google Patents

Abstract

PURPOSE:To evade such a case where the address switching time easily affects the cycle time by accepting the memory access request given from a CPU to be selected even at the clock edge where the memory cycle ends for changeover of an address switch signal and starting the memory cycle at the next clock edge. CONSTITUTION:The precharging time (needed for recovery of the contents of a read-out memory cell) of a dynamic memory 4 and the address given to the memory 4 are not required at the end of a memory working state. In this respect, the memory access request given from a CPU 1 (2) to be selected is accepted even at the end of the memory working state. Then the address switch signal is switched to the CPU 1 (2) to be selected. Thus, an address signal is stabilized during the precharging time and the next memory working state is set. As a result, the address switching time never affects the CPU access time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a shared memory control device that allows a plurality of CPUs to access the same dynamic memory in a time-sharing manner.

(Prior art) In order to shorten the access time to memory and increase the instruction execution speed of the CPU, the CPU status signal output (
When the CPU (which indicates what the CPU is trying to do to the outside world) becomes active, this is detected by the active edge of the memory control unit's clock, which is synchronized with the CPU's operating clock, and a memory cycle is started at that edge. .

However, in the case of a shared memory control device that allows the first CPU and the second CPU to access the same dynamic memory in a time-sharing manner, the address signal output from the first CPU and the address output from the second CPU It is necessary to first change the address switching signal to switch the signal depending on which CPU is accessing it, and then generate a memory cycle while the address signal is stable, ensuring a timing margin for the address to the dynamic memory. There is a conflict between shortening the memory access time and shortening the memory access time.

(Problems to be Solved by the Invention) Conventionally, there has been a problem in that ensuring a timing margin for addresses to dynamic memory and shortening memory access time conflict with each other.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a shared memory control device in which address switching time does not easily affect memory cycle time.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides: 1. A plurality of CPUs.
The selected C
It is characterized in that a memory access request from the PU is also accepted at the clock edge at which the memory cycle ends, the address switching signal is switched, and the memory cycle is started at the next clock edge.

(Function) The present invention provides a dynamic memory precharge time (the time required to recover the contents of a read memory cell).
Focusing on the fact that the address to the dynamic memory is not required at the end of the memory operation state, it accepts a memory access request from the selected CPU even at the end of the memory operation state, and then selects an address switching signal. Instead of the CPU side, the address signal is stabilized during the precharge time and then the memory operation state is entered.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram relating to an example of sequence control in FIG. 1, and FIG. 3 is a timing diagram relating to sequence control of a conventional shared memory control device. be.

That is, in FIG. 1, the address signal of the first CPUI and the address signal of the second CPU2 are sent to the multiplexer (
MUX) 3, and the output address signal of this multiplexer 3 is applied to a dynamic memory (DRAM) 4. The status signal (CAD
S) and the status signal (DSO
・DSI) is applied to the shared memory control device 5, and an operating clock (CLK) is applied to this shared memory control device 5. A row address strobe signal (RAS) and a column address strobe signal (CAS) from the shared memory controller 5 are applied to the dynamic memory 4;
The address switching signal from the shared memory control device 5 (
C/D) and row/column switching signals (R/C) are applied to the multiplexer 3. Thus, the first CPU 1 and the second CPU 2 access the dynamic memory 4 in a time-sharing manner.
configured for access.

Since the address to the dynamic memory 4 is latched at the falling edge of the address strobe signal (RAC, CAS), no address is required at the end of the memory cycle. The address switching signal (C/D) is the first C/D.
The address signals output by the PUI and the second CPU 2 are switched.

The shared memory control device 5 has a first CPUI and a second CPU
Upon receiving the status signal output from U2, it mediates the requests of the same party, generates a timing signal for memory access, and also generates the address switching signal (C/D).

The operating clock (CLK) of the shared memory control device 5 is
1st. It is synchronized with the clock of the second CPUI, 2,
The shared memory control device 5 includes each CPUI.

The status signal output from 2 is connected to the operating clock (
Sample on the rising edge of CLK).

In the embodiment shown in FIG. 2, the status signal (CADS) output from the first CPU 1 is sampled at time 21, and the address switching signal (C/D) is 0'. Multiplexer 3 is suitable. Generally, the CPU outputs the address signal almost simultaneously with the output of the status signal (CADS), so the address signal to the dynamic memory 4 is already stable at time 21.
At the rising edge of the operating clock (CLK) at time 21, the row address strobe signal (RAS) can be activated immediately to enter the memory operating state. Since this address only needs to be maintained until the fall of the column address strobe signal '(-CAS), there is no problem in changing the address switching signal (C/D) at time 23. Therefore, at time 23, the status signal (DSO/DSI) output from the second (:PU2) is accepted, and the second CPU
The multiplexer 3 may be directed to the 2 side. The rising edge of the next operating clock (CLK) at the switched time 23 (
Since the memory operation state is entered at time 24), precharge time is secured. - degree, second C
The address switching signal (/D) directed toward the PU2 side can be returned to its original state when exiting the memory operating state (time 26).

On the other hand, in the conventional example shown in FIG.
), the address switching signal (if:/D) is determined, so wait until the address switching signal (C/D) becomes stable and then the address signal output from multiplexer 3 becomes stable before entering the memory operating state. I have to, and that's it.
Memory cycle time needs to be increased. This problem can be alleviated by using a dynamic memory 4 with a short access time, but this may lead to an increase in cost. Furthermore, although it can be said that it is advantageous that the first CPU 2 and the second CPU 2 are on the same level, the time from when the CPU outputs the status signal to when the memory operation state ends (
Since the memory access time (memory access time) is longer than that of the embodiment shown in FIG. 2, it is rather , it is advantageous to shorten the memory access time of the first CPUI. Furthermore, in this case, it is possible to use a second CPU 2 whose speed is slower than that of the first CPU, and in this case, the speed of the second CPU 2 may be lower than that of the first CPU.
The memory access time on the U2 side is substantially the same as that of the first CP.
The fact that it is one clock longer than the UI becomes irrelevant.

In the embodiment shown in FIG. 2, there are two CPUs, but the second
DMA (Direct Memory Ac)
cess) controller.

[Effects of the Invention] As explained above, according to the present invention, the address switching time overlaps with the precharging time of the dynamic memory, so there is no need to extend the memory cycle for this purpose, and the timing of the address given to the dynamic memory can be adjusted. It is possible to reduce the memory cycle time while ensuring a margin. In particular, when the instruction execution cycle time of the second CPU is greater than or equal to the minimum cycle time of this memory device, the address switching time is
the first CPU without affecting the access time of that CPU.
When there is a conflict with the first CPU, the switching time overlaps with the precharge time, so the first CPU
Waiting on the U side can be minimized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram relating to an example of sequence control in FIG. 1, and FIG. 3 is a timing diagram relating to sequence control of a conventional shared memory control device. be. 1...First CPU, 2...Second CPU, 3...
・Multiplexer, 4... Dynamic memory, 5.
...Shared memory control device.

Claims (1)

[Claims] In a shared memory control device that allows multiple CPUs to access the same dynamic memory in a time-sharing manner,
A shared memory control device characterized in that it accepts a memory access request from a selected CPU at the clock edge at which a memory cycle ends, switches an address switching signal, and starts the memory cycle at the next clock edge.