JPH03291935A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03291935A
JPH03291935A JP9353690A JP9353690A JPH03291935A JP H03291935 A JPH03291935 A JP H03291935A JP 9353690 A JP9353690 A JP 9353690A JP 9353690 A JP9353690 A JP 9353690A JP H03291935 A JPH03291935 A JP H03291935A
Authority
JP
Japan
Prior art keywords
power supply
film
supply wiring
interlayer insulating
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9353690A
Other languages
Japanese (ja)
Inventor
Hiroshi Tsuchiya
浩 土屋
Koji Tanaka
幸次 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP9353690A priority Critical patent/JPH03291935A/en
Publication of JPH03291935A publication Critical patent/JPH03291935A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the generation of cracks in a PSG protecting film by forming unevenness on the surface of an interlayer insulating film turning to a substratum of an Al power supply wiring. CONSTITUTION:A field oxide film 200 is formed on a first conductivity type semiconductor substrate 100; an interlayer insulating film 300 of a poly Si-Al wiring is formed on the film 200; an Al power supply wiring 400 is formed by using the the film 300 as a substratum. In this semiconductor device, unevenness is formed on the surface of the interlayer insulating film 300. For example, the field oxide film 200 is formed on a first conductivity type semiconductor substrate 100 for an IC; a diffusion region 601 is finely formed; thereon the interlayer insulating film 300 for the poly Si-Al wiring is formed; the unevenness is formed on the film 300 surface. The wide Al power supply wiring 400 is arranged on the unevenness, and coated with a PSG protecting film 500 for preventing the damage of IC and protecting the IC from contamination caused by Na ions and the like.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、IC用半導体基板上に層間絶縁膜を形成し
、これを下地としてへ!電源を配設するようにした半導
体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) This invention involves forming an interlayer insulating film on a semiconductor substrate for IC, and using this as a base! The present invention relates to a semiconductor device equipped with a power source.

(従来の技術) 従来のAl電源を配線した半導体装置としては、例えば
第5図に示すようなものがある。この図において、10
0はIC用の第1導電型半導体基板、200はこの半導
体基板100上に形成したフィールド酸化膜(LOGO
8)であって、この酸化膜200の上には、ポリS i
 −A、g配線の層間絶縁膜300が平坦に形成されて
いる。この平坦な層間絶縁膜300の上には、幅の広い
Al電源配線400が配設されている。さらに、このA
l電源配線400の上には、ICの損傷を防止するとと
もにNaイオンなどによってICが汚染されるのを保護
するためにPSG保護膜500が形成されている。
(Prior Art) An example of a semiconductor device in which a conventional Al power source is wired is as shown in FIG. In this figure, 10
0 is a first conductivity type semiconductor substrate for IC, 200 is a field oxide film (LOGO) formed on this semiconductor substrate 100.
8), on this oxide film 200, poly Si
The interlayer insulating film 300 of the -A and g wirings is formed flat. On this flat interlayer insulating film 300, a wide Al power supply wiring 400 is provided. Furthermore, this A
A PSG protective film 500 is formed on the power supply wiring 400 to prevent damage to the IC and to protect the IC from being contaminated by Na ions or the like.

(発明が解決しようとする課題) しかしながら、従来の半導体装置にあっては、平坦な層
間絶縁膜300を下地面として幅の広いAl電源配線4
00を敷設し、その上にPSG保護膜500を被着して
モールドする構造となっている。このため、第6図に示
すように、Al電源配線400にモールドによる応力が
加わり、これによりへ!電源配線400がたわんでしま
う。その結果、A、e電源配線400端部のたわみ変形
によってPSG保護膜500にクラックが生じて信頼性
を低下させるという問題点があった。
(Problem to be Solved by the Invention) However, in a conventional semiconductor device, a wide Al power supply wiring 4 is formed using a flat interlayer insulating film 300 as a base surface.
00 is laid down, a PSG protective film 500 is deposited thereon, and then molded. For this reason, as shown in FIG. 6, stress is applied to the Al power supply wiring 400 due to the molding, and this leads to! The power supply wiring 400 is bent. As a result, there was a problem in that cracks were generated in the PSG protective film 500 due to the bending deformation of the ends of the A and e power supply wirings 400, reducing reliability.

この発明は、上記の問題点に着目してなされたもので、
その目的は、PSG保護膜にクラックが発生するのを防
止できる半導体装置を提供することにある。
This invention was made by focusing on the above-mentioned problems.
The purpose is to provide a semiconductor device that can prevent cracks from occurring in the PSG protective film.

(課題を解決するための手段) この発明は、上記のような目的を達成するため、第1導
電型半導体基板上にフィールド酸化膜を形成するととも
に、その上にポリS t −A、g配線の層間絶縁膜を
形成し、この層間絶縁膜を下地としてAl電源配線を設
けた半導体装置において、上記層間絶縁膜の表面に凹凸
を形成したことを特徴とする。
(Means for Solving the Problems) In order to achieve the above objects, the present invention forms a field oxide film on a first conductivity type semiconductor substrate, and forms a poly S t -A,g wiring thereon. A semiconductor device in which an interlayer insulating film is formed, and an Al power supply wiring is provided using this interlayer insulating film as a base, is characterized in that irregularities are formed on the surface of the interlayer insulating film.

(作用) この発明では、Al!、電源配線の下地となる層間絶縁
膜の表面に凹凸を形成している。このため、モールド時
にAl電源配線に応力が加わっても、この応力は層間絶
縁膜の凹凸箇所において多方向に向かって速やかに分散
され、Al!、電源配線の端部に応力が集中することが
ない。したがって、Al電源配線の端部に応力によるた
わみ変形が生じないので、Ai!、電源配線の端部から
PSG保護膜にクラックが発生するのを防止できる。
(Function) In this invention, Al! , irregularities are formed on the surface of the interlayer insulating film that serves as the base for the power supply wiring. Therefore, even if stress is applied to the Al power supply wiring during molding, this stress is quickly dispersed in multiple directions at the uneven portions of the interlayer insulating film, and the Al! , stress will not be concentrated at the end of the power supply wiring. Therefore, since no bending deformation due to stress occurs at the end of the Al power supply wiring, Ai! , it is possible to prevent cracks from occurring in the PSG protective film from the ends of the power supply wiring.

(実施例) 以下、この発明を図面に基づいて説明する。(Example) The present invention will be explained below based on the drawings.

第1図は、この発明の一実施例を示す半導体装置の断面
図である。
FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention.

まず構成を説明すると、IC用第1導電型半導体基板1
00の上にはフィールド酸化膜(LOGO8)200が
形成されているとともに、拡散領域601が微細に形成
されている。そして、この上にはポリS i−A、g配
線の層間絶縁膜300が形成されている。この層間絶縁
膜300はその表面が凹凸状に形成され、これには幅の
広いAl電源配線400が敷設されている。さらに、こ
の上には第2図にも示すように、ICの損傷を防止し、
かつNaイオンなどによる汚染からICを保護するため
PSG保護膜500が被覆されている。
First, to explain the configuration, first conductivity type semiconductor substrate 1 for IC
A field oxide film (LOGO8) 200 is formed on 00, and a diffusion region 601 is formed finely. Then, an interlayer insulating film 300 of poly Si-A and g wiring is formed on this. This interlayer insulating film 300 has an uneven surface, and a wide Al power supply wiring 400 is laid thereon. Furthermore, as shown in Figure 2, there is a function to prevent damage to the IC.
In addition, a PSG protective film 500 is coated to protect the IC from contamination by Na ions and the like.

次に、Al電源配線用下地である層間絶縁膜に凹凸を形
成する際の製造工程例を、第3図(a)〜(e)によっ
て説明する。
Next, an example of a manufacturing process for forming irregularities in an interlayer insulating film, which is a base for Al power supply wiring, will be described with reference to FIGS. 3(a) to 3(e).

(a)  まず、素子間を絶縁分離するためのフィール
ド領域形成用ナイトライド膜(S i 3 N4膜)1
000を半導体基板100の上に形成する(同図(a)
)。
(a) First, a nitride film (S i 3 N 4 film) 1 for forming a field region for insulating isolation between elements.
000 is formed on the semiconductor substrate 100 (FIG. 1(a)).
).

(b)  次に、このナイトライド膜1000を保護膜
として素子領域の酸化を防ぎながら、半導体基板100
のフィールド領域に反転防止層221(p+フィールド
、n+フィールド)を被着してフィールド酸化膜200
を形成する(同図(b))(C)  そして、半導体基
板100のポリSi配線とAl2電源配線400とを区
分できるよう、フィールド酸化膜200の上に所要厚の
層間絶縁膜(PSG膜)300を常圧CVD装置により
堆積する(同図(C))。
(b) Next, while using this nitride film 1000 as a protective film to prevent oxidation of the element region, the semiconductor substrate 100 is
An anti-inversion layer 221 (p+ field, n+ field) is deposited on the field region of the field oxide film 200.
((b)) (C) Then, an interlayer insulating film (PSG film) of a required thickness is formed on the field oxide film 200 so that the poly-Si wiring of the semiconductor substrate 100 and the Al2 power supply wiring 400 can be separated. 300 is deposited using an atmospheric pressure CVD apparatus (FIG. 3(C)).

(d)  さらに、この層間絶縁膜300の上にAlを
蒸着パターニングし広幅のAl電源配線400を形成す
る(同図(d))。
(d) Further, Al is deposited and patterned on this interlayer insulating film 300 to form a wide Al power supply wiring 400 (FIG. 4(d)).

(e)  最後に、Al電源配線400の損傷を防止す
るとともに、Naイオンなどによる汚染からICを保護
するため、Al電源配線400の上にPSG保護膜50
0を形成する(同図(e))。
(e) Finally, in order to prevent damage to the Al power supply wiring 400 and to protect the IC from contamination by Na ions, etc., a PSG protective film 50 is placed on the Al power supply wiring 400.
0 is formed ((e) in the same figure).

次に、上記Ai!、電源配線用下地に凹凸を形成する際
の他の製造工程例を、第4図(a)〜(e)によって説
明する。
Next, the above Ai! Another example of the manufacturing process for forming irregularities on the base for power supply wiring will be explained with reference to FIGS. 4(a) to 4(e).

(a)  まず、半導体基板100のフィールド領域に
反転防止層(p+フィールド、n+フィールド)を被着
してフィールド酸化膜(LOCO8)200を形成する
(同図(a))。
(a) First, a field oxide film (LOCO8) 200 is formed by depositing an anti-inversion layer (p+ field, n+ field) on the field region of the semiconductor substrate 100 (FIG. 2(a)).

(b)  次いで、この上にn+の多結晶シリコンをパ
ターニングしてポリSi配線600を形成する(同図(
b))。
(b) Next, n+ polycrystalline silicon is patterned on this to form a poly-Si wiring 600 (see FIG.
b)).

(c)  この後、ポリSi配線600とAl電源配線
400とを区分できるよう、所定厚の層間絶縁膜(PS
G膜)300を常圧CVD装置により堆積する(同図(
C))。
(c) After this, in order to separate the poly-Si wiring 600 and the Al power supply wiring 400, an interlayer insulating film (PS
G film) 300 is deposited using an atmospheric pressure CVD apparatus (see figure (
C)).

(d)  さらに、この層間絶縁膜300の上にAlを
蒸着パターニングして広幅のAl電源配線400を形成
する(同図(d))。
(d) Further, Al is deposited and patterned on this interlayer insulating film 300 to form a wide Al power supply wiring 400 (FIG. 4(d)).

(e)  最後に、Al電源配線400の損傷を防止す
るとともに、Naイオンなどによる汚染からICを保護
するため、A乏電源配線400の上にPSG保護膜50
0を形成する(同図(e))。
(e) Finally, in order to prevent damage to the Al power supply wiring 400 and protect the IC from contamination by Na ions, etc., a PSG protective film 50 is placed on the A poor power supply wiring 400.
0 is formed ((e) in the same figure).

次に、この実施例の作用を説明すると、PSG保護膜5
00をモールドする際には、Al電源配線400に応力
が作用する。しかし、本例ではAl電源配線400の下
地、すなわち層間絶縁膜300の表面に凹凸模様を形成
しているため、Al電源配線400に対する縦方向の応
力が多方向に分散される。つまり、第2図に示すように
、モールドの力FによりAl電源配線400の中間部分
は若干たわむが、この場合、下地の凹凸部分において力
の分散が速やかに図られるため、Al電源配線400の
端部に局部的な応力集中が生じない。
Next, to explain the operation of this embodiment, the PSG protective film 5
When molding 00, stress acts on the Al power supply wiring 400. However, in this example, since the uneven pattern is formed on the base of the Al power supply wiring 400, that is, on the surface of the interlayer insulating film 300, the vertical stress on the Al power supply wiring 400 is dispersed in multiple directions. That is, as shown in FIG. 2, the middle portion of the Al power supply wiring 400 is slightly bent due to the force F of the mold, but in this case, the force is quickly dispersed in the uneven portion of the base, so that the Al power supply wiring 400 is bent slightly. No local stress concentration occurs at the ends.

したがって、PSG保護膜500に過度なツノが集中的
に加わらなくなるので、クラックの発生が良好に防止さ
れる。
Therefore, excessive horns are not intensively added to the PSG protective film 500, and cracks are effectively prevented from occurring.

(発明の効果) 以上説明してきたように、この発明によれば、広幅のA
、g電源配線が被着される下地面に凹凸を形成したため
、モールドによってへ!電源配線に応力が加わっても、
この応力はAl電源配線の端部に集中することな(、下
地の凹凸部分において多方向に分散され、これによりA
i!、電源配線の端部からPSG保護膜に向かってクラ
ックが生じるのを確実に防止できるという効果が得られ
る。
(Effect of the invention) As explained above, according to this invention, a wide A
, g Due to the unevenness formed on the base surface to which the power supply wiring is attached, it is damaged by the mold! Even if stress is applied to the power supply wiring,
This stress is not concentrated at the end of the Al power supply wiring (but is dispersed in many directions in the uneven portion of the base, and as a result,
i! , it is possible to reliably prevent cracks from occurring from the ends of the power supply wiring toward the PSG protective film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す半導体装置の断面図
、第2図は応力分布状態を示すA、C電源配線部分の詳
細図、第3図(a)〜(e)はこの発明の製造例を順次
示す工程図、第4図(a)〜(e)はこの発明の他の製
造例を順次示す工程図、第5図は従来例を示す半導体装
置の断面図、第6図はクラック発生箇所を説明する従来
装置の断面図である。 100・・・半導体基板 200・・・フィールド酸化膜 300・・・層間絶縁膜 400・・・Al!、電源配線 500・・・PSG保護膜 600・・・ポリSi配線 1000・・・ナイトライド膜
FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a detailed view of A and C power supply wiring portions showing stress distribution, and FIGS. 3(a) to (e) are views of the present invention. 4(a) to 4(e) are process diagrams sequentially showing other manufacturing examples of the present invention, FIG. 5 is a sectional view of a semiconductor device showing a conventional example, and FIG. FIG. 2 is a cross-sectional view of a conventional device illustrating locations where cracks occur. 100...Semiconductor substrate 200...Field oxide film 300...Interlayer insulating film 400...Al! , power supply wiring 500...PSG protective film 600...poly-Si wiring 1000...nitride film

Claims (1)

【特許請求の範囲】 1、第1導電型半導体基板上にフィールド酸化膜を形成
するとともに、その上にポリSi−Al配線の層間絶縁
膜を形成し、この層間絶縁膜を下地としてAl電源配線
を設けた半導体装置において、 上記層間絶縁膜の表面に凹凸を形成したことを特徴とす
る半導体装置。
[Claims] 1. A field oxide film is formed on a first conductivity type semiconductor substrate, and an interlayer insulating film of poly-Si-Al wiring is formed thereon, and an Al power supply wiring is formed using this interlayer insulating film as a base. What is claimed is: 1. A semiconductor device comprising: a semiconductor device comprising: a surface of the interlayer insulating film having irregularities formed therein;
JP9353690A 1990-04-09 1990-04-09 Semiconductor device Pending JPH03291935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9353690A JPH03291935A (en) 1990-04-09 1990-04-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9353690A JPH03291935A (en) 1990-04-09 1990-04-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03291935A true JPH03291935A (en) 1991-12-24

Family

ID=14085004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9353690A Pending JPH03291935A (en) 1990-04-09 1990-04-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03291935A (en)

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