KR0178997B1 - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor device Download PDFInfo
- Publication number
- KR0178997B1 KR0178997B1 KR1019910005660A KR910005660A KR0178997B1 KR 0178997 B1 KR0178997 B1 KR 0178997B1 KR 1019910005660 A KR1019910005660 A KR 1019910005660A KR 910005660 A KR910005660 A KR 910005660A KR 0178997 B1 KR0178997 B1 KR 0178997B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- insulator
- deposited
- via hole
- wiring
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract 2
- 230000008021 deposition Effects 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 238000000059 patterning Methods 0.000 abstract 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 텅스텐을 사용하지 않아 공정의 단순화와 원가의 절감을 얻을 수 있는 반도체 장치의 배선간 연결방법에 관한 것으로 기판(1)위에 증착되는 제1메탈(3), 제2메탈(6)을 배선하는 방법에 있어서, 상기 제1메탈(3)위에 제2절연체(4)를 형성하고 패터닝하여 비어 홀을 형성한 후 상기 비어 홀에 베리어 메탈(5)을 2000Å이하로 증착하고 상기 베리어 메탈(5)위에 제2절연체(4)을 150℃ 이하의 저온에서 1㎛이하로 증착한 상태에서 대기중에 노출하지 않고 연속으로 500~600℃에서 가열하여서 이루어지는 방법이다.The present invention relates to a wiring-to-wire connection method of a semiconductor device that can simplify the process and reduce the cost by not using tungsten. The present invention relates to a first metal 3 and a second metal 6 deposited on a substrate 1. In the wiring method, after forming and patterning a second insulator 4 on the first metal 3 to form a via hole, the barrier metal 5 is deposited in the via hole below 2000 mW and the barrier metal ( 5) The second insulator 4 is formed by heating at 500 to 600 ° C. continuously without exposing it to the air in a state in which the second insulator 4 is deposited at 1 ° C. or less at a low temperature of 150 ° C. or lower.
Description
제1도는 종래의 배선상태를 나타낸 반도체 장치의 단면도.1 is a cross-sectional view of a semiconductor device showing a conventional wiring state.
제2도는 본 발명에 배선 공정을 나타낸 단면도.2 is a cross-sectional view showing a wiring process in the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 제1절연체1 substrate 2 first insulator
3 : 제1메탈 4 : 제2절연체3: first metal 4: second insulator
5 : 베리어 메탈 6 : 제2메탈5: Barrier Metal 6: Second Metal
본 발명은 ULSI 소자에 적당하도록 한 반도체 장치의 배선가 연결방법에 관한 것이다.The present invention relates to a method of connecting a wiring of a semiconductor device suitable for a ULSI element.
종래 반도체 장치의 배선연결방법은 제1도에 도시된 바와 같이 기판(1)위에 제1절연체(2)를 패터닝한 후 제1메탈(3)을 형성하고 다시 제1메탈(3)위에 제2절연체(4)를 형성하여 패터닝한 후 비어 홀(Via Hole)에 텅스텐(7)을 채운 상태에서 전 표면에 Aℓ합금등의 제2메탈(6)을 형성함으로 제1메탈(3)-텅스텐(7)-제2메탈(6)의 배선간 연결이 이루어 졌다.In the wiring connection method of the conventional semiconductor device, as shown in FIG. 1, the first insulator 2 is patterned on the substrate 1, and then the first metal 3 is formed, and then the second metal is formed on the first metal 3 again. After the insulator 4 is formed and patterned, the first metal 3-tungsten (2) is formed by forming a second metal 6 such as an Al alloy on the entire surface while tungsten 7 is filled in the via hole. 7) -Wiring connection of the second metal 6 was made.
그러나, 이와 같은 종래 배선간 연결방법에 있어서는 텅스텐(7)을 제2절연체(4)의 전면 또는 비어 홀에 부분적으로 증착시키기가 어려움은 물론 고가의 텅스텐(7)을 사용해야 함으로 원가가 상승하게 되는 결점이 있다.However, in the conventional wiring-to-wire connection method, it is difficult to partially deposit the tungsten (7) on the front surface or via hole of the second insulator (4), and the cost increases due to the use of expensive tungsten (7). There is a flaw.
본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로 텅스텐을 사용하지 않고 베리어 메탈을 사용하여 배선간 연결을 할 수 있는 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned shortcomings, and an object thereof is to provide a method for connecting wires using barrier metal without using tungsten.
이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to FIG. 2.
먼저(a)와 같이 기판(1)위에 제1절연체(2)를 형성하여 패터닝한 후 제1메탈(3)을 증착하며 이 제1메탈(3)위에 제2절연체(4)를 형성하여 패터닝함으로 비어 홀을 형성한 후 전체적으로 베리어 메탈(5)(예를 들어 TiW, MOSi2등)을 2000Å 이하로 증착한다.First, as shown in (a), the first insulator 2 is formed and patterned on the substrate 1, and then the first metal 3 is deposited, and the second insulator 4 is formed on the first metal 3 and patterned. As a result, after forming the via hole, the barrier metal 5 (for example, TiW, MOSi 2, etc.) is deposited to 2000 mW or less.
그리고 (b)와 같이 베리어 메탈(5)위에 제2메탈(6)(예를 들어 Aℓ합금)을 150℃이하의 저온에서 1㎛이하로 증착한다.Then, as shown in (b), the second metal 6 (for example, A 1 alloy) is deposited on the barrier metal 5 at a low temperature of 150 ° C. or less at 1 μm or less.
다음에 (c)와 같이 상기 제2메탈(6)을 증착한 상태에서 대기중에 노출하지 않고 연속으로 500~600℃ 사이에서 가열한다.Next, as shown in (c), the second metal 6 is heated continuously between 500 ° C and 600 ° C without being exposed to the atmosphere.
이와 같은 본 발명에 의하면 베리어 메탈(5)을 사용함으로써 제2메탈(6)에 플로잉을 유발할 수 있으며 비어 홀 부위에서 제2메탈(6)이 단선되거나 가열시에 제2메탈(6)이 하층에 제2절연체(4)와 반응하여 산화막이 생성되는 것을 방지할 수 있다.According to the present invention, the use of the barrier metal 5 may cause the second metal 6 to flow, and the second metal 6 is disconnected or heated at the via hole. It is possible to prevent the oxide film from being formed by reacting with the second insulator 4 in the lower layer.
또한, 텅스텐(7)을 사용하지 않음으로 인한 원가의 감소와 공정의 단순화를 이룰 수 있는 특징이 있다.In addition, there is a feature that can reduce the cost and simplify the process by not using tungsten (7).
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910005660A KR0178997B1 (en) | 1991-04-09 | 1991-04-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910005660A KR0178997B1 (en) | 1991-04-09 | 1991-04-09 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920020679A KR920020679A (en) | 1992-11-21 |
| KR0178997B1 true KR0178997B1 (en) | 1999-04-15 |
Family
ID=19313059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910005660A KR0178997B1 (en) | 1991-04-09 | 1991-04-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0178997B1 (en) |
-
1991
- 1991-04-09 KR KR1019910005660A patent/KR0178997B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920020679A (en) | 1992-11-21 |
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