JPH03274763A - Static ram - Google Patents

Abstract

PURPOSE:To enhance integration by forming a gate electrode or one inverter of one layer of a 2-layer polycryetalline silicon film, and forming a gate electrode of the other inverter of the second layer. CONSTITUTION:Active regions 3, 4 are provided in a semiconductor substrate 1, and an active region 5 is also provided in a well 2. A polycrystalline silicon film 6 of a first layer and a polycrystalline silicon film 7 of a second layer are crossed with the regions 3, 4, 5 to form N-channel transistors 8, 9, and 10, 11, and P-channel transistors 12, 13. The transistors 11, 12 of the film 6, and the transistors 8, 9 10 13 of the film 7 are provided. The connection of a gate to a drain and wirings of VDD, VSS are covered with metal 15, and wirings of BL, BL are formed of metal 16 to form a static RAM cell. Thus, since the gate electrodes and wirings of the two inverters can be crossed and narrowed at an interval therebetween, its area can be reduced, and its integration can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a large-capacity, large-integration CMOS static RAM used in electronic equipment, computers, and the like.

[Summary of the Invention] The present invention forms the gate electrode of one impark in the first layer of the two-layer polycrystalline silicon layer, and the gate electrode of the other inverter in the second layer, thereby achieving a small area and a large inverter. An integrated CMOS static RAM is obtained.

[Prior Art] A conventional technology will be explained using FIG. 8. The semiconductor substrate ml is provided with an active transistor t13.4, and N-channel transistors 8.9, 11 are formed via polycrystalline silicon films 6.7, 14. In the well region 2, an active region 5 and a polycrystalline silicon film 6.7 are formed.
P-channel transistors 12.13 are formed. By connecting these with two layers of metal wiring, a static RAM cell is formed.

[Problems to be Solved by the Invention] However, as mentioned above, since the gate electrodes and wiring lines 6, 7, and 14 of the two inverters and word lines are formed of the same layer of polycrystalline silicon film, It is impossible to do so. However, since the three wirings must be completely separated by photolithography and etching, it is necessary to leave a certain distance between them. Therefore, there is a drawback that there is a limit to miniaturization and it is not suitable for small area or large scale integration.

[Means for Solving the Problems 1] In order to solve the above problems, the present invention uses two-layer polycrystalline silicon technology to form the gate electrodes and interconnections of the two inverters with different layers of polycrystalline silicon films. This makes it possible to arrange and route the wires with no gap between them, and also to make them intersect.

[Function] By using the above means, it has become possible to obtain a static RAM with a small area, that is, with high integration.

[Embodiment 1] A first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 1 is a semiconductor substrate, and 2 is a well region. An active region @3.4 is provided within the substrate 1, and an active region 5 is provided within the well 2 as well. These active areas 3.4
．． 5, the first layer polycrystalline silicon film 6 and the second layer polycrystalline silicon film 7 are crossed to form an N-channel transistor 8.9.
and 10.11, P channel transistor 12゜13
form. Transistor made of polycrystalline silicon 6 is 1
1.12, a transistor made of polycrystalline silicon 7 is 8.
It is 9.10.13. As shown in the figure, polycrystalline silicon film 6
．． 7 may be crossed; connect the gate and drain and wire V DD and V ss using metal 15;
By wiring L and BL with metal 17, a static RAM cell is created. Figures 3 to 6 are the first
Figure A-A', B-B', C-C', D-D'E
-E' is a sectional view. The cross section of the transistors 10 and 11 is similar to that shown in FIG. 3B, and the cross section of the connection between the drain of the transistor 10 and the polycrystalline silicon film 6 is similar to that shown in FIG. 4.

FIG. 7 shows a second embodiment. The layout is almost the same as the first embodiment, but since the polycrystalline silicon film and the active region are in direct contact, the area is smaller than that of the first embodiment. A static RAM of 60 μm2 is possible with complete CMOS.

[Effects of the Invention] As described above, the static RAM using the two-layer polycrystalline silicon of the present invention can have a small area and high integration because the gate electrodes and wiring of two inverters can cross each other and the spacing can be narrowed. made possible.

[Brief explanation of drawings]

FIG. 1 shows a static RA of a first embodiment according to the present invention.
The plan view of M, Sections 2 to 6 are A- in Fig. 1, respectively.
A', B-B', C-C', D-D', E-E'
7 is a plan view of a static RAM according to a second embodiment of the present invention, and section 8 is a plan view of a static RAM of the prior art. 1...Substrate region 2...Well region 3.4.5...Active region 6...
.....First layer polycrystalline silicon 7.....Second layer polycrystalline silicon 8.9.10.11...N channel transistor 12.13... ...P-channel transistor 14, . ＜1 state rough 8^M
7. A-A' sectional view 2. FIG. B-B' sectional view FIG. 3 c-c 'Cross-sectional view 84 Figure D-1)'FF 1st view No. 5 Figure E-E' Cross-sectional view Conventional Hachikan Niyoshuti 77th AM half-view No. 8
Ward

Claims (2)

[Claims] (1) A complete CMOS static RAM comprising a first gate electrode thin film, an insulating film on the first gate electrode thin film, and a second gate electrode thin film on the insulating film. (2) The gate electrodes of the first N-channel transistor and the first P-channel transistor of the first inverter are made of the first gate electrode thin film, and the gate electrodes of the first N-channel transistor and the second P-channel transistor of the second inverter are made of the first gate electrode thin film. 2. The static complete CMOS RAM according to claim 1, wherein the gate electrode of the P-channel transistor is made of the second gate electrode thin film.