JPH0411769A - Static ram - Google Patents

Abstract

PURPOSE:To effectively prevent a latchup by applying the source potential of a MOS transistor at each CMOS transistor to each well region, and fixing the potential. CONSTITUTION:n-type well regions 2 and p-type well regions 3 are alternately formed on an n-type silicon substrate 1, and the regions 2, 3 are formed in a stripelike pattern in an X direction as a longitudinal direction. These regions 2, 3 are isolated at l1 in a Y direction, and MOS transistors TrQ1-Q6 of two memory cells are formed in the regions 2, 3. They are divided at the centers of the regions 2, 3, and different conductivity type memory cells are bonded to obtain one memory. The source potential of the MOS transistors formed at each CMOS memory cell is applied to the regions 2, 3. The potential is fixed to effectively prevent a latchup.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a static RAM having completely CMOS type memory cells.

[Summary of the invention]

The present invention prevents latch-up in a static RAM having CMOS type memory cells by applying a source potential of a MOS transistor formed in a well region or a semiconductor substrate to each memory cell.

[Prior art] The circuit of each memory cell is composed of two active load pMO3I circuits.
- CM
An OS type memory cell is obtained. This CMOS type memory cell has advantages such as low current consumption.

By the way, when such a CMOS type memory cell is formed on a semiconductor substrate, wells or substrates of two conductivity types are exposed on the surface of the substrate, and a PMOS transistor and an nMOSMOS transistor are formed thereon. Therefore, for example, when an n-type silicon substrate is used, an n-type well region is formed on the surface of the n-type silicon substrate, and when a double well structure is formed, the n-type well region is also formed on the n-type silicon substrate. formed on top.

(Problems to be Solved by the Invention) Generally, in order to achieve high integration of static RAM, it is necessary to reduce the size of each memory cell.However, it is necessary to reduce the size of the memory cell of a CMOS type memory cell. In such cases, pMOS transistor and n
MOS transistors are placed close to each other, and as a result, latch-up phenomena are more likely to occur.

In order to prevent the Chianob phenomenon, it is necessary to reliably fix the potential of the well region and the substrate. However, in a conventional static RAM having a completely CMOS type memory cell, a contact for fixing the potential is made for each pin of the memory cell, or a contact for fixing the potential is made for each memory cell only on the nMOS transistor side. However, it is not sufficient especially when high integration of memory cells is attempted.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a static RAM that effectively prevents the launch amplifier phenomenon.

[Means to solve the problem]

In order to solve the above-mentioned technical problem, the static RAM of the present invention has a CMOS type memory cell, and a semiconductor substrate has a channel MOS transistor of a second conductivity type in which a MOS transistor of a first conductivity type is formed. A well region and a well region of a first conductivity type in which a MOS transistor of a second conductivity type channel is formed are formed.Here, the channel region of one conductivity type may be a semiconductor substrate. .and,
In the static RAM of the present invention, for each CMOS type memory cell, M
It is characterized in that the source potential of the OS transistor is applied to each well region or semiconductor substrate.

(Function) By supplying the potential of the source side of the MOS transistor formed respectively to the well region and the semiconductor substrate for each memory cell, the potential of the well region and the semiconductor substrate is reliably fixed. This increases the strength against internal latch-up.

:Example: Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of a state RAM having CMOS type memory cells, and each memory cell has a power supply voltage Voo
It has a structure in which a ground voltage Vss is supplied to each region.

First, there are two memory cell circuit structures G, which will be briefly explained with reference to FIG. Static R of this example
The AM memory cell circuit consists of a pair of inverter circuits based on the power supply voltage ■. It has a pMOS MOS transistor nMOS transistor Q and a pMOS MOS transistor nMOS transistor Q2 connected between D and the ground voltage Vss. That is, pMOSMOS
Power supply voltage VDD is applied to transistor Q3Q-S,
Ground voltage V is applied to the sources of nMOS transistors Q, , Q,
ss is given. pMOsMoS transistor QMO
The train of the SMOS transistor Q is commonly connected to one of the source and drain of the nMO5 transistor Q5 for access, and the pMO3 transistor Q4 and the 0M
Connected to the gate of O3 transistor Q2. Also, p
The drains of the MO3 transistor Q4 and the nMOSMoS transistor Qz are commonly connected to one of the access nMOSMOS transistor Q-strains, and the pMosMoS transistor QMO3 transistor Q,
connected to the gate. And nMO for access,
The other source and drain of the s transistors Q, ,Q, are connected to the paired pinto lines BLI, BL2, and each nM
OsMoS transistor Q.

The gate of is connected to the same word line WL.

Next, a specific layout of a memory cell having such a Mo3 transistor will be described with reference to FIGS. 1 and 2.

In the static RAM of this embodiment, an n-type silicon substrate 1 is used, and an n-type well region 2 and a p-type well region 3 are formed on the n-type silicon substrate 1. The shape of these well regions 2.3 is a strip pattern with the longitudinal direction in the X direction in the figure, and n-type well regions 2 and p-type well regions 3 are alternately formed on the silicon substrate l in the Y direction. be done.

These n-type well region 2 and p-type well region 3 are
They are spaced apart by 2+ in the direction. Also, if we pay attention to the Y direction, MoS transistors for two memory cells are formed in each well region 2.3.
The circuit arrangement is such that one memory cell is obtained by dividing each well region at the center and combining them with memory cell elements of different conductivity types.

On the main surface of the substrate of the static RAM of this embodiment having such a double well structure, a field oxide film IO is formed in a desired pattern by selective oxidation. The region where the field oxide film IO is not formed is defined as an element formation region, and each Mo
S transistor or NB': L voltage V l111. In particular, in the static RAM of this embodiment, a well region 2 is formed for each memory cell.
．． Contact has been made to 3.

First, regarding the size of each memory cell, see YNXX in the figure.
The area indicated by M indicates the area occupied by one CMOS memory cell, and the shape of one CMOS memory cell is approximately rectangular. Furthermore, continuity between a memory cell and an adjacent memory cell is such that the structure is folded back at the boundary line of the memory cell.

Next, to explain the structural numbers of three examples of p-type well regions, in this p-type well region 3, there are two driving n-type well regions.
A MO5lMoS transistor Q is formed, and an accessing 0MO3 transistor Qs, Q= is also formed. The nMOS transistors Q, ,Q, for access are
A pin contact hole 11.12 is formed in one of the source/drain regions. Through these contact holes 11 and 12, each nMOSMoS transistor Q- is connected to a pinto line (not shown). Note that the longitudinal direction of the bit line is the Y direction in the figure.
3 transistor Q5. The gate electrode of Q is the word line WL. The word line WL extends in the X direction without being offset in the Y direction between the nMOSMoS transistors Qs. This word vAWL consists of a first wiring layer, and this first wiring layer is, for example, a polysilicon layer or a polycide structure wiring layer.

The other source and drain of the nMOS transistor Q are connected to the first common gate electrode layer 21 via the contact region 13. This contact region 13 is provided with a substantially rectangular connection layer with one corner cut out for connection between the source train and the first common gate electrode layer 21 . In the vicinity of the contact region 13 on the Y direction side, a channel of the 0MO3 transistor Q2 is formed under the first common gate electrode layer 21. Its channel direction is the X direction. A ground line 23 is connected to the source 31 of the nMOS transistor Q2 through a contact hole 15.
A ground voltage Vss is given from.

This ground line 23 is a wide band-shaped voltage line whose longitudinal direction is along the X direction in the figure, and has a polycide structure. and,
A contact hole 5 for connecting between the p-type well region 3 and the ground line 23 is provided so as to line up with this contact hole 15 .

A p-type impurity diffusion region 33 for connection to the p-type well region 3 is formed below the contact hole 5. In this way, in the p-type well region 3, the ground voltage Vss is supplied from the contact hole 5 portion for one memory cell.

Therefore, the potential of the p-type well region 3 is reliably fixed.

The other source/drain of the nMO5I-transistor Q has a continuous diffusion layer and serves as the drain 32 of the nMOS transistor Q2. In the contact region 14, the diffusion layer and the second common gate electrode layer 22 are connected. This contact region 14 is also provided with a substantially rectangular connection layer for connecting the second common gate electrode layer 22, and the drain 32 of the nMOS transistor Q2 and the second common gate electrode layer 22 are connected via this connection layer. Connected. On the Y-direction side of this contact region 14, an nM film is formed using the second common gate electrode layer 22 as a gate electrode.

An S transistor Q is provided. Its channel direction is the X direction. Source 34 of nMOS transistor Q
is connected to the ground line 23 via the contact hole 16. The train 35 of the nMOS transistor Q1 is
It is connected to the first common gate electrode N21 via the contact region 17.

A substantially rectangular connection layer for connection is also formed in this contact region 17 .

The first common gate electrode layer 21 and the second common gate electrode layer 22 are formed of the same first wiring layer as the word 11WL. In FIG. 1, these first wiring layers are indicated by dashed lines. These first common gates are connected to the pole layer 2.
The first and second common gate electrode layers 22 extend substantially parallel to each other with the Y direction in the figure as the longitudinal direction, and function as a wiring layer from the p-type well region 3 to the n-type well region 2. .

Next, on the n-type well region 2 side, two active load pMO54 transistors Q3. Q is formed. pMO
The 3l-transistor Q4 is formed using the first common gate electrode layer 21 as a gate electrode, and its channel direction is in the X direction. The source 36 of the pMOS transistor Q4
A power line 24 for supplying the voltage tA is connected to the contact hole 18 through the contact hole 18. This electric fifi
The line 24 is formed of the same layer as the ground line 23, and has a wide band-like pattern whose longitudinal direction is the X direction. Further, this power supply line 24 is shared by two memory cells adjacent in the Y direction. Drain 37 of PMO5 transistor Q4
is connected to the second common gate electrode layer 22 via the contact region 19. A substantially rectangular connection layer is formed in this contact region 19 similarly to other collect holes. The pMO3 transistor Q3 has a contact region 19
The second common gate electrode layer 22 serves as the gate electrode. The chamfer direction is the X direction. The source 38 of the pMO3 transistor Q3 is connected to the 'r4. It is connected to the source line 24. Train 39 of pMO3 transistor Q3 is
The contact region 20 is connected to the first common gate electrode 121 . A substantially rectangular connection layer is also formed in this contact region 20, and conduction is established through the connection layer.

In the n-type well region 2 in which such ρMOS transistors Q, , Q, are formed, an r-contact hole 4 is formed to fix the potential of the n-type well region 2, and an n-type contact hole 4 is formed below the collector hole 4. Impurity diffusion region 40 and power supply line 24 are connected via contact hole 4 . Therefore, p
MO3 transistor Q3. The potential i of the n-type well region 2 in which Q is formed, and the voltage a; voltage van is supplied through the contact hole 4 provided for each memory cell, and as a result, the potential of the well becomes Fixed, increasing the strength of the latch-up resistance.

FIG. 2 is a diagram showing the layout of a mask for ion implantation for forming source/drain regions. Ion implantation for forming sources and drains is performed on the field oxide film 10. Word *WL, first common gate electrode layer 21. This is performed using the second common gate electrode N22 and the resist layer as a mask. Therefore, the field oxide film 10. Word line W
L, first common gate electrode layer 21. Impurities are introduced into the second common gate electrode layer 22 through a self-alignment line.

In FIG. 2, the shaded regions are regions into which n-type impurities are introduced, and the other regions are regions into which p-type impurities are introduced. On the n-type well region 2 side, n-type impurities are introduced only around the contact hole 4, and p-type impurities are introduced elsewhere. Therefore, the power supply voltage V0 of each memory cell is
In addition to supplying pMO3 transistors Q,...
Q.

is formed by the gate and self-line. Furthermore, on the p-type well g region 3 side, p-type impurities are introduced only around the contact hole 5, and n-type impurities are introduced elsewhere. Therefore, the ground voltage ■ss is supplied to each memory cell through the contact hole 5, and n
MOS transistors Q, ,Q, ,Q5. Q is formed by a gate and a self-line.

FIG. 3 is a sectional view taken along the line ■--■ in FIG. 1. As shown in FIG. 3, an n-type well region 2 and a p-type well region 3 are formed on an n-type silicon substrate 1 with a distance of 1+. A p-type impurity diffusion region that becomes the source 36 of the pMO5 transistor Q4 is formed on the surface of the n-type well region 2, and this source 36 is connected to the power supply line through the contact hole 18 formed in the interlayer insulating film 41. Connect to 24.

This power supply line 24 has a polycide structure. An n-type impurity diffusion region 40 is formed in close contact with the source 36 for applying a potential to the n-type well region 2 for each memory cell. A contact hole 4 is formed on the n-type impurity diffusion region 40 by opening the glabella insulating film 41, and the TA line type 4 is connected through the contact hole 4.

Next, on the surface of the p-type well region 3, an nMOSMOS
An n-type impurity diffusion region serving as the transistor Q2 source 31 is formed, and this source 31 is connected to the ground line 23 through a contact hole 15 formed in the glabella insulating film 41. This ground line 23 has the same polycide structure as the electric fA line 24, and is formed by patterning at the same time. A p-type impurity diffusion region 33 is formed adjacent to the source 31 for applying a potential to the p-type well region 3 for each memory cell. This p-type impurity diffusion region 3
A contact hole 5 is formed on the contact hole 3 through the glabellar insulating film 41, and the t cross wire 23 is connected through the contact hole 5.

In addition, the grounding wire 23. Both power supply lines 24 are covered with an insulating film 42.

In the static RAM of this embodiment, the source potential of the MOS transistor formed in the well region of each memory cell is applied via the contact hole 4.5. As a result, the potential of each well region 2.3 is reliably fixed, so that the strength against launch-up can be sufficiently increased.

Although the static RAM of this embodiment has a double well structure, the n-type well region may be an n-type semiconductor substrate. In addition, contact holes 11.1 with the hit lines of nMOS transistors Q, Q6 for access are provided.
2 is provided with a connection layer similar to the other contact areas,
It is also possible to have a structure that is resistant to mask displacement and the like.

[Effects of the Invention] In the state RAM having CMO3 type memory cells of the present invention, a predetermined voltage is supplied to the well region and the semiconductor substrate for each memory cell, so that the potential of the well region and the semiconductor substrate is By fixing it, you can increase the strength of the base.

[Brief explanation of the drawing]

FIG. 1 is a plan view of essential parts of an example of a static RAM of the present invention, FIG. 2 is a plan view showing a mask pattern for ion implantation of the example, FIG. The figure is a circuit diagram of a CMO3 type memory cell in a static RAM. l...Silicon substrate 2...N type well region 3...P type well region 4.5...Contact hole 23...Ground line 24...Power line Q+, Qz, Qs, Q6-nMO3tra7dis9Q,,
Q4: PMOS transistor patent applicant Akira Kobe (and 2 other people), patent attorney representing Sony Corporation

Claims (2)

[Claims] (1) Static RA with CMOS type memory cells
M includes, on the semiconductor substrate, a second conductivity type well region in which a first conductivity type channel MOS transistor is formed, and a first conductivity type well region in which a second conductivity type channel MOS transistor is formed.
A static RAM characterized in that a well region of a conductivity type is formed, and a source potential of a MOS transistor formed in each of the well regions is applied to each well region for each of the CMOS type memory cells. (2) Static RA with CMOS type memory cells
In M, a well region of a second conductivity type in which a MOS transistor of a first conductivity type channel is formed is formed in a semiconductor substrate of a first conductivity type in which a MOS transistor of a second conductivity type channel is formed; A static RAM characterized in that source potentials of MOS transistors formed in the semiconductor substrate and the well region are respectively applied to the semiconductor substrate and the well region for each memory cell.