KR100557930B1 - Contact structure of semiconductor device and method for forming the same - Google Patents

Abstract

The present invention discloses a contact structure of a semiconductor device and a method of forming the same. According to an aspect of the present invention, there is provided a method of forming a contact structure of a semiconductor device, the method including: providing a semiconductor substrate in which an active region and a contact predetermined region are defined; Forming a gate oxide film and a conductive layer for a gate electrode on the semiconductor substrate; Patterning the gate electrode conductive layer and the gate oxide film in a predetermined form to form a plurality of gate electrodes; Depositing an insulating film for a spacer on the semiconductor substrate resultant; And anisotropically etching the spacer insulating film to expose the surface of the gate electrode, thereby forming a spacer, wherein the gate electrode in the contact region is formed to be spaced at least twice the line width of the spacer, and The gate electrode, which is not a predetermined region, is formed to be spaced apart by a distance less than twice the line width of the spacer.

Description

Contact structure of semiconductor device and method for forming the same

1 is a circuit diagram schematically showing a typical SRAM device.

2 is a plan view of a conventional SRAM device.

3 is a cross-sectional view taken along the line III-III ′ of FIG. 2.

4A and 4B are cross-sectional views of respective processes for explaining a method for forming a contact of a semiconductor device according to an embodiment of the present invention.

5 is a plan view of an SRAM device according to Embodiment 2 of the present invention;

6A to 6E are cross-sectional views of FIG. 5 taken along line VI-VI ′ to illustrate a method for forming a contact of an SRAM device according to Embodiment 2 of the present invention.

(Explanation of symbols for the main parts of the drawing)

20,31- Semiconductor Substrate 21,32-Gate Oxide

22a, 22b, 22c, 34a, 34b, 34c, 34d-gate electrode

23,36-Insulation layer for spacer 24,37-Spacer

35a, 35b-low concentration impurity regions 38a, 38b-high concentration impurity regions

40a-common node line 40b-bit line

S, D-source, drain region H, H1, H2-contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure of a semiconductor device and a method of forming the same, and more particularly, to a contact structure of a semiconductor device and a method of forming the same, which can reduce an active area area.

In general, unlike the DRAM device, the SRAM device does not need to recharge periodically stored information, it is easy to design, and there is an advantage that less potential problems occur. In addition, these SRAM devices are very popular memory devices because they can be driven at high speed, low power consumption and simple operation.

As shown in FIG. 1, the SRAM has a structure in which an inverter composed of load transistors Q1 and Q2 and pull down transistors Q3 and Q4 is cross-coupled, and a pull-down transistor. Pass-through transistors Q5 and Q6 are respectively connected between Q3 and Q4, the bit line BL, and the bit line bar BL ⁻¹ , respectively. Here, the gates of the pass transistors Q5 and Q6 are connected to the word line WL. In this case, the load transistors Q1 and Q2 use a high resistance P-type MOS transistor or a thin film transistor and a high resistor to minimize the leakage current of the drain charges of the pull-down transistor and the pass-through transistor.

FIG. 2 is a plan view in which an SRAM device having such a configuration is disposed on a semiconductor substrate. In this figure, pull-down transistors Q3 and Q4 and pass-through transistors Q5 and Q6 are shown in a unit SRAM.

With reference to the drawings, a predetermined portion of the semiconductor substrate (not shown) is field oxidized to define the device isolation region 2 and the first and second active regions A1 and A2. Here, the first active region A1 is a region where the first pull-down transistor Q3 and the first pass-through transistor Q5 are formed, and the second active region A2 is the second pull-down transistor Q4 and the second pass-through. This is the region where the transistor Q6 is formed.

The first word line WL1 is disposed to pass through a portion of the first active region A1, and the second word line WL2 is disposed to pass through a portion of the second active region A2. Here, the first and second word lines WL1 and WL2 become gate electrodes of the first and second pass-through transistors Q5 and Q6, respectively.

Meanwhile, the first and second gate electrodes 4a and 4b are formed to pass through the remaining portions of the first and second active regions A1 and A2. The first gate electrode 4a extends so as to overlap the predetermined portion of the second active region A2 while passing through the predetermined portion of the first active region A1, and the second gate electrode 4b extends the second active region ( It extends so as to overlap the predetermined portion of the first active region A1 while passing through the predetermined portion of A2).

Here, each of the gaps between the first and second word lines WL1 and WL2 and the first and second gate electrodes 4a and 4b may be set in consideration of spacers and contact areas to be formed on the respective sidewalls. .

The first and second pools are formed by ion implanting impurities into each of the word lines WL1 and WL2 and the active regions A1 and A2 on both sides of the gate electrodes 4a and 4b to form source and drain regions S and D. Down transistors Q3 and Q4 and first and second pass transistors Q5 and Q6 are completed. In this case, the gate electrode 4a of the first pull-down transistor Q3 is in contact with the common drain region of the second pull-down transistor Q4 and the second pass-through transistor Q6. In addition, the gate electrode 4b of the second pull-down transistor Q4 is in contact with the common drain region of the first pull-down transistor Q3 and the first pass-through transistor Q5. The bit line contact CA and the common node contact CB are selectively formed in the source and drain regions of each transistor.

3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

Referring to FIG. 3, a gate oxide film 3 and a polysilicon film are deposited on the semiconductor substrate 1. Then, the predetermined partial patterning is performed to form the word line WL1 and the gate electrode 4b. The word line WL1 and the gate electrode 4b are preferably set in consideration of a spacer width and a contact area to be formed later. Then, sidewall spacers 6 are formed on both sidewalls of the word line WL1 and the gate electrode 4b. Impurities are implanted into regions of the semiconductor substrate 1 on both sides of the sidewall spacers 6 to form source and drain regions S and D. FIG. The first interlayer insulating film 7 is formed on the semiconductor substrate product. A contact hole is formed to expose the source region S on one side of the word line WL1. Since the sidewall spacer 6 of the word line WL1 is partially lost when forming the contact hole, the contact spacer 8 is formed on both sidewalls of the contact hole in order to prevent short circuit. Thereafter, the bit line 9 is formed in a known manner so as to contact the exposed source region S. After the second interlayer insulating film 10 is formed on the semiconductor substrate product on which the bit lines 9 are formed, the first and second interlayer insulating films 10 may be exposed so that a predetermined portion of the gate electrode 4b and the drain region D are simultaneously exposed. 7, 10) is etched to form a contact hole for a common connection node. Thereafter, the common connection line 11 is formed to contact the exposed gate electrode 4b and the common drain region D. FIG.

However, in the SRAM device, each word line and the gate electrode are spaced apart by a predetermined distance in consideration of the line width and the contact area of the spacer, whether or not the contact is formed.

In this way, although the contact is not formed, each gate electrode is spaced apart in consideration of the contact area, so that an unnecessary area exists in the active region.

As a result, the area of the active region is increased, and it is difficult to form a highly integrated SRAM device.

Accordingly, an object of the present invention is to provide a contact structure of a semiconductor device capable of reducing the area of an active region by adjusting the distance between gate electrodes, to solve the conventional problems described above.

In addition, another object of the present invention is to provide a method for forming a contact of a semiconductor device capable of forming contact holes without adjusting an interval between gate electrodes to form and etch processes between layers.

The contact structure of a semiconductor device according to the present invention for achieving the above object is to interpose a semiconductor substrate, an active region defined by an isolation layer on the semiconductor substrate, and a gate oxide film to pass over the active region of the semiconductor substrate; A plurality of gate electrodes of a plurality of pull-down and pass transistors formed, spacers formed on sidewalls of the plurality of gate electrodes, a plurality of source and drain regions formed in the active regions on both sides of the plurality of gate electrodes, and the plurality of gate electrodes; In a semiconductor device including a contact formed to selectively electrically connect the plurality of source and drain regions, the gate electrode is at least two times the line width of the spacer in the region where the contact is to be formed a distance apart from the adjacent gate electrode Become the contact In the area outside the station and between the double or less of the width of the spacer characterized in that the spacer is filled.

According to another aspect of the present invention, there is provided a method of forming a contact structure of a semiconductor device, the method comprising: sequentially forming a gate oxide film and a conductive layer for a gate electrode on a semiconductor substrate in which an active region and a contact predetermined region are defined; And forming a plurality of gate electrodes constituting a pull-down transistor and a pass transistor by patterning a gate oxide layer, and forming spacers on sidewalls of the plurality of gate electrodes. The distance between the electrode and the adjacent gate electrode may be formed to be at least twice the line width of the spacer in the contact region and less than twice the line width of the spacer in the non-contact region.

According to the present invention, the gate electrode is formed so as to be spaced at least twice as wide as the line width of the spacer formed on the sidewall in the contact predetermined region, and in the non-contact region, the gate electrode is not larger than twice the line width of the spacer formed on the sidewall. It is formed so as to be spaced apart. Then, at the same time as the spacer is formed, a contact hole is formed in the contact predetermined region, and is buried by the spacer in the other portion.

Accordingly, the distance between the gate electrodes can be reduced in the region where no contact is formed, and the active area is greatly reduced. In addition, since the contact hole can be formed without the interlayer insulating film forming process and the etching process, the process is shortened.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Example 1: Contact Forming Method of Semiconductor Device)

4A and 4B are cross-sectional views of respective processes for describing a method for forming a contact of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, a gate oxide film 21 and a conductive layer for a gate electrode are formed on the semiconductor substrate 20. Then, the gate electrode conductive layer and the gate oxide film 21 are partially patterned to form the gate electrodes 22a, 22b, and 22c. At this time, the intervals of the gate electrodes 22a, 22b, and 22c change depending on whether contact holes are formed. That is, if contact holes are to be formed between the gate electrodes, the gate electrodes are spaced apart by a distance of at least twice the width of the spacer line to be formed later. On the other hand, if a contact hole is not scheduled between the gate electrodes, the gate electrodes are formed such that the gap therebetween is not more than twice the line width of the spacer. Thereafter, an insulating film 23 for spacers is deposited on the resultant of the semiconductor substrate 20. At this time, the spacer insulating film 23 is formed in consideration of this to form a spacer having a desired line width.

Next, as shown in FIG. 4B, the spacer insulating film 23 is anisotropically etched to expose the surface of the gate electrodes 22a, 22b, and 22c, thereby forming the spacer 24. Then, in the portion where the distance between the gate electrodes 22a, 22b, and 22c is greater than twice the line width of the spacer, the semiconductor substrate, that is, the source and drain regions are exposed together with the formation of the spacer 24, so that the contact hole is not required without a separate interlayer insulating film. (H) is formed. On the other hand, in the part where the space | interval between gate electrodes is smaller than twice the line width of a spacer, the space | interval between gate electrodes is filled with the spacer 24, and a contact hole is not formed. Thereafter, impurities are implanted into the exposed contact holes to form source and drain regions S and D.

According to the above, the area of the contact hole does not have to be considered in the junction area where the contact hole is not formed, so that the area of the unnecessary active area can be reduced.

(Example 2: Contact Forming Method of SRAM Device)

FIG. 5 is a plan view showing an SRAM device according to Embodiment 2 of the present invention, and FIGS. 6A to 6E are diagrams for describing a contact forming method of an SRAM device according to Embodiment 2 of the present invention. It is sectional drawing which cut | disconnected 5 and the VI-VI 'line. 5 shows only a pair of pull-down transistors and a pair of pass-through transistors in the unit cell of the SRAM device.

Referring to FIG. 5, a predetermined portion of a semiconductor substrate (not shown) is field oxidized to define the device isolation region 32 and the first and second active regions A11 and A12. Here, the first active region A11 is a region where the first pull-down transistor Q3 (see FIG. 1) and the first pass-through transistor Q5 are to be formed, and the second active region A12 is the second pull-down transistor Q4. And a region in which the second pass transistor Q6 is formed.

First word line 34a (hereinafter referred to as first gate electrode) serving as the gate electrode of first pass-through transistor Q5, gate electrode 34b (hereinafter referred to as second gate electrode) and second pull-down of second pull-down transistor Q4 The gate electrode 34c (hereinafter referred to as the third gate electrode) of the transistor Q3 and the second word line 34d (hereinafter referred to as the fourth gate electrode) serving as the gate electrode of the second pass transistor Q6 are formed at predetermined intervals. .

In this case, the gate electrode at the portion where the bit line contact and the common connection node contact are to be formed is formed to be spaced apart by a distance of at least twice the line width of the spacer to be formed on the sidewall of the gate electrode. On the other hand, the gate electrode in the portion other than the contact scheduled region is formed at a distance not more than twice the width of the spacer line formed on the sidewall of the gate electrode.

Spacers (not shown) are formed on the sidewalls of the gate electrodes 34a-34b, and impurities are injected into the active regions A11 and A12 exposed to both sides of the gate electrodes 34a-34d, so that the source and drain regions ( S, D) are formed. Thus, each transistor Q3, Q4, Q5, Q6 is completed.

The bit line contact C1 is formed between the second word line 34d and the first pull-down transistor gate electrode 34c, and the common connection node C2 is formed in the common drain region of the first pull-down transistor and the first pass-through transistor. Is formed.

At this time, in the active region of the present embodiment, the spacing between the gate electrodes is significantly reduced compared to that of the conventional active region (see FIG. 2), so that the area of the active region can be reduced.

6A to 6E, the method for forming a contact of an SRAM device will be described in more detail.

Referring to FIG. 6A, the gate oxide film 33, the polysilicon film 340, and the hard mask film 340b are sequentially stacked on the semiconductor substrate 31 on which the device isolation film 32 is formed.

Thereafter, as shown in FIG. 6B, a predetermined portion of the hard mask layer 340b is etched to expose a predetermined portion of the polysilicon layer 340a.

Next, as shown in FIG. 6C, the hard mask layer 340b and the polysilicon layer 340a are partially etched to form first to fourth gate electrodes 34a, 34b, 34c, and 34d. In this case, the polysilicon layer 340a of the second gate electrode 34b is partially opened by the predetermined partial etching of the hard mask layer 340b. This is because the common connection line and the second gate electrode must then be contacted. In addition, an area in which a contact is to be formed, that is, between the second and third gate electrodes 34b and 34c in which a common connection node is formed and between the third and fourth gate electrodes 34c and 34d in which a bit line contact is to be formed is At least twice the line width of the spacer to be formed. Thereafter, source and drain low concentration impurity regions 35a and 35b are formed in the semiconductor substrate 31 opened from the gate electrodes 34a to 34d. Here, reference numeral 35a denotes a low concentration impurity region of the source predetermined region, and 35b denotes a low concentration impurity region of the drain predetermined region. Next, an insulating film 36 for spacers is deposited on the semiconductor substrate 31.

Then, as shown in Fig. 6D, the spacer insulating film 36 is anisotropically etched back until the surface of each of the gate electrodes 34a-34d is exposed, and then formed on both sidewalls of the gate electrodes 34a-34d. The spacer 37 is formed. In this case, spacers 37 are formed on sidewalls of the polysilicon film 340a and the hard mask film 340b in the second gate electrode 34b.

 Here, in the portion where the contact is to be formed, the impurity regions 35a and 35b are exposed only by forming the spacer 37 to form the contact holes H1 and H2, and the portion which is not the contact scheduled portion is filled by the spacer 37. It is done. Therefore, the contact hole can be formed only by the spacer forming step. In addition, since the hard mask layer 340b is formed on the gate electrode surface, a short between the gate electrodes and the conductive layer to be formed later can be prevented without a separate interlayer insulating layer forming process. Thereafter, high concentration impurities 38a and 38b are ion-implanted into the exposed contact holes H1 and H2 to form source and drain regions S and D.

Next, as shown in FIG. 6E, the common connection line 40a and the bit line 40b are formed of a polysilicon film so as to contact the exposed source and drain regions S and D. FIG.

As described above, when the contact forming method is applied to an SRAM device, the bit line contact hole and the common node line contact hole may be simultaneously formed, thereby reducing the process of depositing two interlayer insulating films and the process of forming two contact holes. .

As described in detail above, according to the present invention, in the contact predetermined region, the gate electrode is formed to be spaced at least about twice the line width of the spacer line width formed on the sidewall, and in the non-contact region, the gate electrode is disposed on the sidewall. It is formed to be spaced apart by a line width of less than twice the line width of the spacer to be formed. Then, at the same time as the spacer is formed, a contact hole is formed in the contact predetermined region, and is buried by the spacer in the other portion.

Accordingly, the distance between the gate electrodes can be reduced in the region where no contact is formed, and the active area is greatly reduced. In addition, since the contact hole can be formed without the interlayer insulating film forming process and the etching process, the process is shortened.

Furthermore, in the case of SRAM, since the bit line contact hole and the common node line contact hole can be formed at the same time, the number of processes can be greatly reduced.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

A gate electrode of a pull-down transistor and a pass transistor formed by interposing a semiconductor substrate, an active region defined by an isolation layer on the semiconductor substrate, a gate oxide film passing through an upper portion of the active region of the semiconductor substrate, and the plurality of gates; A spacer formed on an electrode sidewall, a plurality of source and drain regions formed in the active region on both sides of the plurality of gate electrodes, and a contact formed to selectively electrically connect the plurality of gate electrodes and the plurality of source and drain regions. In a semiconductor device comprising: The gate electrode is spaced apart from an adjacent gate electrode by more than twice the line width of the spacer in the region where the contact is to be formed, and by less than twice the line width of the spacer in the region other than the region where the contact is to be formed. A contact structure of a semiconductor device, characterized in that the filling. The contact structure of a semiconductor device according to claim 1, wherein said gate electrode has a laminated structure of a gate oxide film, a conductive layer, and a hard mask film. Sequentially forming a gate oxide film and a conductive layer for a gate electrode on a semiconductor substrate having a defined active area and a contact region, and patterning the conductive layer and the gate oxide film to form a plurality of gate electrodes constituting a pull-down transistor and a pass transistor. A method of manufacturing a semiconductor device comprising forming a spacer and forming spacers on sidewalls of the plurality of gate electrodes. Wherein the distance between the gate electrode and the adjacent gate electrode is greater than twice the line width of the spacer in the contact region and less than twice the line width of the spacer in the non-contact region. Method for forming a contact structure of the device. 4. The semiconductor device of claim 3, further comprising forming a hard mask film on the conductive layer for the gate electrode between the forming of the conductive layer for the gate electrode and the forming the gate electrode. Method of forming a contact structure.

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