JPH03270153A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH03270153A
JPH03270153A JP2070707A JP7070790A JPH03270153A JP H03270153 A JPH03270153 A JP H03270153A JP 2070707 A JP2070707 A JP 2070707A JP 7070790 A JP7070790 A JP 7070790A JP H03270153 A JPH03270153 A JP H03270153A
Authority
JP
Japan
Prior art keywords
film
region
mask
insulating film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2070707A
Other languages
Japanese (ja)
Inventor
Masaaki Uno
宇野 昌明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2070707A priority Critical patent/JPH03270153A/en
Publication of JPH03270153A publication Critical patent/JPH03270153A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To form an impurity region in a self-aligned manner by avoiding the part of a bird's beak of an oxide film by a method wherein an insulating film is left so as to be wider than the oxide film formed by a selective oxidation method and impurities are introduced into a semiconductor substrate by making use of the remaining insulating film as a mask. CONSTITUTION:An SiO2 film 16 formed by a selective oxidation method is covered; a resist pattern 19 is left from the end part of a bird's beak of the SiO2 film 16 up to its outside at about 0.1mum. Then, SiO2 films 18, 12 are etched and removed by making use of the resist pattern 19 as a mask; then, an element region (A) and an element isolation region (B) are formed. Then, arsenic ions are implanted selectively into an Si substrate 11 by making use of a gate electrode 21 and an SiO2 film 18a in the element isolation region (D) as a mask; after that, a heat treatment is executed; As is diffused deep; S/D regions (impurity regions) 22a to 22d are formed. Then, an SiO2 film is formed on the whole surface; after that, it is etched anisotropically; an SiO2 film 23 for insulation use of the gate electrode 21 is formed; then, a MIS transistor is completed.

Description

【発明の詳細な説明】 〔目 次〕 概要 産業上の利用分野 従来の技術(第2図) 発明が解決しようとする課題 課題を解決するための手段 作用 実施例(第1図) 発明の効果 〔概 要〕 半導体装置の製造方法に関し、更に詳しく言えば、選択
酸化法により素子分離領域を形成する工程を含む半導体
装置の製造方法に関し、選択酸化法に起因する結晶歪み
が半導体基板に生じた場合でも素子領域にその影響を及
ぼさないようにすることができる半導体装置の製造方法
を提供することを目的とし、 開口部を有する半導体基板上の酸化防止膜をマスフとし
て前記半導体基板を選択的に酸化し、前記080部内に
酸化膜を形成する工程と、前記酸化防止膜を除去する工
程と、前記半導体基板上に絶縁膜を堆積し、前記酸化膜
を被覆する工程と、前記絶縁膜表面にマスクを選択形成
し、該マスクを利用して前記絶縁膜を選択的に除去し、
前記形成された酸化膜の幅よりも大きい幅に残存する工
程と、前記残存する絶縁膜をマスクとして導電型不純物
を半導体基板に導入して不純物領域を形成する工程とを
含み槽底する。
[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 2) Examples of means and actions for solving the problem to be solved by the invention (Figure 1) Effects of the invention [Summary] Regarding a method of manufacturing a semiconductor device, more specifically, regarding a method of manufacturing a semiconductor device that includes a step of forming an element isolation region by a selective oxidation method, crystal distortion due to the selective oxidation method is generated in a semiconductor substrate. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the effect from affecting the element region even when the semiconductor substrate has an opening, and selectively processes the semiconductor substrate by using an anti-oxidation film on the semiconductor substrate as a mask. a step of oxidizing and forming an oxide film within the 080 portion; a step of removing the anti-oxidation film; a step of depositing an insulating film on the semiconductor substrate and covering the oxide film; selectively forming a mask and selectively removing the insulating film using the mask;
The method includes a step of remaining in a width larger than the width of the formed oxide film, and a step of introducing conductive impurities into the semiconductor substrate using the remaining insulating film as a mask to form an impurity region.

〔産業上の利用骨デf〕[Industrial use bone def]

本発明は、半導体装置の製造方法に関し、更に詳しく言
えば、選択酸化法により素子分動領域を形成する工程を
含む半導体装置の製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device including a step of forming an element separation region by a selective oxidation method.

〔従来の技術) 第2図(a)〜(d)は、従来例の素子分動領域の形成
方法をM I S (MetaI−1nsuIator
−5eaicoductor )  トランジスタの作
成に適用した場合について説明する断面図である。
[Prior Art] FIGS. 2(a) to 2(d) show a conventional method of forming an element switching region using an MIS (MetaI-1nsuIator).
-5eaicoductor) FIG. 5 is a cross-sectional view illustrating a case where the method is applied to fabrication of a transistor.

まず、同図(a)に示すように、p型のSi基板1上に
Si基板基板上5iJn膜の反応防止膜としてのSiO
□膜2と、酸化防止膜としての5iJ4H3とを順次形
成した後、これらをパターニングして素子分離領域(B
)を形成すべき領域に開口部4を形成する。続いて、開
口部4を介してSi基板1にp型の不純物を選択的にイ
オン注入する。その結果、開口部4の底部のs+基板1
にイオン注入領域5が形成される。
First, as shown in the same figure (a), a SiO2 film as a reaction prevention film for a 5iJn film on a Si substrate is formed on a p-type Si substrate 1.
□After sequentially forming film 2 and 5iJ4H3 as an oxidation prevention film, these are patterned to form element isolation regions (B
) is formed in the region where the opening 4 is to be formed. Subsequently, p-type impurity ions are selectively implanted into the Si substrate 1 through the opening 4. As a result, the s+ substrate 1 at the bottom of the opening 4
An ion implantation region 5 is formed.

次に、同図(b)に示すように、開口部4を介してSi
基板1表面を選択的に熱酸化する。その結果、素子分動
領域(B)にSiO□WIJ6が形成されるとともに、
既に導入されている不純物も拡散して広がり、StO□
膜6の周辺部にp°型の分離拡散領域5aが形成される
Next, as shown in FIG. 4(b), Si
The surface of the substrate 1 is selectively thermally oxidized. As a result, SiO□WIJ6 is formed in the element swing region (B), and
Impurities that have already been introduced also diffuse and spread, and StO□
A p° type isolation diffusion region 5a is formed at the periphery of the film 6.

次いで、Si3N、 M3を除去した後、全面をエツチ
ングして5in2膜2を除去する。次に、通常の工程を
経て素子領域(A)にゲート酸化膜となるSi0□欣7
及びゲート電極8を形成する(同図(c))。
Next, after removing Si3N and M3, the entire surface is etched to remove the 5in2 film 2. Next, through the usual process, Si0
Then, a gate electrode 8 is formed (FIG. 3(c)).

次いで、同図(d)に示すように、ゲート電極8及び素
子分動領域(B)のsio、J12aをマスクとしてS
i基板1にi!沢的にn型の不純物を導入してソース・
ドレイン(S/D)61域9a〜9dを形成する。
Next, as shown in the same figure (d), using the gate electrode 8 and sio and J12a of the element switching region (B) as a mask, S
i on board 1! By introducing a large amount of n-type impurities, the source
Drain (S/D) 61 regions 9a to 9d are formed.

その後、同図(e)に示すように、ゲート電極8を不図
示のS/D電極から絶縁するための絶縁膜!Oを形成す
ると、MISトランジスタが完成する。
Thereafter, as shown in FIG. 2(e), an insulating film is formed to insulate the gate electrode 8 from the S/D electrode (not shown). After forming O, the MIS transistor is completed.

(発明が解決しようとする18) ところで、第2図(b)に示す選択酸化法で1よSi3
N、 咬2からSt基板1に及ぼされる応力による歪み
により5iJalfff2の開口部4@にバーズビーク
が発生することは避けられない。
(18 to be solved by the invention) By the way, the selective oxidation method shown in FIG. 2(b)
N. It is inevitable that a bird's beak will occur at the opening 4@ of the 5iJalffff2 due to the strain caused by the stress exerted on the St substrate 1 from the bite 2.

従って、同図(e)に示すように、バーズビークの下の
St基板lには歪みが残っているため、ここに形成され
るS/D領域9a〜9dのpn接合部及びその近傍のs
+基板1に結晶欠陥が生しる場合があり、この結晶欠陥
を介してリーク電流が流れやすくなる。従って、S /
 D elf域9a〜9dとSi基板基板上間のリーク
電流が増えるので、半導体メモリなどのりフレッシュ特
性などが悪化するという問題がある。
Therefore, as shown in FIG. 6(e), since distortion remains in the St substrate l under the bird's beak, the pn junctions of the S/D regions 9a to 9d formed here and the s
+Crystal defects may occur in the substrate 1, and leakage current tends to flow through these crystal defects. Therefore, S/
Since the leakage current between the Delf regions 9a to 9d and the Si substrate increases, there is a problem that the paste freshness characteristics of semiconductor memories and the like deteriorate.

そこで本発明は、このような従来の問題点に鑑みてなさ
れたものであって、選択酸化法に起因する結晶歪みが半
導体基板に生した場合でも素子領域にその影響を及ぼさ
ないようにすることができる半導体装置の製造方法を提
供することを目的とするものである。
The present invention has been made in view of these conventional problems, and aims to prevent crystal distortion caused by selective oxidation from affecting the element region even if crystal distortion occurs in the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows for the manufacturing of semiconductor devices.

(課題を解決するための手段) 上記課題は、開口部を有する半導体基板上の酸化防止膜
をマスクとして前記半導体基板を選択的に酸化し、前記
開口部内に酸化膜を形成する工程と、前記酸化防止膜を
除去する工程と、前記半導体基板上にtI!、Ii n
’J、を堆積し、前記酸化膜を被覆する工程と、前記絶
縁膜表面にマスクを選択形成し、該マスクを利用して前
記絶縁膜を選択的に除去し、前記形成された酸化膜の幅
よりも大きい幅に残Hする工程と、前記残存する絶縁膜
をマスクとして導電型不純物を半導体基板に導入して不
純物領域を形成する工程とを有することを特徴とする半
導体装置の製造方法によって達成される。
(Means for Solving the Problems) The above problems include a step of selectively oxidizing the semiconductor substrate using an oxidation prevention film on the semiconductor substrate having an opening as a mask to form an oxide film in the opening; A step of removing the anti-oxidation film and applying tI! on the semiconductor substrate. , Ii n
'J, to cover the oxide film, selectively forming a mask on the surface of the insulating film, selectively removing the insulating film using the mask, and removing the formed oxide film. A method for manufacturing a semiconductor device, comprising: a step of leaving H in a width larger than the width; and a step of introducing a conductivity type impurity into a semiconductor substrate using the remaining insulating film as a mask to form an impurity region. achieved.

[作 用] 本発明の半導体装置の製造方法によれば、選択酸化法に
より形成された酸化膜の幅よりも大きい幅に絶縁膜を残
在しているので、この残在する絶縁膜をマスクとして半
導体基板に不純物を導入することにより酸化膜のバーズ
ビークの部分を避けて自己整合的に不純物領域を形成す
ることができる。
[Function] According to the method for manufacturing a semiconductor device of the present invention, since the insulating film remains with a width larger than the width of the oxide film formed by the selective oxidation method, this remaining insulating film is masked. By introducing impurities into the semiconductor substrate, an impurity region can be formed in a self-aligned manner avoiding the bird's beak portion of the oxide film.

これにより、選択酸化法に用いる5iJa WJからの
応力に起因する結晶歪みが半導体基板に生した場合でも
素子領域にその影響を及ぼさないようにすることができ
る。
Thereby, even if crystal distortion occurs in the semiconductor substrate due to stress from the 5iJa WJ used in the selective oxidation method, it can be prevented from affecting the element region.

〔実施例) 以下、本発明の実施例について図を参照しながら具体的
に説明する。
[Example] Hereinafter, examples of the present invention will be specifically described with reference to the drawings.

第1図(a)〜(h)は、本発明の実施例の選択酸化法
を用いた素子分離領域の形成方法をMIS (Meta
l−Insulator−5emiconductor
 )  トランジスタの作成に適用した場合について説
明する断面図である。
FIGS. 1(a) to 1(h) show a method for forming an element isolation region using a selective oxidation method according to an embodiment of the present invention using MIS (Meta
l-Insulator-5emiconductor
) FIG. 2 is a cross-sectional view illustrating a case where the method is applied to fabrication of a transistor.

まず、同図(a)に示すように、p型のSi5板(半導
体基板)11上に熱酸化法により温度900°Cの条件
でSi基板11とSi、N、膜との反応防止膜としての
P!膜膜厚5註00 CV D (Che+5ical Vapor Dep
osition )法によりこの5i02膜12上に膜
厚約1000Åの513N4 WIJl 3を形成する
First, as shown in the same figure (a), a reaction prevention film between the Si substrate 11 and Si, N, and films was formed on a p-type Si5 plate (semiconductor substrate) 11 by thermal oxidation at a temperature of 900°C. The P! Film thickness 500 CV D (Che+5ical Vapor Dep
A 513N4 WIJl 3 having a thickness of about 1000 Å is formed on the 5i02 film 12 by the 513N4 WIJl 3 film (position) method.

次に、素子分離領域(B)を形成すべき領域に不図示の
開口部を有するレジストパターンを形成した後、このレ
ジストパターンをマスクとしてCF4/l’hガスを用
いたドライエツチング法によりSi、N、膜I3を選択
的にエツチングする。続いてC11hガスを用いたドラ
イエンチング法により5i02膜12をエツチングして
開口部14を形成した後、開口部14底部のSi基Fi
、11に加速電圧100keVドーズIll XIO”
cm−”の条件でp型不純物のボロンを選択的にイオン
注入し、イオン注入領域15を選択的に形成する(同図
(b))。
Next, after forming a resist pattern having an opening (not shown) in the region where the element isolation region (B) is to be formed, Si, N, selectively etching film I3. Subsequently, the 5i02 film 12 is etched by a dry etching method using C11h gas to form an opening 14, and then the Si-based Fi film at the bottom of the opening 14 is etched.
, acceleration voltage 100 keV dose Ill XIO”
Boron, which is a p-type impurity, is selectively ion-implanted under the condition of "cm-" to selectively form an ion-implanted region 15 (FIG. 3(b)).

次いで、ウェット02ガスを用いた熱酸化法により温度
1000°Cの条件で残存する5i3Na v!(酸化
防止Jlff)13aをマスクとしてSi基板11を′
Jj!、沢的に酸化し、膜厚約3000大のSLO□N
 (酸化膜)16を形成するとともに、イオン注入領域
15のポロンをより深く拡散し、p゛型の分離拡散領域
15aを形成する。このとき、Si、N、 rPj、1
3aからの応力による歪みによりバーズビーク17が開
口部14の周辺部に形成される。(同図(C))。
Next, a thermal oxidation method using wet 02 gas was applied to the residual 5i3Na v! at a temperature of 1000°C. (Anti-oxidation Jlff) Using 13a as a mask, Si substrate 11 is
Jj! , SLO□N is heavily oxidized and has a film thickness of approximately 3000 mm.
(Oxide film) 16 is formed, and poron in the ion implantation region 15 is diffused deeper to form a p'-type isolation diffusion region 15a. At this time, Si, N, rPj, 1
A bird's beak 17 is formed at the periphery of the opening 14 due to distortion due to the stress from 3a. (Figure (C)).

次に、残存する5isN、膜13aを除去した後、CV
 D (Chemical Vapor Deposi
口on )法によりSi基Fi11全面に510□膜(
絶縁膜)18を形成する(同図(d))。
Next, after removing the remaining 5isN and film 13a, CV
D (Chemical Vapor Deposit
A 510□ film (
An insulating film) 18 is formed ((d) in the same figure).

次いで、選択酸化法により形成されたSiO□膜16を
被覆して、sio、HI 6のバーズビーク端部から0
.17ym程度外側までレジストパターン19を残在さ
せる。
Next, a SiO□ film 16 formed by a selective oxidation method is coated, and 0
.. The resist pattern 19 is left to the outside by about 17 ym.

次に、レジストパターン19をマスクとしてSiO□I
IΔ18.12をエツチング・除去すると、素子領域(
A)及び素子分RjJ ’pm域(B)が形成される(
同図(e))。
Next, using the resist pattern 19 as a mask, SiO□I
When IΔ18.12 is etched and removed, the element region (
A) and elemental RjJ 'pm region (B) are formed (
Figure (e)).

次に、Si基板11を熱酸化して素子領域(A)にゲー
ト酸化数となる膜厚約300人のSiO2膜2。
Next, the Si substrate 11 is thermally oxidized to form an SiO2 film 2 with a thickness of about 300 in the element region (A) to the gate oxidation number.

を形成した後、CVD法によりゲート電極となる膜厚約
3000Åのポリシリコン膜を形成する。続いて、この
ポリシリコン膜をパターニングしてゲート電極21を形
成する(同図(f))。
After forming, a polysilicon film having a thickness of about 3000 Å, which will become a gate electrode, is formed by CVD. Subsequently, this polysilicon film is patterned to form a gate electrode 21 (FIG. 4(f)).

次いで、ゲート電極21及び素子分離領域(B)のSi
ng膜18aをマスクとしてSil仮11にi!沢的に
砒素(As)をイオン注入した後、加熱処理を行い、A
sを深く拡散してS / D ftI域(不純物領域)
22a〜22dを形成する。なお、図中符号22c。
Next, Si of the gate electrode 21 and the element isolation region (B) is
Using the NG film 18a as a mask, apply i! to the Sil temporary 11! After a large amount of arsenic (As) is ion-implanted, heat treatment is performed, and A
Diffuse s deeply to create S/D ftI region (impurity region)
22a to 22d are formed. In addition, the reference numeral 22c in the figure.

22dは分鰭拡rPi領域15aを介して隣接するM!
s!ランジスタのS / D fi、II域である(同
図(g))。
22d is an adjacent M! through the fin expansion rPi region 15a.
s! This is the S/D fi, II region of the transistor ((g) in the same figure).

次に、全面に510□膜を形成した後、異方性エツチン
グして、ゲート電極21の絶縁用のSiO□膜23膜形
3膜形3MISトランジスタが完成する(同図(h))
Next, after forming a 510□ film on the entire surface, anisotropic etching is performed to complete a 3-film type 3MIS transistor with 23 SiO□ films for insulating the gate electrode 21 ((h) in the same figure).
.

以上のように、本発明の実施例によれば、選択酸化法に
より形成されたSiO□M16の幅よりも大きい幅に上
のSiO,膜I8aを残存しているので、この残存する
SiO□膜18aをマスクとしてSi基板11にAsを
導入することにより5toJ l 6のバーズビーク1
7の部分を避けて自己整合的にS/D領域22a〜22
dを形成することができる。
As described above, according to the embodiment of the present invention, since the upper SiO film I8a remains in a width larger than the width of the SiO□M16 formed by the selective oxidation method, this remaining SiO□ film By introducing As into the Si substrate 11 using 18a as a mask, a bird's beak 1 of 5 to J l 6 is formed.
S/D areas 22a to 22 in a self-aligned manner avoiding the part 7.
d can be formed.

従って、選択酸化法に用いる5iiNa膜13aからの
応力に起因する結晶歪みが5iIvil lに生じた場
合でも素子領域(A)にその影響を及ぼさないようにす
ることができる。
Therefore, even if crystal distortion occurs in 5iIvil due to stress from the 5iiNa film 13a used in the selective oxidation method, it can be prevented from affecting the element region (A).

このため、結晶歪みに起因するS / D H域22a
〜22dとSi基板11との間のリーク電流の増加を防
止することができる。
Therefore, the S/DH region 22a caused by crystal distortion
An increase in leakage current between ~22d and the Si substrate 11 can be prevented.

これにより、半導体装置の高密度化及び特性や信頼度の
向上を図ることができる。
Thereby, it is possible to increase the density and improve the characteristics and reliability of the semiconductor device.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明の半導体装置の製造方法によれば
、l[酸化法により形成された絶縁膜の幅よりも大きい
幅に上の絶縁膜を残存しているので、この残存する絶縁
膜をマスクとして半導体基板に不純物を導入することに
より選択酸化して形成された絶縁膜のバーズビークの部
分を避けて自己整合的に不純物領域としてのS/D領域
などを形成することができる。
As described above, according to the method for manufacturing a semiconductor device of the present invention, since the upper insulating film remains with a width larger than the width of the insulating film formed by the oxidation method, this remaining insulating film By introducing impurities into the semiconductor substrate using the mask as a mask, an S/D region or the like as an impurity region can be formed in a self-aligned manner while avoiding the bird's beak portion of the insulating film formed by selective oxidation.

従って、選択酸化法に用いる5izes膜からの応力に
起因する結晶歪みが半導体基板に生じた場合でも素子領
域にその影響を及ぼさないようにすることができる。
Therefore, even if crystal distortion occurs in the semiconductor substrate due to stress from the 5izes film used in the selective oxidation method, it can be prevented from affecting the element region.

このため、結晶歪みに起因するS / D eM域と半
導体基板との間のリーク電流の増加を防止することがで
きる。
Therefore, an increase in leakage current between the S/DeM region and the semiconductor substrate due to crystal distortion can be prevented.

これにより、半導体装置の高密度化及び特性や信頼度の
向上を図ることができる。
Thereby, it is possible to increase the density and improve the characteristics and reliability of the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の実施例の素子骨N領域の作成方法を
説明する断面図、 第2図は、従来例の素子分離領域の作成方法を説明する
断面図である。 〔符号の説明] 1・・・Si基板、 2.6,10.12,20.23・・・5i02膜、3
・・・SiJ、膜、 4.14・・・開口部、 5□ 15・・・イオン注入領域、 5a、15a・・・分離拡散領域、 7a、20a・・・ゲート酸化膜、 8.21・・・ゲート電極、 9 a〜9d・−3/Df+1域、 11・・・Si基板(半導体基板)、 13.13a”・SiJ、n (酸化防止gす、16・
・・SiO□膜(酸化W!J)、17・・・バーズビー
ク、 1 B 、 18a ・=SlOt膜(絶縁膜)、19
・・・レジストパターン、 22 a 〜22 d −S / D fiJl域(不
純物領域)、A・・・素子領域、 B・・・素子分離領域。
FIG. 1 is a sectional view illustrating a method for creating an element bone N region according to an embodiment of the present invention, and FIG. 2 is a sectional view illustrating a method for creating an element isolation region in a conventional example. [Explanation of symbols] 1...Si substrate, 2.6, 10.12, 20.23...5i02 film, 3
...SiJ, film, 4.14...opening, 5□ 15...ion implantation region, 5a, 15a...isolation diffusion region, 7a, 20a...gate oxide film, 8.21.・・Gate electrode, 9 a to 9d・−3/Df+1 region, 11・Si substrate (semiconductor substrate), 13.13a”・SiJ, n (oxidation prevention gas, 16・
...SiO□ film (oxidized W!J), 17...Bird's beak, 1 B, 18a ・=SlOt film (insulating film), 19
...Resist pattern, 22a to 22d-S/D fiJl region (impurity region), A...device region, B...device isolation region.

Claims (1)

【特許請求の範囲】[Claims]  開口部を有する半導体基板上の酸化防止膜をマスクと
して前記半導体基板を選択的に酸化し、前記開口部内に
酸化膜を形成する工程と、前記酸化防止膜を除去する工
程と、前記半導体基板上に絶縁膜を堆積し、前記酸化膜
を被覆する工程と、前記絶縁膜表面にマスクを選択形成
し、該マスクを利用して前記絶縁膜を選択的に除去し、
前記形成された酸化膜の幅よりも大きい幅に残存する工
程と、前記残存する絶縁膜をマスクとして導電型不純物
を半導体基板に導入して不純物領域を形成する工程とを
有することを特徴とする半導体装置の製造方法。
a step of selectively oxidizing the semiconductor substrate using an oxidation prevention film on a semiconductor substrate having an opening as a mask to form an oxide film in the opening; a step of removing the oxidation prevention film; depositing an insulating film on and covering the oxide film; selectively forming a mask on the surface of the insulating film; and selectively removing the insulating film using the mask;
The method is characterized by comprising a step of remaining in a width larger than the width of the formed oxide film, and a step of introducing a conductivity type impurity into the semiconductor substrate using the remaining insulating film as a mask to form an impurity region. A method for manufacturing a semiconductor device.
JP2070707A 1990-03-20 1990-03-20 Manufacture of semiconductor device Pending JPH03270153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2070707A JPH03270153A (en) 1990-03-20 1990-03-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2070707A JPH03270153A (en) 1990-03-20 1990-03-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03270153A true JPH03270153A (en) 1991-12-02

Family

ID=13439330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2070707A Pending JPH03270153A (en) 1990-03-20 1990-03-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03270153A (en)

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