JPH03263339A - Film carrier and semiconductor device - Google Patents

Film carrier and semiconductor device

Info

Publication number
JPH03263339A
JPH03263339A JP2061554A JP6155490A JPH03263339A JP H03263339 A JPH03263339 A JP H03263339A JP 2061554 A JP2061554 A JP 2061554A JP 6155490 A JP6155490 A JP 6155490A JP H03263339 A JPH03263339 A JP H03263339A
Authority
JP
Japan
Prior art keywords
leads
film carrier
chip
width
widths
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2061554A
Other languages
Japanese (ja)
Other versions
JP2533216B2 (en
Inventor
Eiji Aoki
英二 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2061554A priority Critical patent/JP2533216B2/en
Publication of JPH03263339A publication Critical patent/JPH03263339A/en
Application granted granted Critical
Publication of JP2533216B2 publication Critical patent/JP2533216B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid inappropriate positional shift or joint of a film carrier for tape-automated-bonding by a method wherein the widths of the leads of the film carrier corresponding to the corner part of an IC chip are made to be wider than the widths of the other leads and the IC chip is mounted by using such film carrier. CONSTITUTION:The widths of eight corner leads 3 corresponding to the corner of an LSI are made to be 60mum which is larger than 40mum, the widths of normal leads 4. Or, the width of the corner lead 3 at the end is 60mum and the width is reduced successively by 4mum until the width becomes 40mum. Practically, as outer lead bonding(OLB) is more difficult than inner lead bonding-(ILB), it is recommended that the width of the parts of the leads for OLB is only 40mum and the widths of the other parts is 60mum. In order to mount an IC chip 1 with this film carrier 2, the leads 3 of the film carrier 2 are bonded to the bumps 4 of the IC chip 1 by ILB, the leads 3 are bonded to a package 5 by OLB and a cap 7 is attached so as to have the LSI chip face-down or face-up.

Description

【発明の詳細な説明】 〔概要〕 本発明は、テープオートメイテッドボンディング（ＴＡ
Ｂ）用のフィルムキャリアのリードに関し。[Detailed Description of the Invention] [Summary] The present invention provides tape automated bonding (TA
Regarding the lead of the film carrier for B).

インナーリードポンディング（ＩＬＢ）時のストレスに
よるリード変形を防止することを目的とし■テープオー
トメイテッドボンディングを行うフィルムキャリアにお
いて。■For film carriers that perform tape automated bonding with the aim of preventing lead deformation due to stress during inner lead bonding (ILB).

ＩＣチップのコーナーの位置に相当するフィルムキャリ
ア上の相対するリードの幅がその他のリードの幅より太
くなっているように。Just like the width of the opposing leads on the film carrier corresponding to the corner positions of the IC chip is wider than the width of the other leads.

■前記フィルムキャリアを使用してマウントするように
構成する。(2) It is configured to be mounted using the film carrier.

〔産業上の利用分野〕[Industrial application field]

本発明は、　ＴＡＢのフィルムキャリアのリードに関す
る。The present invention relates to a TAB film carrier lead.

近年、ＬＳＩの高集積化に伴い、その接続するビン数も
増加の一途を辿っている。In recent years, as LSIs become more highly integrated, the number of connected bins continues to increase.

そのため、　ＴＡＢ構造による。すなわち、チップ上の
バンプに、−括数百本のリードをボンディングし、更に
、そのリードを一括ボンディングでパッケージパターン
に接続する方法が採られるようになってきた。Therefore, it depends on the TAB structure. That is, a method has been adopted in which hundreds of leads are bonded to bumps on a chip, and the leads are then connected to a package pattern by batch bonding.

〔従来の技術〕[Conventional technology]

第４図は従来例の説明図である。 FIG. 4 is an explanatory diagram of a conventional example.

図において、１１はＩＣチップ、１２はフィルムキャリ
ア、１３はリード、１４はバンブ、１５はパッケージ、
　１６はビン、１７はキャップ、１８はソルダー、１９
はヒートシンク　である。In the figure, 11 is an IC chip, 12 is a film carrier, 13 is a lead, 14 is a bump, 15 is a package,
16 is a bottle, 17 is a cap, 18 is a solder, 19
is a heat sink.

現行のフィルムキャリアを用いるＴＡＢ構造では第４図
（ａ）に模式断面図で示すような構造となっている。The TAB structure using the current film carrier has a structure as shown in a schematic cross-sectional view in FIG. 4(a).

即ち、ＩＣチップ１１はリード１３を介してパッケージ
１５と接続されている。That is, the IC chip 11 is connected to the package 15 via the leads 13.

このインナリードポンディング（ＩＬＢ）されたり一ド
１３の状態を詳細に見ると、第４図（ｂ）に示すように
、フィルムキャリア１２上にパタニングされたリード１
３はバンプ１４を介して、ＩＣチップ１１と接続されて
いる。If we look in detail at the state of the leads 13 after inner lead bonding (ILB), we can see that the leads 13 patterned on the film carrier 12 are shown in FIG.
3 is connected to the IC chip 11 via bumps 14.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前記のように、　１１８時にフィルムキャリア１２上の
リードをＩＣチップ１１上のバンブ１４に加熱接合する
際に、フィルムキャリア１２のフィルム母材及びリード
材の熱膨張及び収縮によって、特にコーナー付近にねじ
れ等の応力が生じ、歪みがたまって、リード１３が変形
して曲がったり、ずれたりする。As mentioned above, when the leads on the film carrier 12 are heat-bonded to the bumps 14 on the IC chip 11 at 118, due to thermal expansion and contraction of the film base material and lead material of the film carrier 12, twisting occurs particularly near the corners. Stresses such as these are generated, distortion accumulates, and the leads 13 are deformed and bent or shifted.

そのために、その後のアウターリードポンディング（Ｏ
ＬＢ）でパッケージ１５上のリード接続パターンと位置
合わせが良好にできなくなる。Therefore, subsequent outer lead pounding (O
LB), the lead connection pattern on the package 15 cannot be properly aligned.

〔課題を解決するための手段〕[Means to solve the problem]

第１図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.

図において、１はＩＣチップ、２はフィルムキャリア　
３はコーナーリード、４はリードである。In the figure, 1 is an IC chip, 2 is a film carrier
3 is a corner lead and 4 is a lead.

解決手段として、テープオートメイテッドポンディング
を行うフィルムキャリアにおいて、ＩＣチップのコーナ
ーの位置に相当するフィルムキャリア上の相対するリー
ドの幅がその他のリードの幅より太くなっているように
し、前記フィルムキャリアを使用してマウントする。As a solution, in a film carrier that performs tape automated bonding, the width of opposing leads on the film carrier corresponding to the corner positions of the IC chip is made wider than the width of other leads, and the film carrier Mount it using

〔作用〕[Effect]

本発明では、ＩＣチップのコーナ一部分のリードを太く
強化するので、　１１８時の加熱によっても歪んだり曲
がったりしない。In the present invention, the leads at the corners of the IC chip are thickened and strengthened, so they will not be distorted or bent even when heated at 118 o'clock.

よって、正常なポンディングが可能となる。Therefore, normal pounding is possible.

〔実施例〕〔Example〕

第２図、第３図は本発明の詳細な説明図である。 FIGS. 2 and 3 are detailed explanatory diagrams of the present invention.

図において、１はＩＣチップ、２はフィルムキャリア、
３はコーナーリード、４はリード、５はパッケージ、６
はビン、７はキャップ、８はソルダー　９はヒートシン
ク、１０はフィンである。In the figure, 1 is an IC chip, 2 is a film carrier,
3 is corner lead, 4 is lead, 5 is package, 6
is a bottle, 7 is a cap, 8 is a solder, 9 is a heat sink, and 10 is a fin.

第１図、第２図により第１の実施例を説明する。A first embodiment will be explained with reference to FIGS. 1 and 2.

第１図に示すように、６００本のビンを有するＬＳＩに
おいて　、−辺当たり１５０本のリードのうち、コーナ
ーの相対する８本のコーナーリード４の幅を通常のり一
ド３の４０μｍ幅に対して、６０μｍと太（する。As shown in Figure 1, in an LSI with 600 bins, of the 150 leads per side, the width of the eight corner leads 4 facing each other at the corners is 40 μm compared to the 40 μm width of the normal glued lead 3. The thickness is 60 μm.

第２図（ａ）に示すように、各辺のコーナーより、中心
に向かって少しづつ細くした例である。As shown in FIG. 2(a), this is an example in which each side is tapered little by little from the corner toward the center.

一番端のコーナーリード４が６０μｍ幅で、内側に４μ
ｍずつ狭くして、４０μｍ幅になったらそのままとする
。The corner lead 4 at the end is 60μm wide, with 4μm inside.
Narrow the width in m increments until it becomes 40 μm wide, then leave it as it is.

上記の例では、コーナーリード４を均一な幅で太くした
が、実際にはＩＬＢよりＯＬＢの方が難しく。In the above example, the corner leads 4 are made thick with a uniform width, but in reality, OLB is more difficult than ILB.

特に金・錫反応による接合では、　０１８間の合金ショ
ートを発生し易いので、第２図（ｂ）に示すように、　
ＯＬＢの部分のみを通常の４０μｍ幅とし、その他の部
分を６０μｍ幅とした。Particularly in bonding by gold-tin reaction, alloy shorts between 018 and 018 are likely to occur, so as shown in Figure 2(b),
Only the OLB portion was made to have a normal width of 40 μm, and the other portions were made to have a width of 60 μm.

以上９本発明のリードを使用したフィルムキャリアを用
いて、実際に半導体装置をマウントした第２の実施例を
第３図に示す。FIG. 3 shows a second embodiment in which a semiconductor device is actually mounted using a film carrier using the leads of the present invention.

第３図（ａ）はフィルムキャリア２のリード３を、ＩＣ
チップ１上のバンプ４にＩＬＢを行った断面図である。FIG. 3(a) shows the lead 3 of the film carrier 2 connected to the IC
3 is a cross-sectional view of bumps 4 on chip 1 subjected to ILB. FIG.

続いて、リード３をパッケージ５にＯＬＢを行い。Next, lead 3 is subjected to OLB to package 5.

キャップを被せるが、第３図（ｂ）はＬＳＩチップがフ
ェイスダウンタイプの場合であり、第３図（Ｃ）はＬＳ
Ｉチップがフェイスアップタイプの場合である。Figure 3 (b) shows the case where the LSI chip is a face-down type, and Figure 3 (C) shows the case where the LSI chip is a face-down type.
This is a case where the I-chip is a face-up type.

〔発明の効果〕〔Effect of the invention〕

以上説明したように５本発明によれば、　ＩＬＢ後のリ
ード変形の心配がないため、　ＩＬＢのボンデング条件
を強めにでき例えば金・錫接続では温度を３２０°Ｃか
ら３５０“Ｃへと上げられるので、接合性が向上する。As explained above, according to the present invention, there is no need to worry about lead deformation after ILB, so the ILB bonding conditions can be strengthened, and the temperature can be raised from 320°C to 350"C for gold-tin connections, for example. Therefore, bondability is improved.

また、パッケージのリード接続パターンとの位置合わせ
が容易となって２位置ずれ不良や接合不良が減少し、約
１０％の歩留りアップとともに。In addition, alignment with the package lead connection pattern becomes easier, reducing two-position misalignment defects and bonding defects, and increasing yield by about 10%.

リード間の信頼性の向上が図られる。Reliability between leads can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第４図は従来例の説明図 である。 図において。 １はＩＣチップ、　　　２はフィルムキャリアはコーナ
ーリード。 はパッケージ。 はキャップ はヒートシンク。 ４はリード ６はビン。 ８はソルダー ｌＯはフィンFIG. 4 is an explanatory diagram of a conventional example. In fig. 1 is an IC chip, 2 is a film carrier with a corner lead. is a package. The cap is a heat sink. 4 is lead and 6 is bottle. 8 is solder lO is fin

Claims (1)

【特許請求の範囲】 １）テープオートメイテッドボンディングを行うフィル
ムキャリアにおいて、 ＩＣチップのコーナーの位置に相当するフィルムキャリ
ア上の相対するリードの幅がその他のリードの幅より太
くなっていることを特徴とするフィルムキャリア。 ２）前記請求項１記載のフィルムキャリアを使用してマ
ウントすることを特徴とする半導体装置。[Claims] 1) A film carrier for tape automated bonding, characterized in that the width of opposing leads on the film carrier corresponding to the corner positions of the IC chip is wider than the width of other leads. film carrier. 2) A semiconductor device mounted using the film carrier according to claim 1.
JP2061554A 1990-03-13 1990-03-13 Film carrier and semiconductor device Expired - Fee Related JP2533216B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2061554A JP2533216B2 (en) 1990-03-13 1990-03-13 Film carrier and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2061554A JP2533216B2 (en) 1990-03-13 1990-03-13 Film carrier and semiconductor device

Publications (2)

Publication Number Publication Date
JPH03263339A true JPH03263339A (en) 1991-11-22
JP2533216B2 JP2533216B2 (en) 1996-09-11

Family

ID=13174448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2061554A Expired - Fee Related JP2533216B2 (en) 1990-03-13 1990-03-13 Film carrier and semiconductor device

Country Status (1)

Country Link
JP (1) JP2533216B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729941A (en) * 1993-07-13 1995-01-31 Nec Corp Carrier tape for tab type semiconductor device
JP2010529673A (en) * 2007-06-07 2010-08-26 シリコン・ワークス・カンパニー・リミテッド Pad layout structure of semiconductor chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729941A (en) * 1993-07-13 1995-01-31 Nec Corp Carrier tape for tab type semiconductor device
JP2010529673A (en) * 2007-06-07 2010-08-26 シリコン・ワークス・カンパニー・リミテッド Pad layout structure of semiconductor chip

Also Published As

Publication number Publication date
JP2533216B2 (en) 1996-09-11

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