JPH09283696A - Semiconductor hybrid mounting method - Google Patents
Semiconductor hybrid mounting methodInfo
- Publication number
- JPH09283696A JPH09283696A JP8092357A JP9235796A JPH09283696A JP H09283696 A JPH09283696 A JP H09283696A JP 8092357 A JP8092357 A JP 8092357A JP 9235796 A JP9235796 A JP 9235796A JP H09283696 A JPH09283696 A JP H09283696A
- Authority
- JP
- Japan
- Prior art keywords
- bare
- substrate
- tab
- mounting method
- module substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体ＩＣの実装
に関し、特に複数のＩＣをモジュール化して実装するマ
ルチチップモジュール（以下、ＭＣＭという）に使用す
る半導体混載実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting of semiconductor ICs, and more particularly to a semiconductor mixed mounting method used in a multi-chip module (hereinafter referred to as MCM) for mounting a plurality of ICs in a module.
【０００２】[0002]
【従来の技術】図３は、従来の半導体混載実装方法によ
り実装されたＭＣＭの上面図を示しており、図４は、従
来の半導体混載実装方法により実装されたＭＣＭの樹脂
封止後の側面図である。2. Description of the Related Art FIG. 3 shows a top view of an MCM mounted by a conventional semiconductor mixed mounting method, and FIG. 4 shows a side surface of a MCM mounted by a conventional semiconductor mixed mounting method after resin sealing. It is a figure.
【０００３】図３及び図４において、複数のＩＣ３１は
モジュール基板３２にそれぞれ実装され、金（Ａｕ）線
等のワイヤー３３によりワイヤーボンディングした後
に、封止樹脂３４により封止されＭＣＭとして完成す
る。その後に、他の部品とともにＭＣＭは、ハンダ３５
等によりマザー基板３６に接合される。In FIGS. 3 and 4, a plurality of ICs 31 are mounted on a module substrate 32, wire-bonded with wires 33 such as gold (Au) wires, and then sealed with a sealing resin 34 to complete an MCM. After that, the MCM, along with other components
It is bonded to the mother substrate 36 by the above.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体混載実装方法では、ＩＣの数が増加した場
合、モジュール基板の面積が大きくなるにしたがい、モ
ジュール基板の反りが大きくなり、モジュール基板とマ
ザー基板との接合部に短絡あるいは未接合などの接合不
良が発生するという問題があった。However, in the conventional semiconductor mixed mounting method described above, when the number of ICs is increased, the warp of the module substrate is increased as the area of the module substrate is increased. There is a problem that a joint failure such as a short circuit or a non-joint occurs at the joint with the substrate.
【０００５】また、ＩＣにワイヤーボンディング法を用
いた場合には樹脂封止を行うため、モジュール基板の面
積が大きくなって封止する樹脂量が増加すると、封止樹
脂とモジュール基板との熱膨脹係数の違いからモジュー
ル基板の反りがさらに大きくなり接合不良の原因となる
ものであった。Further, when the wire bonding method is used for the IC, resin encapsulation is performed. Therefore, when the area of the module substrate increases and the amount of encapsulating resin increases, the coefficient of thermal expansion between the encapsulating resin and the module substrate increases. Due to the difference between the two, the warp of the module substrate is further increased, which causes a defective joint.
【０００６】さらに、品質保証されたベアＩＣ（以下、
ＫＧＤ（Known Good Die）という）が入手困難な場合
に、モジュール化したい全てのＩＣがＫＧＤで存在しな
いために、ＭＣＭ化できない場合が多く発生していた。[0006] Furthermore, the quality-guaranteed bare IC (hereinafter,
When it is difficult to obtain a KGD (Known Good Die), all the ICs that are desired to be modularized do not exist in the KGD, so that there are many cases where the MCM cannot be implemented.
【０００７】本発明は、上記従来の問題点を解決するも
のであり、安価な基板を用いても接合不良を起こすこと
なく、モジュール化したいＩＣのＫＧＤが揃わない場合
にもＭＣＭ化することのできる半導体混載実装方法を提
供することを目的とするものである。The present invention solves the above-mentioned problems of the prior art. Even if an inexpensive substrate is used, a bonding failure does not occur, and even if the KGDs of the ICs to be modularized are not complete, the MCMs can be formed. An object of the present invention is to provide a semiconductor mixed mounting method that can be performed.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するために、ベアＩＣとＴＡＢとを絶縁性接着剤を介
して接着し、上記ベアＩＣをフェースダウンで封止樹脂
を介して基板にフリップチップ実装し、上記ＴＡＢのア
ウタリードを上記基板に実装するようにしたものであ
る。In order to achieve the above object, the present invention adheres a bare IC and a TAB with an insulating adhesive, and the bare IC is face-down with a sealing resin. The substrate is flip-chip mounted and the TAB outer leads are mounted on the substrate.
【０００９】以上により、安価な基板を用いても接合不
良を起こすことなく、モジュール化したいＩＣのＫＧＤ
が揃わない場合にも、ＭＣＭ化することのできるもので
ある。As described above, the KGD of an IC desired to be modularized does not cause defective bonding even if an inexpensive substrate is used.
It is possible to use the MCM even when there is no match.
【００１０】[0010]
【発明の実施の形態】本発明の請求項１に記載の発明
は、ベアＩＣとＴＡＢとを絶縁性接着剤を介して接着
し、上記ベアＩＣをフェースダウンで封止樹脂を介して
基板にフリップチップ実装し、上記ＴＡＢのアウタリー
ドを上記基板に実装するものであり、基板の大きさを小
型化することができ、安価な基板を用いても接合不良を
起こすことなく、モジュール化したいＩＣのＫＧＤが揃
わない場合にも、ＭＣＭ化することのできる作用を有す
る。BEST MODE FOR CARRYING OUT THE INVENTION According to the first aspect of the present invention, the bare IC and the TAB are adhered to each other via an insulating adhesive, and the bare IC is face down on a substrate via a sealing resin. This is a flip-chip mounting method and the outer leads of the TAB are mounted on the board. The size of the board can be reduced, and even if an inexpensive board is used, a bonding failure does not occur and an IC to be modularized is desired. Even when the KGDs are not complete, it has the effect of converting to MCM.
【００１１】また、請求項２に記載の発明は、請求項１
に記載の発明で、ベアＩＣとＴＡＢをコンパクトパッケ
ージ化したものであり、モジュール基板の面積を小さく
でき、基板の反りを少なくし接合不良を防止できる。The invention described in claim 2 is the same as claim 1.
In the invention described in (1), the bare IC and the TAB are packaged in a compact package, and the area of the module substrate can be reduced, the warp of the substrate can be reduced, and defective bonding can be prevented.
【００１２】また、請求項３に記載の発明は、ベアＩＣ
とＴＡＢとを放熱性の高い干渉材を介して積層し、上記
ベアＩＣをフェースダウンで封止樹脂を介して基板にフ
リップチップ実装し、上記ＴＡＢのアウタリードを上記
基板に実装するものであり、モジュール基板の面積を小
さくでき、基板の反りを少なくし接合不良を防止でき
る。The invention according to claim 3 is the bare IC.
And TAB are laminated via an interfering material having a high heat dissipation property, the bare IC is face-down mounted on a substrate via a sealing resin, and the outer leads of the TAB are mounted on the substrate. It is possible to reduce the area of the module substrate, reduce the warp of the substrate, and prevent defective bonding.
【００１３】また、請求項４に記載の発明は、請求項３
に記載の発明で、ベアＩＣとＴＡＢをコンパクトパッケ
ージ化したものであり、モジュール基板の面積を小さく
でき、基板の反りを少なくし接合不良を防止できる。The invention described in claim 4 is the same as the claim 3.
In the invention described in (1), the bare IC and the TAB are packaged in a compact package, and the area of the module substrate can be reduced, the warp of the substrate can be reduced, and defective bonding can be prevented.
【００１４】以下、本発明の実施の形態について、図１
〜図２とともに説明する。 （実施の形態１）図１および図２は、本発明の実施の形
態におけるベアＩＣとＴＡＢとによる半導体混載実装方
法を示す側断面図および上面図である。図１および図２
において、１はベアＩＣ、２はＴＡＢであり、それぞれ
絶縁性接着剤３を介して接合されている。４はバンプで
あり、このバンプ４により導電性接着剤５を介してベア
ＩＣ１およびモジュール基板６が接続される。７はベア
ＩＣ１をモジュール基板６上に封止する封止樹脂であ
る。８はアウタリードであり、このアウタリード８はＴ
ＡＢ２とモジュール基板６とを接続するものである。Hereinafter, an embodiment of the present invention will be described with reference to FIG.
~ It will be described with reference to FIG. (Embodiment 1) FIGS. 1 and 2 are a side sectional view and a top view showing a semiconductor mixed mounting method using a bare IC and a TAB according to an embodiment of the present invention. 1 and 2
In FIG. 1, reference numeral 1 is a bare IC, and 2 is a TAB, which are bonded to each other via an insulating adhesive 3. Reference numeral 4 is a bump, and the bare IC 1 and the module substrate 6 are connected by the bump 4 via a conductive adhesive 5. Reference numeral 7 is a sealing resin that seals the bare IC 1 on the module substrate 6. 8 is an outer lead, and this outer lead 8 is a T
The AB 2 and the module substrate 6 are connected to each other.
【００１５】次に、上記実施の形態における実装方法に
ついて説明する。まず、ベアＩＣ１とＴＡＢ２とを絶縁
性接着剤３を介して接着固定する。次に、一体化したベ
アＩＣ１をフェースダウンでバンプ４を形成し、導電性
接着剤５で仮接合した後、ベアＩＣ１とモジュール基板
６との間を封止樹脂７にて封止する（これをＦＣ実装と
いう）。その後、ＴＡＢ２とモジュール基板６とをアウ
タリード８にて接合する。Next, the mounting method in the above embodiment will be described. First, the bare IC1 and the TAB2 are bonded and fixed via the insulating adhesive 3. Next, bumps 4 are formed face down on the integrated bare IC 1, and temporary bonding is performed with a conductive adhesive 5, and then the bare IC 1 and the module substrate 6 are sealed with a sealing resin 7 (this). Is called FC implementation). After that, the TAB 2 and the module substrate 6 are joined by the outer leads 8.
【００１６】上記実施の形態によれば、以下に示すよう
な利点を有するものである。 （１）ベアＩＣ１とＴＡＢ２とを積層した構成であるた
めに、実装面積が半減し、モジュール基板６を小さくす
ることができ、モジュール基板６全体の反りが小さくな
り、マザー基板への接合部での短絡や接合不良等を回避
することができる。According to the above embodiment, there are the following advantages. (1) Since the bare IC1 and the TAB2 are laminated, the mounting area is halved, the module substrate 6 can be made small, and the warpage of the module substrate 6 as a whole is reduced, so that the bonding portion to the mother substrate is reduced. It is possible to avoid a short circuit and a defective joint.
【００１７】（２）ベアＩＣをフェースダウンしてバン
プを形成し、ベアＩＣ１とモジュール基板との間を封止
樹脂にて封止（ＦＣ実装）しているため、ベアＩＣをワ
イヤーボンディングにより実装する従来方法に比べて、
ワイヤー部分に封止樹脂を上部から山状に覆う必要がな
く、封止樹脂とモジュール基板との線膨脹係数の差が原
因で生じる基板の反りも少なくなり、これにより、マザ
ー基板への接合部での短絡や接合不良等を確実に回避で
きる。(2) Since the bare IC is faced down to form bumps and the bare IC 1 and the module substrate are sealed with a sealing resin (FC mounting), the bare IC is mounted by wire bonding. Compared with the conventional method
It is not necessary to cover the wire part with the encapsulation resin from the top, and the warpage of the substrate caused by the difference in the coefficient of linear expansion between the encapsulation resin and the module substrate is also reduced. It is possible to reliably avoid a short circuit, a joint failure, etc.
【００１８】（３）モジュール化したいベアＩＣのＫＧ
Ｄが揃わない場合にも、ＴＡＢで置き換えることによ
り、全てのＩＣに対してＫＧＤを使用することなく、Ｍ
ＣＭ化することが可能となる。(3) KG of bare IC to be modularized
Even if D is not available, by replacing with TAB, it is possible to use MGD without using KGD for all ICs.
It becomes possible to commercialize.
【００１９】なお、上記実施の形態では、一方をベアＩ
Ｃで構成した例で説明したが、ベアＩＣに予めバンプを
メッキ等で形成し、コンパクトパッケージ化した構成の
ものを使用した場合にも同様の効果が得られるものであ
る。In the above embodiment, one of the bear I
Although the example of the C configuration has been described, similar effects can be obtained when a bare IC is formed in advance by plating or the like and a compact package is used.
【００２０】また、上記実施の形態では、ベアＩＣ１と
ＴＡＢ２とを絶縁性接着剤３により接合固定した構成で
あるが、絶縁性接着剤３の代わりに、放熱性の高い物
質、あるいはベアＩＣ１とＴＡＢ２とを干渉を防ぐ材料
に置き換えた場合にも、上記実施の形態と同様の効果が
得られるものである。In the above embodiment, the bare IC1 and the TAB2 are bonded and fixed by the insulating adhesive 3. However, instead of the insulating adhesive 3, a substance having a high heat dissipation property or a bare IC1 is used. Even when TAB2 is replaced with a material that prevents interference, the same effect as in the above-described embodiment can be obtained.
【００２１】[0021]
【発明の効果】以上のように本発明は、ベアＩＣとＴＡ
Ｂとを絶縁性接着剤を介して接着し、上記ベアＩＣをフ
ェースダウンで封止樹脂を介して基板にフリップチップ
実装し、上記ＴＡＢのアウタリードを上記基板に実装し
たものであり、以下のような効果を有するものである。As described above, according to the present invention, the bare IC and TA
B is bonded to the substrate via an insulating adhesive, the bare IC is mounted face down on the substrate via a sealing resin, and the outer leads of the TAB are mounted on the substrate. It has various effects.
【００２２】ベアＩＣとＴＡＢとを積層した構成である
ため、従来のように横並べに実装した場合に比べて実装
面積が半減しモジュール基板を小さくすることができ、
高密度実装が可能となると共に、モジュール基板の反り
が小さくなり、接合不良を回避することができる。Since the bare IC and the TAB are laminated, the mounting area can be halved and the module substrate can be made smaller as compared with the case where the bare IC and the TAB are mounted side by side.
High-density mounting is possible, warpage of the module substrate is reduced, and defective joints can be avoided.
【００２３】また、ベアＩＣをフェースダウンしてバン
プを形成し、ベアＩＣとモジュール基板との間を封止樹
脂にて封止（ＦＣ実装）しているため、ベアＩＣをワイ
ヤーボンディングにより実装する従来方法に比べて、ワ
イヤー部分に封止樹脂を上部から山状に覆う必要がな
く、封止樹脂とモジュール基板との線膨脹係数の差が原
因で生じる基板の反りも少なくなり、マザー基板への接
合部での短絡や接合不良等を確実に回避できる。Since the bare IC is faced down to form bumps and the bare IC and the module substrate are sealed (FC mounted) with a sealing resin, the bare IC is mounted by wire bonding. Compared to the conventional method, it is not necessary to cover the wire portion with the encapsulation resin from the top, and the warpage of the substrate caused by the difference in the linear expansion coefficient between the encapsulation resin and the module substrate is reduced, and It is possible to surely avoid a short circuit, a defective joint, or the like at the joint portion.
【００２４】さらに、モジュール化したいベアＩＣのＫ
ＧＤが揃わない場合にも、ＴＡＢで置き換えることによ
り、ＭＣＭ化することが可能となる。Furthermore, the bare IC K to be modularized
Even when the GDs are not complete, the MCM can be realized by replacing with the TAB.
【図１】本発明の実施の形態における半導体混載実装方
法を示す側断面図FIG. 1 is a side sectional view showing a semiconductor mixed mounting method according to an embodiment of the present invention.
【図２】同実施の形態の半導体混載実装方法を示す上面
図FIG. 2 is a top view showing a semiconductor mixed mounting method of the same embodiment.
【図３】従来の半導体混載実装方法を示す上面図FIG. 3 is a top view showing a conventional semiconductor mixed mounting method.
【図４】従来の半導体混載実装方法を示す側断面図FIG. 4 is a side sectional view showing a conventional semiconductor mixed mounting method.
１ ベアＩＣ ２ ＴＡＢ ３ 絶縁性接着剤 ４ バンプ ５ 導電性接着剤 ６ モジュール基板 ７ 封止樹脂 ８ アウタリード 1 Bare IC 2 TAB 3 Insulating Adhesive 4 Bump 5 Conductive Adhesive 6 Module Substrate 7 Sealing Resin 8 Outer Lead
Claims (4)
して接着し、上記ベアＩＣをフェースダウンで封止樹脂
を介して基板にフリップチップ実装し、上記ＴＡＢのア
ウタリードを上記基板に実装する半導体混載実装方法。1. A bare IC and a TAB are bonded together via an insulating adhesive, the bare IC is flip-chip mounted on a substrate face down with a sealing resin, and outer leads of the TAB are mounted on the substrate. Semiconductor mixed mounting method.
イージ化したことを特徴とする請求項１記載の半導体混
載実装方法。2. The semiconductor integrated mounting method according to claim 1, wherein the bare IC and the TAB are made into a compact package.
材を介して積層し、上記ベアＩＣをフェースダウンで封
止樹脂を介して基板にフリップチップ実装し、上記ＴＡ
Ｂのアウタリードを上記基板に実装する半導体混載実装
方法。3. A bare IC and a TAB are laminated via an interference material having a high heat dissipation property, and the bare IC is flip-chip mounted on a substrate face down with a sealing resin interposed therebetween.
A semiconductor mixed mounting method in which the outer lead of B is mounted on the substrate.
イージ化したことを特徴とする請求項３記載の半導体混
載実装方法。4. The semiconductor mixed mounting method according to claim 3, wherein the bare IC and the TAB are made into a compact package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8092357A JPH09283696A (en) | 1996-04-15 | 1996-04-15 | Semiconductor hybrid mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8092357A JPH09283696A (en) | 1996-04-15 | 1996-04-15 | Semiconductor hybrid mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09283696A true JPH09283696A (en) | 1997-10-31 |
Family
ID=14052159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8092357A Pending JPH09283696A (en) | 1996-04-15 | 1996-04-15 | Semiconductor hybrid mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09283696A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100281115B1 (en) * | 1998-05-12 | 2001-02-01 | 김영환 | Multichip module |
| WO2001037332A1 (en) * | 1999-11-16 | 2001-05-25 | Indian Space Research Organisation | A high density hybrid integrated circuit package having a flip-con structure |
| KR20020016278A (en) * | 2000-08-25 | 2002-03-04 | 듀흐 마리 에스. | Improved Method of Mounting Chips in Flip Chip Technology Process |
-
1996
- 1996-04-15 JP JP8092357A patent/JPH09283696A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100281115B1 (en) * | 1998-05-12 | 2001-02-01 | 김영환 | Multichip module |
| WO2001037332A1 (en) * | 1999-11-16 | 2001-05-25 | Indian Space Research Organisation | A high density hybrid integrated circuit package having a flip-con structure |
| KR20020016278A (en) * | 2000-08-25 | 2002-03-04 | 듀흐 마리 에스. | Improved Method of Mounting Chips in Flip Chip Technology Process |
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