451443 6319twf-doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（广） 本發明是有關於一種具有摻雜材質的凸塊結構，且特 別是有關於一種應用於半導體覆晶型態封裝且具有摻雜材 質之凸塊結構。 一般而言，積體電路(Integrated Circuit，1C)的生產，主 要分爲三個階段：矽晶片的製造、積體電路的製作及積體 電路的封裝(Package)。積體電路封裝，可說是完成積體電 路成品的最後步驟。積體電路之封裝，其目的在於提供晶 片（Die)與印刷電路板(Printed Circuit Board，PCB)或其他適 當元件之間電性連接的媒介、以及保護晶片，爲製作積體 電路成品的最後步驟。 現今電子產品之開發莫不朝向輕、薄、短、小的目標 發展，對於半導體來說即是提高其積集度(Integration)，至 於封裝技術方面，則有晶片尺寸封裝(Chip Scale Package， CSP)、覆晶構裝（Flip Chip，FC)等高密度之封裝技術的提 出。其中覆晶構裝以應用於高接腳數晶片的封裝上，如微 處理器，其優點包括：可採用面積陣列(Area Array)配置， 因此接腳數的密度較高、自動對準（Sdf-align)生成的錫球 及較短的信號傳遞路徑等。 請參照第1A圖與第1B圖，其所繪示爲習知覆晶產品 組裝結構的剖面示意圖。 如第1A圖所示，在覆晶構裝(Flip Chip，FC)技術中， 於基底102上形成銲墊l〇4(Pad)，以作爲對外之接點。晶 片106至少包括一主動表面101，並於晶片1〇6之主動表. 面101上，配置數個凸塊l〇8(Bump)。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公a ) (請先閲讀背面之注意事項再填寫本頁) ρ sj· i線. 經濟部智慧財產局員工消费合作社印製 45 1 44 3 €319twf.doc/006 A7 B7 五、發明說明（2) 如第1B圖所示，將晶片106之主動表面101上的凸 塊108，向基板102的銲墊104對正接合。在此一組裝步 驟中，常因晶片110上凸塊108的共同平面度不佳，或基 板102上銲墊104的共平面度不佳，導致部分凸塊108與 銲墊104之間具有空隙110。即使在進行迴銲(Reflow)後， 仍然無法改善凸塊108與銲墊104之接合。故此種平面度 不良會使得覆晶產品組裝不易，造成產品良率損失（Yield Loss)。 目前改善的作法是在基板之銲墊上預先加上與凸塊相 同材質的銲錫(Presolder)，以解決無法銲接的問題，但此 種作法不但增加了製程的繁複性，而且使得生產成本(Cost) 變高。 因此，本發明之一目的即在提供一種可改善平面度之 具有摻雜材質的凸塊結構。 本發明之另一目的在提供一種應用在覆晶產品構 裝，且可改善產品平面度之具有摻雜材質的凸塊結構。 本發明之再一目的在提供一種應用在覆晶產品構 裝，僅摻雜不同材質至凸塊，即可改善產品平面度之凸塊 結構。 根據本發明之上述之目的，提出一種具有摻雜材質 的凸塊結構，至少包括：一基板、數個靜塾、—晶片、以 及數個凸塊。其中基板至少具有一第一表面。數個銲墊配 置於基板之第一表面上。晶片至少具有一主動表面。凸塊 至少包括一底材與複數個摻雜物，且配置於晶片之主動表 4 本紙張尺度適用中國國家標準（cns)a4規格m〇 x 297公釐） (請先閲讀背面之注意事項再填窝本頁) * Q--------訂—-----線--Ο----------------------- 經濟部智慧財產局員工消費合作社印製 451443 6319twf-doc/006 五、發明說明（>) 面上。晶片以主動表面面對基板之第一表面配置，使得每 一凸塊分別對應銲墊之一，並使凸塊之摻雜物與基板之銲 墊接觸。 依照本發明之較佳實施例，本發明具有摻雜材質的 凸塊結構，僅將摻雜物加入銲料中，並藉由控制摻雜物的 粒徑大小’可順利消除晶片上凸塊與基板上的靜墊之間 隙，即可改善覆晶構裝產品之平面度。僅將摻雜物加入銲 料中，並不改善原組裝流程，具良好之作業性。可以低成 本的方式改善覆晶構裝產品之平面度，達到提高組裝良率 的效果，具良好之產品品質。可強化凸塊與銲墊接合之接 點強度，不但改善覆晶構裝產品之平面度，且具良好之信 賴性。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖與第1B圖係繪示習知覆晶產品組裝結構的剖 面示意圖。 第2A圖與第2B圖係繪示根據本發明具有摻雜材質的 凸塊結構較佳實施例的剖面示意圖。 圖式之標記說明： 102、202 :基底 101、201 :主動表面 203 :第一表面 5 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） ------------^!·ο--- (請先閱讀背面之注意事項再填寫本頁) 訂 ;線· 451443 6319twf. doc/006 A7 B7 五、發明說明（+) 104 、 204 : 銲墊 108 、 208 : 凸塊 106 、 206 : 晶片 110 :空隙 經濟部智慧財產局員工消費合作社印製 212 :底材 214 :摻雜物 實施例 請參照第2A圖與第2B圖，其所繪示根據本發明具 有摻雜材質的凸塊結構較佳實施例的剖面示意圖。 如第2A圖所示，晶片206至少具有一主動表面201 ° 凸塊208至少包括一底材212與摻雜物214，且配置於晶 片206之主動表面201上，其中凸塊208之底材212的材 質比如是共晶之錫鉛合金、金、或導電聚合物，凸塊 之摻雜物214比如是銀鈀合金、高鉛、銅、或鎳。凸塊208 之底材212的熔點較凸塊208之摻雜物214的熔點低，且 凸塊208之底材212的比重較凸塊208之摻雜物214的比 重小，底材212與摻雜物214經溶拌可作爲形成凸塊208 之靜料(Solder)。 如第2B圖所示，基板202至少具有一第一表面203。 數個銲墊204配置於基板202之第一表面203上，以作爲 基板202對外之接點，銲墊204之材質比如是銅或鋁。晶 片206以主動表面201面對基板202之第一表面203配置， 使得每一凸塊208分別對應銲墊204之一。進行迴銲(Reflow). 步驟時，凸塊208中熔點較低的底材212於低溫時先行熔 6 (諳先閲讀背面之注意事項再填寫本頁) -0-------- 訂---------線！ 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 451443 6319twf-doc/006 五、發明說明（Γ) (請先間讀背面之注§項再填寫本頁) 化，凸塊208中之摻雜物214因比重大且熔點較底材212 高，故會將形成凸塊208的銲料往下帶’使凸塊208之摻 雜物214往下降至基板之銲墊204上’可改善凸塊108 與銲墊1〇4之接合黏著(Wetting)。藉由控制摻雜物214的 粒徑大小，使凸塊208之摻雜物214與基板202之銲墊204 接觸，可順利消除晶片206上凸塊208與基板202上的銲 墊204之間隙，即可改善覆晶構裝產品之平面度，達到提 高組裝良率的效果.，具良好之產品品質。此外，將摻雜物 214之底材212加入凸塊208所形成之銲料’具有強化凸 塊208與銲墊204接合之接點強度，且不改善原組裝流程， 具良好之作業性。 綜上所述，本發明至少具有下列優點： 1. 本發明具有摻雜材質的凸塊結構，僅將摻雜物加入 銲料中，並藉由控制摻雜物的粒徑大小，可順利消除晶片 上凸塊與基板上的銲墊之間隙，即可改善覆晶構裝產品之 平面度。 經濟部智慧財產局員工消費合作社印製 2. 本發明具有摻雜材質的凸塊結構，僅將摻雜物加入 銲料中，並不改善原組裝流程，即可改善覆晶構裝產品之 平面度’具良好之作業性。 3. 本發明具有摻雜材質的凸塊結構，僅將摻雜物加入 銲料中，可以低成本的方式改善覆晶構裝產品之平面度， 達到提高組裝良率的效果，具良好之產品品質。 4. 本發明具有摻雜材質的凸塊結構，僅將摻雜物加入. _料中’可強化凸塊與銲墊接合之接點強度，不但改善覆 7 本紙張尺度適用中關家標準（CNS)A4規格⑵G x 297公髮） 15 1 44 3 63l9twf.d〇c/006 B7 五、發明說明（έ) 晶構裝產品之平面度，且具良好之信賴性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (諳先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格<210 X 297公釐）451443 6319twf-doc / 006 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (Wide) The present invention relates to a bump structure with a doped material, and more particularly to a bump structure applied to semiconductor devices. The crystalline package has a bump structure with doped material. Generally speaking, the production of integrated circuits (1C) is mainly divided into three stages: the manufacture of silicon wafers, the manufacture of integrated circuits, and the packaging of integrated circuits. Integrated circuit packaging can be said to be the last step to complete the finished integrated circuit. The package of integrated circuits is designed to provide a medium for the electrical connection between a die and a printed circuit board (PCB) or other appropriate components, and to protect the chip. It is the final step in making a finished integrated circuit. . At present, the development of electronic products must be developed toward light, thin, short, and small goals. For semiconductors, it is to increase their integration. As for packaging technology, there is Chip Scale Package (CSP). And flip chip packaging (Flip Chip, FC) and other high-density packaging technologies. The flip chip structure is applied to packages with high pin count chips, such as microprocessors, and its advantages include: Area Array configuration can be used, so the pin number density is higher and automatic alignment (Sdf -align) generated solder balls and shorter signal transmission paths. Please refer to FIG. 1A and FIG. 1B, which are schematic cross-sectional views showing the assembly structure of a conventional flip chip product. As shown in FIG. 1A, in a flip chip (FC) technology, a pad 104 (Pad) is formed on the substrate 102 as an external contact. The wafer 106 includes at least an active surface 101, and a plurality of bumps 108 (Bump) are arranged on the active surface 101 of the wafer 106. 3 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 malea) (Please read the notes on the back before filling this page) ρ sj · i line. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 45 1 44 3 € 319twf.doc / 006 A7 B7 V. Description of the invention (2) As shown in FIG. 1B, the bumps 108 on the active surface 101 of the wafer 106 are aligned to the pads 104 of the substrate 102. In this assembly step, the common flatness of the bumps 108 on the wafer 110 or the poor coplanarity of the pads 104 on the substrate 102 often results in a gap 110 between some of the bumps 108 and the pads 104. . Even after the reflow, the joint between the bump 108 and the pad 104 cannot be improved. Therefore, this kind of poor flatness will make the assembly of flip-chip products difficult, resulting in product yield loss (Yield Loss). At present, the improved method is to add solder (Presolder) of the same material as the bumps on the substrate pads in advance to solve the problem of inability to solder. However, this method not only increases the complexity of the manufacturing process, but also causes the cost of production (Cost). Becomes high. Therefore, an object of the present invention is to provide a bump structure with a doped material which can improve the flatness. Another object of the present invention is to provide a bump structure with doped material which can be used in flip chip product structure and can improve the flatness of the product. Yet another object of the present invention is to provide a bump structure that can be used in flip-chip product structures, and can only improve the flatness of the product by doping different materials to the bumps. According to the above object of the present invention, a bump structure with a doped material is proposed, which includes at least: a substrate, a plurality of wafers, a wafer, and a plurality of bumps. The substrate has at least a first surface. A plurality of pads are disposed on the first surface of the substrate. The wafer has at least one active surface. The bumps include at least a substrate and a plurality of dopants, and are arranged on the active sheet of the wafer. The paper size is applicable to the Chinese national standard (cns) a4 specification m 0x 297 mm. (Filling page) * Q -------- Order ------- line --〇 ----------------------- Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 451443 6319twf-doc / 006 5. The invention description (>). The wafer is arranged with the first surface of the active surface facing the substrate, so that each bump corresponds to one of the bonding pads respectively, and the dopants of the bumps contact the bonding pads of the substrate. According to a preferred embodiment of the present invention, the present invention has a bump structure of doped material. Only the dopant is added to the solder, and by controlling the particle size of the dopant, the bumps and the substrate on the wafer can be smoothly eliminated. The gap between the static pads on the surface can improve the flatness of the flip-chip structured product. Adding dopants to the solder does not improve the original assembly process and has good workability. The flatness of flip-chip packaged products can be improved in a low cost manner to achieve the effect of increasing the yield of assembly and have good product quality. It can strengthen the strength of the joints between the bumps and the solder pads, not only improve the flatness of the flip-chip structured products, but also have good reliability. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A and FIG. FIG. 1B is a schematic cross-sectional view showing a conventional flip-chip product assembly structure. Figures 2A and 2B are schematic cross-sectional views illustrating a preferred embodiment of a bump structure having a doped material according to the present invention. Explanation of drawing symbols: 102, 202: substrate 101, 201: active surface 203: first surface 5 The paper size is applicable to Chinese national standard < CNS) A4 specification (210 X 297 mm) ------- ----- ^! · Ο --- (Please read the notes on the back before filling in this page) Order; line · 451443 6319twf. Doc / 006 A7 B7 V. Description of the invention (+) 104, 204: Solder pad 108, 208: bumps 106, 206: wafer 110: printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Gap Economy 212: substrate 214: dopant For examples, please refer to Figures 2A and 2B. A schematic cross-sectional view of a preferred embodiment of a bump structure with a doped material according to the present invention. As shown in FIG. 2A, the wafer 206 has at least an active surface 201 °. The bump 208 includes at least a substrate 212 and a dopant 214, and is disposed on the active surface 201 of the wafer 206. The substrate 212 of the bump 208 The material used is eutectic tin-lead alloy, gold, or conductive polymer, and the bump dopant 214 is, for example, silver-palladium alloy, high lead, copper, or nickel. The melting point of the substrate 212 of the bump 208 is lower than the melting point of the dopant 214 of the bump 208, and the specific gravity of the substrate 212 of the bump 208 is smaller than that of the dopant 214 of the bump 208. The impurities 214 can be used as a solder to form the bumps 208 after being mixed. As shown in FIG. 2B, the substrate 202 has at least a first surface 203. A plurality of solder pads 204 are disposed on the first surface 203 of the substrate 202 to serve as external contacts of the substrate 202. The material of the solder pads 204 is, for example, copper or aluminum. The wafer 206 is configured with the active surface 201 facing the first surface 203 of the substrate 202 so that each bump 208 corresponds to one of the bonding pads 204, respectively. Reflow. In the step, the substrate 212 with the lower melting point in the bump 208 is melted at low temperature 6 (谙 Please read the precautions on the back before filling this page) -0 -------- Order --------- line! This paper size applies the Chinese national standard (CNS > A4 specification (210 X 297 mm) 451443 6319twf-doc / 006 V. Description of the invention (Γ) (please read the note § on the back before filling this page)) The dopant 214 in the block 208 has a high specific gravity and a higher melting point than the substrate 212, so the solder forming the bump 208 is brought down to 'drop the dopant 214 of the bump 208 onto the pad 204 of the substrate. 'Wetting can improve the bonding adhesion between the bump 108 and the pad 104. By controlling the particle size of the dopant 214, the dopant 214 of the bump 208 and the pad 204 of the substrate 202 can be brought into contact with each other. By smoothly eliminating the gap between the bumps 208 on the wafer 206 and the pads 204 on the substrate 202, the flatness of the flip-chip structured product can be improved, and the effect of improving the assembly yield can be achieved. It has good product quality. In addition, The solder formed by adding the bumps 208 to the substrate 212 of the sundries 214 has the strength of strengthening the joints between the bumps 208 and the pads 204, and does not improve the original assembly process, and has good workability. In summary, this The invention has at least the following advantages: 1. The invention has a bump structure of doped material, and only Debris is added to the solder, and by controlling the particle size of the dopant, the gap between the bumps on the wafer and the pads on the substrate can be smoothly eliminated, and the flatness of the flip-chip package can be improved. Printed by the Bureau ’s Consumer Cooperatives 2. The invention has a bump structure with doped material. Only adding dopants to the solder does not improve the original assembly process, and can improve the flatness of the flip-chip structured product. Workability 3. The invention has a bump structure of doped material, and only adding dopants to the solder can improve the flatness of the flip-chip structured product at a low cost, and achieve the effect of improving the assembly yield, with good Product quality. 4. The present invention has a bump structure of doped material, only the dopant is added. _In the material can strengthen the strength of the joint between the bump and the pad, not only improve the coverage of this paper. Guan Jia Standard (CNS) A4 size (G x 297) 15 1 44 3 63l9twf.doc / 006 B7 V. Description of the invention (Straight) The flatness of the crystal structure product, and it has good reliability. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (谙 Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
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