TW439237B - Flip chip structure and its manufacturing method - Google Patents

Flip chip structure and its manufacturing method Download PDF

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Publication number
TW439237B
TW439237B TW088105830A TW88105830A TW439237B TW 439237 B TW439237 B TW 439237B TW 088105830 A TW088105830 A TW 088105830A TW 88105830 A TW88105830 A TW 88105830A TW 439237 B TW439237 B TW 439237B
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Taiwan
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scope
patent application
item
semiconductor package
flip
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TW088105830A
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Chinese (zh)
Inventor
Wen-Jiun Liou
Yi-Hua Jang
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Walsin Advanced Electronics
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Priority to TW088105830A priority Critical patent/TW439237B/en
Priority to JP11189428A priority patent/JP2000299344A/en
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Publication of TW439237B publication Critical patent/TW439237B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

A flip chip structure has a chip formed thereon a plurality of bonding pads, each being adhered with a copper ball, wherein the copper ball is pre-electroplated and adhered to the bonding pad by conductive material.

Description

K?4 3 B7 五、發明説明（/) 本發明是有關於一種積體電路構裝，且特別是有關於 一種覆晶結構(Flip Chip)及其製造方法。 第1A至1C圖係繪示習知覆晶結構之凸塊（Bump)製 程的剖面示意圖。 請參照第1A圖，在銘接合墊（Bonding Pad)10上依序 形成保護層、鈦金屬層14及銅金屬層16，然後在銅金 屬層1 6上形成已定義的光阻層18 請參照第1B圖，在光阻層18所暴露出的銅金屬層16 表面上’電鍍（E丨ectroplating)形成銅金屬層20。然後，同 樣利用電鍍的方法，在銅金屬層20及部份的光阻18表面 上形成鉛錫合金層（SnPb)22。 請梦照第1 C圖，移除光阻層18，接著進行熱流步驟 (Reflow)，使鉛錫合金層22形成凸塊24。然後，蝕刻去 除部份的銅金屬層16及鈦金屬層14，以形成銅金屬層16a 及鈦金屬層14a。 上述製程需要進行多次的微影及飩刻製程，步驟繁 複，且製程中必需進行電鍍，而電鑛製程可能影響到晶片 的電路性質。 而另一習知的覆晶製程爲使用網版印刷（Screen Printing)、點膠（Dispensing)或是沾針轉移（Pin Transfer)等 方式，將導電膠（Conductive Ep0Xy)直接置放於鋁接合墊26 上，當作凸塊28來使用，如第2圖所示。 由於導電膠無法使用焊料（Solder)進行粘著，因此使 用此種覆晶結構，往後的組裝（Assembly)製程及相關的承 3 本紙張尺度適用中麵家^CNS ) A4規格（2IGX297公 (請先閲讀背面之注意事項再填寫本頁) -裝-K? 4 3 B7 V. Description of the invention (/) The present invention relates to an integrated circuit structure, and more particularly to a flip chip structure and a manufacturing method thereof. Figures 1A to 1C are schematic cross-sectional views showing a conventional bump process for a flip-chip structure. Referring to FIG. 1A, a protective layer, a titanium metal layer 14, and a copper metal layer 16 are sequentially formed on a bonding pad 10, and then a defined photoresist layer 18 is formed on the copper metal layer 16. Please refer to FIG. In FIG. 1B, the copper metal layer 20 is formed by electroplating on the surface of the copper metal layer 16 exposed by the photoresist layer 18. Then, a lead-tin alloy layer (SnPb) 22 is formed on the surface of the copper metal layer 20 and a portion of the photoresist 18 by the same method of electroplating. Please dream according to FIG. 1C, remove the photoresist layer 18, and then perform a heat flow step (Reflow), so that the lead-tin alloy layer 22 forms a bump 24. Then, a portion of the copper metal layer 16 and the titanium metal layer 14 are removed by etching to form a copper metal layer 16a and a titanium metal layer 14a. The above process requires multiple lithography and engraving processes, the steps are complicated, and electroplating must be performed in the process, and the electric mining process may affect the circuit properties of the wafer. Another conventional flip-chip manufacturing process uses screen printing, dispensing, or pin transfer to place conductive epoxy (0xy) directly on aluminum bonding pads. It is used as a bump 28 as shown in FIG. 2. Since the conductive adhesive cannot be adhered with Solder, using this flip-chip structure, the subsequent assembly process and related bearings 3 paper size is applicable to mid-range home ^ CNS) A4 size (2IGX297 male ( (Please read the notes on the back before filling out this page)-装-

,1T 經濟部智慧財產局員工消費合作社印製 E,1T Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs,

4334<wI :/0()2 A7 B7 經濟部智装財產局員工消費合作社印製 五、發明説明（》） 載器（Carrier)或印刷電路板（Printed Circuit Board) ’在接點 (Contact)上皆需重新設計’以導電膠替換常用之錫膏’造 成製造成本的增加。另一方面’導電膠的導電性比金屬差' 所以上述的覆晶結構導電性’比使用金屬形成凸塊的覆晶 結構差。在未來高頻、高傳輸速度及低能量損耗之應用趨 勢下，將導致元件間訊號傳遞的阻抗變高，甚至造成訊號 延遲（Delay)或訊號衰減（Decay)。 因此本發明的目的之一是在於提供一種覆晶結構’其 製造過程不需進行繁複的微影蝕刻製程及電鍍製程’而且 可與原先的封裝製程及承載器相容。 本發明的另一目的在於提出一種覆晶結構，其具有較 好之導電特性，可因應未來高效能電子產品之需求。 本發明提出一種覆晶結構，此覆晶結構具有一晶片， 在晶片上具有複數個接合墊，且使用導電材質分別在每一 接合墊上粘著一個銅球，其中銅球事先經過電鍍處理。 本發明中，使用銅球與導電材質形成凸塊，可以大量 生產提高產量，另一方面，可與原先的封裝製程及承載器 相容，不需重新設計。在製程中，不需微影蝕刻製程及電 鎞製程，可以提高可靠性。此外，藉由銅球較佳之導電性， 可以改善訊號傳遞路徑之品質，而適當選擇銅球鍍層，可 以改善凸塊與後續電路板或承載器之接合效果，提高產品 之可靠度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 4 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公董） ^^1* ^^^1 tjn ^^^1 ^^^1 ,^—^i . ^^^1 ^^^1 ^^^1 ^^^1· 111 k^in ^^ V - (請先閲讀背面之注^^項再填寫本頁) 43 3 4t\\ f doc/002 A7 43 3 4t\\ f doc/002 A7 經濟部智慧財產局員工消費合作社印製 87 五、發明説明（？） 說明如下： 圖式之簡單說明： 第1A至1C圖係繪示習知製造覆晶結構製程的剖面 示意圖； 第2圖係繪示習知另一種覆晶結構的示意圖； 第3A至3C圖係繪示根據本發明一較佳實施例之覆 晶結構製程的剖面示意圖； 第4圖係繪示根據本發明覆晶結構的半導體封裝剖面 示意圖；以及 第5圖係繪示根據本發明覆晶結構的另一種半導體封 裝剖面示意圖。 圖式之標記說明： 10, 26, 32 :接合墊 12, 34 :保護層 14 :鈦金屬層 16, 20 :銅金屬層 18 :光阻 22:鉛錫合金層 24, 28 :凸塊 36 :導電膠 30 :晶片 38 :銅球 39 :鍍層 40 :承載器 '裝 訂^ (諳先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 43 3 4tw f,dac/〇〇2 A/ B7 五、發明説明（士） 41 :線路接點 42 :焊料 (請先閱讀背面之注意事項再填寫本頁) 44 :塡充膠 46 :封裝樹脂 48 :散熱片 實施例 第3A至3C圖係繪示根據本發明一較佳實施例之覆 晶結構製程的剖面示意圖。在這些圖中，僅繪出部份接合 墊之製造情形。 經濟部智慧財產局®工消費合作社印敕 請參照第3A圖，在晶片30上具有接合墊32，在晶 片30上形成保護層34，暴露出接合墊32。接著，在接合 墊32上形成導電材質層36。其中，晶片30包括一般之半 導體晶片，其上具有許多半導體元件及線路。接合墊32 的材質比如是鋁，連接晶片30上之線路與元件；而導電 材質層36的材質包括是導電膠，異方性導電膠（Anisotropic Conductive Paste, ACP)、異方性導電膜（Anisotropic Conductive Fiim，ACF)或銀膠（Ag paste) ’形成導電材質層 36的方式包括網版印刷、點膠、沾針轉移或者沖模粘黏 (punch,針對ACF而言）的方式。 請參照第3B圖，在導電材質層36上放置銅球38， 銅球38與導電材質層36係作爲凸塊之用，其中銅球38 可以事先經過電鍍處理，形成一鍍層39以增加後續之接 合性（Solderability)、抗氧化性及抗腐触性，鍍層39之材 質包括是金（Au)、銀(Ag)、錫（Sn)、鈀(Pd)和鎳(Ni)等。 6 本紙張尺度適用中國國家標率（CNS ) A4規格（210 X 297公釐} 陷4392 3 7 r.d nc/o U2 A7 B7 五、發明説明（s) 由上述製程可知，本發明製造凸塊時不需進行微影蝕 刻等製程，即可形成凸塊，製程較爲簡單。而且銅球之電 鑛部分是分開獨立進行，在整個製程中晶片無須進行電鍍 製程，晶片的電路特性不會被影響。另一方面，導電材質 與銅球的放置可以大量進行，因此產量可以提高。 請參照第3C圖，在承載器4〇之線路接點41上放置 焊料42，之後在承載器40上粘著晶片30，粘著方式爲將 銅球38與焊料42接合。隨後進行塡充（Underfill)步驟， 在晶片30與承載器40間塡入塡充膠44，以提高組裝的可 靠性。而承載器40包括球腳格狀陣列基板（BGA substrate)、島狀陣列基板（LGA substrate)或者印刷電路板 (PCB)等。且承載器4〇的材質包括BT樹脂、FR4樹脂、 陶瓷材料或是聚亞醯胺（polyimide)等。 第4圖係繪示根據本發明覆晶結構的半導體封裝剖面 示意圖’第5圖係繪示根據本發明覆晶結構的另一種半導 體封裝剖面示意圖。 經濟部智慧財產局工消費合作社印製 81! U ί In i u --- - - -- ---- n n I U3-6 (請先閲讀背面之注意事項再填寫本頁) 請參照第4圖及第5圖，進行塡充步驟後，可以進一 步使用封裝樹脂46覆蓋晶片30，形成封裝結構，接著可 在封裝樹脂46上粘著散熱片（Heat Slug)48,如第4圖所示， 以增加整個封裝結構的散熱性。其中封裝樹脂46的材質 包括環氧樹脂(Epoxy)。 然而’使用封裝樹脂46封裝時，可以暴露出晶片30 的背面’然後將散熱片48直接粘著於晶片30暴露的背面 上’如第5圖所示，如此晶片30產生的熱可以直接由散 7 &張尺度適用中國國{ CNS ) A4規格（210X297公釐)~~' ，4 j - - :. 433 4ΐ\' I. iUu."i()2 A7 B7 五、發明説明（灰） 熱片48帶走，進一步增加散熱效率。 (請先閱讀背面之注意事項再填寫本頁) 在本發明中，由於凸塊是由銅球所形成，其可與承載 器上的焊料直接粘著，再加上其上之鍍層更可以改善與焊 料之接合性。此外，上述實施例中，銅球係放置於晶片之 接合墊上，再與承載器或電路板接合。然而熟習該技術者 應知，亦可以將銅球先植於承載器或電路板上，然後將接 合墊上具有導電材質層之晶片與銅球接合，其效果與結構 和上述實施例是相同的。 因此，本發明之覆晶結構可與習知封裝製程相容，並 不需更改製程及承載器的設計。銅球經過電鍍處理，可以 增加接合性、抗氧化性及抗腐蝕性。 綜上所述，本發明之覆晶結構至少具有下列優點： 1. 本發明中，凸塊是由銅球及導電材質組成，不必進 行繁複的微影蝕刻及電鍍的製程，即可形成，製程較爲簡 單。而且因爲導電膠及銅球的放置可以大量地進行，產量 可以提商。 經濟部智慧財產局員工消費合作社印製 2. 本發明使用銅球作爲凸塊，其可以直接與焊料進行 接合，不需更改製程及承載器的設計，可相容於現行封裝 製程。 3. 對於現今半導體產品，高速度、低損耗之需求，已 逐漸採用銅作爲內連線材質°然而，本發明之覆晶結構亦 採用銅球作爲接合媒介，具有更佳之導電特性，可減低阻 抗、避免訊號延遲及訊號衰減，符合未來產品需求。 雖然本發明已以較佳實施例揭露如上，然其並非用以 8 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2!0X297公釐） 43.Ulu r.iloc/002 A7 B7 五、發明説明（q) 限定本發明，任何熟習此技藝者，'在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 -I— I-- - I—I 0¾-a (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印紫 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐）4334 < wI: / 0 () 2 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs. 5. Description of the invention (") Carrier or Printed Circuit Board" Contact " All of them need to be redesigned to replace the commonly used solder paste with conductive glue, which causes an increase in manufacturing costs. On the other hand, 'the conductive paste has lower conductivity than metal', so the above-mentioned flip-chip structure has lower conductivity than the flip-chip structure in which bumps are formed using metal. In the future application trend of high frequency, high transmission speed and low energy loss, it will cause the impedance of signal transmission between components to become higher, and even cause signal delay (Decay) or signal attenuation (Decay). Therefore, one of the objectives of the present invention is to provide a flip-chip structure 'whose manufacturing process does not require a complicated lithographic etching process and an electroplating process' and is compatible with the original packaging process and the carrier. Another object of the present invention is to provide a flip-chip structure, which has better conductive characteristics and can meet the needs of high-performance electronic products in the future. The present invention provides a flip-chip structure. The flip-chip structure has a wafer, a plurality of bonding pads on the wafer, and a copper ball is adhered to each of the bonding pads using a conductive material, wherein the copper balls are electroplated in advance. In the present invention, copper balls and conductive materials are used to form bumps, which can be mass-produced to increase yield. On the other hand, it is compatible with the original packaging process and the carrier, and does not need to be redesigned. In the manufacturing process, the lithographic etching process and the electro-chemical process are not needed, which can improve the reliability. In addition, the better conductivity of the copper balls can improve the quality of the signal transmission path, and the proper choice of copper ball plating can improve the bonding effect between the bumps and subsequent circuit boards or carriers, and improve the reliability of the product. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail, in conjunction with the accompanying drawings, to make details. 4 This paper size applies the Chinese National Standard (CNS) A4 specification. (2 丨 0X297 public director) ^^ 1 * ^^^ 1 tjn ^^^ 1 ^^^ 1, ^-^ i. ^^^ 1 ^^^ 1 ^^^ 1 ^^^ 1 · 111 k ^ in ^^ V-(Please read the note ^^ on the back before filling out this page) 43 3 4t \\ f doc / 002 A7 43 3 4t \\ f doc / 002 A7 Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 87 V. Description of the invention (?) The description is as follows: Brief description of the drawings: Figures 1A to 1C are cross-sectional schematic diagrams showing a conventional process for manufacturing a flip-chip structure; Figure 2 is a diagram showing another conventional flip-chip structure. 3A to 3C are schematic cross-sectional views of a flip-chip structure manufacturing process according to a preferred embodiment of the present invention; FIG. 4 is a schematic cross-sectional view of a semiconductor package according to the flip-chip structure of the present invention; A schematic cross-sectional view of another semiconductor package with a flip-chip structure according to the present invention is shown. Description of drawing symbols: 10, 26, 32: bonding pads 12, 34: protective layer 14: titanium metal layer 16, 20: copper metal layer 18: photoresist 22: lead-tin alloy layer 24, 28: bump 36: Conductive adhesive 30: Wafer 38: Copper ball 39: Coating 40: Carrier's binding ^ (^ Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 43 3 4tw f, dac / 〇〇2 A / B7 V. Description of the Invention (Taxi) 41: Circuit Contact 42: Solder (Please read the precautions on the back before filling out this page) 44: Filler 46: Sealing resin 48 Figures 3A to 3C of the embodiment of the heat sink are schematic cross-sectional views showing a flip-chip structure manufacturing process according to a preferred embodiment of the present invention. In these figures, only a part of the manufacturing of the bonding pads is drawn. The Intellectual Property Bureau of the Ministry of Economic Affairs® Industrial and Consumer Cooperative Seal Please refer to FIG. 3A. There is a bonding pad 32 on the wafer 30. A protective layer 34 is formed on the wafer 30 to expose the bonding pad 32. Next, a conductive material layer 36 is formed on the bonding pad 32. Among them, the wafer 30 includes a general semiconductor wafer having a plurality of semiconductor elements and circuits thereon. The material of the bonding pad 32 is, for example, aluminum, which connects the circuits and components on the chip 30. The material of the conductive material layer 36 includes conductive adhesive, anisotropic conductive paste (ACP), and anisotropic conductive film (Anisotropic conductive film). Conductive Fiim (ACF) or silver paste (Ag paste) The method of forming the conductive material layer 36 includes screen printing, dispensing, needle transfer or punch (for ACF). Referring to FIG. 3B, a copper ball 38 is placed on the conductive material layer 36. The copper ball 38 and the conductive material layer 36 are used as bumps. The copper ball 38 can be electroplated in advance to form a plating layer 39 to increase subsequent Bondability (Solderability), oxidation resistance, and corrosion resistance. The material of the plating layer 39 includes gold (Au), silver (Ag), tin (Sn), palladium (Pd), and nickel (Ni). 6 This paper scale is applicable to China National Standards (CNS) A4 specifications (210 X 297 mm) sag 4392 3 7 rd nc / o U2 A7 B7 V. Description of the invention (s) From the above process, it can be known that when the bumps are manufactured by the present invention The bumps can be formed without the need for processes such as lithographic etching, and the process is relatively simple. Moreover, the electrical and mineral parts of the copper balls are carried out separately and independently. In the entire process, the wafer does not need to be plated, and the circuit characteristics of the wafer are not affected On the other hand, the placement of conductive materials and copper balls can be carried out in large quantities, so the yield can be increased. Please refer to FIG. 3C, place solder 42 on the circuit contact 41 of the carrier 40, and then adhere to the carrier 40 For the wafer 30, the bonding method is to join the copper ball 38 with the solder 42. Then, an underfill step is performed to insert an underfill 44 between the wafer 30 and the carrier 40 to improve the reliability of assembly. The carrier 40 includes a ball-shaped grid array substrate (BGA substrate), an island-shaped array substrate (LGA substrate), or a printed circuit board (PCB), and the material of the carrier 40 includes BT resin, FR4 resin, ceramic material, or polyurethane. Amidine lyimide) etc. Fig. 4 is a schematic cross-sectional view of a semiconductor package according to the flip-chip structure of the present invention. Fig. 5 is a schematic cross-sectional view of another semiconductor package according to the flip-chip structure of the present invention. Printed 81! U ί In iu ---------- nn I U3-6 (Please read the precautions on the back before filling this page) Please refer to Figure 4 and Figure 5 for charging After the step, the sealing resin 46 may be further used to cover the wafer 30 to form a packaging structure, and then a heat sink 48 may be adhered to the packaging resin 46 as shown in FIG. 4 to increase the heat dissipation of the entire packaging structure. The material of the encapsulating resin 46 includes epoxy resin. However, when the encapsulating resin 46 is used for encapsulation, the back surface of the wafer 30 can be exposed. Then, the heat sink 48 is directly adhered to the exposed back surface of the wafer 30. As shown in the figure, the heat generated by the wafer 30 can be directly dissipated from 7 & Zhang scales applicable to China's {CNS) A4 specification (210X297 mm) ~~ ', 4 j--:. 433 4ΐ \' I. iUu. " i () 2 A7 B7 V. Description of the Invention (Gray) Hot film 48 belts To further increase the cooling efficiency. (Please read the precautions on the back before filling this page) In the present invention, since the bumps are formed of copper balls, they can be directly adhered to the solder on the carrier, and the plating on it can be improved. Bondability with solder. In addition, in the above embodiments, the copper balls are placed on the bonding pads of the wafer and then bonded to the carrier or the circuit board. However, those skilled in the art should know that the copper ball can also be planted on the carrier or circuit board first, and then the wafer with the conductive material layer on the bonding pad can be bonded to the copper ball. The effect and structure are the same as the above embodiment. Therefore, the flip-chip structure of the present invention can be compatible with the conventional packaging process without changing the process and the design of the carrier. Copper balls are electroplated to increase bonding, oxidation resistance and corrosion resistance. In summary, the flip-chip structure of the present invention has at least the following advantages: 1. In the present invention, the bumps are composed of copper balls and conductive materials, and can be formed without the complicated lithographic etching and electroplating processes. Simpler. And because the placement of conductive glue and copper balls can be carried out in large quantities, the yield can be improved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. The present invention uses copper balls as bumps, which can be directly bonded to solder, without the need to change the process and the design of the carrier, and is compatible with the current packaging process. 3. For today's semiconductor products, high-speed, low-loss requirements have gradually adopted copper as the material of the interconnect. However, the flip-chip structure of the present invention also uses copper balls as the bonding medium, which has better conductive properties and can reduce impedance. 5. Avoid signal delay and signal attenuation, and meet future product requirements. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to be used for 8 paper sizes. The Chinese National Standard (CNS) Λ4 specification (2! 0X297 mm) is used. 43.Ulu r.iloc / 002 A7 B7 V. Invention Explanation (q) Limits the present invention. Anyone who is familiar with this skill, 'can be changed and retouched without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention Defined shall prevail. -I— I---I—I 0¾-a (Please read the notes on the back before filling out this page) The printed paper size of the printed paper printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) Λ4 specification (210X297 Mm)

Claims (1)

A8 B8 ^334tw f.doc/O 02 六、申請專利範圍 1. 一種覆晶結構的製程，該製程至少包括： 提供一晶片，其中該晶片上至少有一個接合墊； 在該接合墊上放置一導電材質；以及 在該導電材質上放置一金屬球。 2. 如申請專利範圍第1項所述之覆晶結構製程，其中 該接合墊的材質包括是鋁。 3. 如申請專利範圍第1項所述之覆晶結構製程，其中 該導電材質包括是導電膠。 4·如申請專利範圍第1項所述之覆晶結構製程，其中 該導電材質包括是銀膠。 5. 如申請專利範圍第I項所述之覆晶結構製程，其中 該導電材質的放置方式是網版印刷。 6. 如申請專利範圍第1項所述之覆晶結構製程，其中 該導電材質的放置方式是使用點膠的方式。 7·如申請專利範圍第1項所述之覆晶結構製程，其中 該導電材質的放置方式是使用沾針轉移的方式。 8. 如申請專利範圍第1項所述之覆晶結構製程，其中 該金屬球的材質包括是銅。 經濟部中央標準局貝工消f合作社印製 (請先W讀背面之注意事項再填寫本頁) 9. 如申請專利範圍第1項所述之覆晶結構製程，其中 該金屬球事先經過電鍍處理，在該金屬球表面形成一鍍 層。 1 〇.如申請專利範圍第9項所述之覆晶結構製程，其中 該鍍層材質係選自於由金、銀、錫、鈀、鎳及該等之組合 所組成之族群中的一種材質。 10 ^紙浪尺度適用中國國家標ί ( CNS >_A4規格（210X297公ftT ABCD 4 3 3 41 vv f. d 〇 c / 0 02 六、申請專利範圍 Π.如申請專利範圍第1項所述之覆晶結構製程，更包 括粘著該晶片於一承載器上。 I2.如申請專利範圍第11項所述之覆晶結構製程，其 中該承載器包括是印刷電路板。 Π.如申請專利範圍第11項所述之覆晶結構製程，其 中該承載器包括是球腳格狀陣列基板。 H·如申請專利範圍第11項所述之覆晶結構製程，其 中該承載器包括是島狀陣列基板。 15.—種覆晶結構，至少包括： —晶片> 複數個接合墊，該些接合墊位於該晶片之同一面上； 一導電材質，配置於每一該些接合墊上；；以及 複數個金屬球，其中每一該些金屬球分別配置於該些 接合墊之一上，並以該導電材質與該些接合墊接合。 10.如申請專利範圍第15項所述之覆晶結構，其中該 些接合墊的材質包括是鋁。 I7-如申請專利範圍第I5項所述之覆晶結構，其中該 些金屬球的材質包括是銅。 18.如申請專利範圍第15項所述之覆晶結構，其中該 些金屬球事先經過電鍍處理，在該些金屬球表面形成一鍍 層。 19·如申請專利範圍第18項所述之覆晶結構，其中該 鍍層材質選自於由金、銀 '錫、鈀、鎳及該等之組合所組 成之族群中之一種材質。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ϋ n n I n I n ! I I It n T n fi I (齋先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局男工消費合作社印裝 經濟部中央標隼局員工消費合作社印製 i439237 Μ 4 33 4i^ I'.doc/OOS LPq 六、申請專利範圍 20. 如申請專利範圍第15項所述之覆晶結構，其中該 導電材質包括是導電膠。 21. 如申請專利範圍第15項所述之覆晶結構，其中該 導電材質包括是銀膠。 22. 如申請專利範圍第I5項所述之覆晶結構，其中該 導電材質包括異方性導電膠。 23. 如申請專利範圍第15項所述之覆晶結構，其中該 導電材質包括異方性導電膜。 24. —種半導體封裝，至少包括： 一晶片； 複數個接合墊，該些接合墊位於該晶片之同一面上； 一導電材質，配置於每一該些接合墊上； 複數個金屬球，且每一該些金屬球分別配置於該些接 合墊之一上，並以該導電材質與該些接合墊連接；以及 一承載器，該承載器具有複數個接點，分別與該些金 屬球連接。 25. 如申請專利範圍第24項所述之半導體封裝，其中 該些接合墊的材質包括是銘。 26. 如申請專利範圍第24項所述之半導體封裝，其中 該些金屬球的材質包括是銅。 27. 如申請專利範圍第24項所述之半導體封裝，其中 該些金屬球事先經過電鍍處理，在該些金屬球表面形成一 鍍層。 28. 如申請專利範圍第27項所述之半導體封裝，其中 装 訂 線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 8 8 8 8 ABCD 經濟部中央榇準局負工消費合作社印掣 六、申請專利範圍 該鑛層之材質選自於金、銀、錫、IG、鎳和該等之組合所 組成之族群中的一種材質。 29. 如申請專利範圍第24項所述之半導體封裝，其中 * 、 該導電材質包括是導電膠。 30. 如申請專利範圍第24項所述之半導體封裝，其中 該導電材質包括是銀膠。 31. 如申請專利範圍第24項所述之半導體封裝，其中 該導電材質包括異方性導電膠。 32. 如申請專利範圍第24項所述之半導體封裝，其中 該導電材質包括異方性導電膜。 33. 如申請專利範圍第24項所述之半導體封裝，其中 該承載器包括是印刷電路板。 34. 如申請專利範圍第24項所述之半導體封裝，其中 該承載器包括是球腳格狀陣列基板。 35. 如申請專利範圍第24項所述之半導體封裝，其中 該承載器包括是島狀陣列基板。 36. —種半導體封裝，至少包括： 一晶片，具有第一表面及第二表面； 複數個接合墊，該些接合墊位於該晶片之第一表面 上； 一導電材質，配置於每一該些接合墊上； 複數個金屬球1且每一該些金屬球分別配置於該些接 合墊之一上，並以該導電材質與該些接合墊連接； 一承載器，該承載器具有複數個接點，分別與該些金 (殊-先閱讀背面之注意事項再填寫本頁) -=° .· y 本紙張尺度適用中國國家標準（CNS ) A4現格（2丨0X297公嫠） ABCD 433 4i\v t'.di>c/0 02 六、申請專利範圍 屬球連接；以及 一封裝材料，該封裝材料覆蓋該晶片。 37.如申請專利範圍第36項所述之半導體封裝，更包 括一散熱片粘著於該封裝材料。 38·如申請專利範圍第36項所述之半導體封裝，其中 該些接合墊的材質包括是鋁。 39. 如申請專利範圍第36項所述之半導體封裝，其中 該些金屬球的材質包括是銅。 40. 如申請專利範圍第36項所述之半導體封裝，其中 該些金屬球事先經過電鍍處理，在該些金屬球表面形成一 鍍層。 41. 如申請專利範圍第40項所述之半導體封裝，其中 該鍍層之材質選自於金、銀、錫、鈀、鎳和該等之組合所 組成之族群中的一種材質。 42. 如申請專利範圍第36項所述之半導體封裝，其中 該導電材質包括是導電膠。 43. 如申請專利範圍第36項所述之半導體封裝，其中 該導電材質包括是銀膠。 44. 如申請專利範圍第36項所述之半導體封裝，其中 該導電材質包括異方性導電膠。 45. 如申請專利範圍第36項所述之半導體封裝，其中 該導電材質包括異方性導電膜。 46. 如申請專利範圍第36項所述之半導體封裝，其中 該承載器包括是印刷電路板。 ---------A------訂------束 (請t閲讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） 經濟部中央標隼局貝工消费合作社ip東 '7 A8 1 BS 4 3 3 41 \v ί', d oc / () () 2 C8 _ D8 六、申請專利範圍 47·如申請專利範圍第36項所述之半導體封裝，其中 該承載器包括是球腳格狀陣列基板。 48·如申請專利範圍第36項所述之半導體封裝，其中 該承載器包括是島狀陣列基板。 49·一種半導體封裝，至少包括： 一晶片’具有第一表面及第二表面； 複數個接合墊’該些接合墊位於該晶片之第一表面 上； 一導電材質’配置於每一該些接合墊上； 複數個金屬球’且每一該些金屬球分別配置於該些接 合墊之一上，並以該導電材質與該些接合墊連接； 一承載器’該承載器具有複數個接點，分別與該些金 屬球連接；以及 一封裝材料’該封裝材料覆蓋該晶片，但暴露出該晶 片的第二表面。 50如申請專利範圍第49項所述之半導體封裝，更包 括一散熱片粘著於該晶片暴露出的表面。 51.如申請專利範圍第49項所述之半導體封裝，其中 該些接合墊的材質包括是鋁。 52·如申請專利範圍第49項所述之半導體封裝，其中 該些金屬球的材質包括是銅。 53·如申請專利範圍第49項所述之半導體封裝，其中 該些金屬球事先經過電鍍處理，在該些金屬球表面形成一 鍍層。 本紙張尺度適用中國國家揉準（CNS ) A4現格（2丨0XW7公釐） ---------Λ------,玎------it {請4·閲讀背ά之注意事項再填寫本頁) A8 B8 4334t\\ r.doc/002 U〇 六、申請專利範圍 54. 如申請專利範圍第53項所述之半導體封裝，其中 該鍍層之材質選自於金、銀、錫、鈀、鎳和該等之組合所 組成之族群中的一種材質。 55. 如申請專利範圍第49項所述之半導體封裝，其中 該導電材質包括是導電膠。 56. 如申請專利範圍第49項所述之半導體封裝，其中 該導電材質包括是銀膠。 57. 如申請專利範圍第49項所述之半導體封裝，其中 該導電材質包括異方性導電膠。 58. 如申請專利範圍第49項所述之半導體封裝，其中 該導電材質包括異方性導電膜。 59. 如申請專利範圍第49項所述之半導體封裝，其中 該承載器包括是印刷電路板。 60. 如申請專利範圍第49項所述之半導體封裝，其中 該承載器包括是球腳格狀陣列基板。 61. 如申請專利範圍第49項所述之半導體封裝，其中 該承載器包括是島狀陣列基板。 裝 訂" (諄先閱^:面之注意事項再填寫本！) 經濟部中央橾隼局員工消費合作社印製 本紙張尺度適用中國國家樣準（CNS ) A4规格（210Χ297公釐）A8 B8 ^ 334tw f.doc / O 02 6. Scope of patent application 1. A process of flip-chip structure, the process at least includes: providing a wafer, wherein the wafer has at least one bonding pad; placing a conductive pad on the bonding pad Material; and placing a metal ball on the conductive material. 2. The flip-chip structure manufacturing process described in item 1 of the patent application scope, wherein the material of the bonding pad includes aluminum. 3. The flip-chip structure manufacturing process as described in item 1 of the patent application scope, wherein the conductive material includes a conductive adhesive. 4. The flip-chip structure manufacturing process according to item 1 of the scope of patent application, wherein the conductive material includes silver glue. 5. The flip-chip structure manufacturing process described in item I of the patent application scope, wherein the conductive material is placed by screen printing. 6. The flip-chip structure manufacturing process as described in item 1 of the scope of patent application, wherein the conductive material is placed using a method of dispensing. 7. The flip-chip structure manufacturing process as described in item 1 of the scope of patent application, wherein the conductive material is placed using a dipstick transfer method. 8. The flip-chip structure manufacturing process according to item 1 of the scope of patent application, wherein the material of the metal ball includes copper. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Bei Gong Xiao Cooperative (please read the precautions on the back, and then fill out this page) 9. The flip-chip structure manufacturing process described in item 1 of the scope of patent application, in which the metal ball is electroplated in advance After processing, a plating layer is formed on the surface of the metal ball. 10. The flip-chip structure manufacturing process according to item 9 of the scope of the patent application, wherein the coating material is a material selected from the group consisting of gold, silver, tin, palladium, nickel, and combinations thereof. 10 ^ Paper wave scale applies Chinese national standard (CNS > _A4 specification (210X297 ftT ABCD 4 3 3 41 vv f. D occ / 0 02) 6. Scope of patent application Π. As described in item 1 of the scope of patent application The flip-chip structure manufacturing process further includes adhering the wafer to a carrier. I2. The flip-chip structure manufacturing process described in item 11 of the patent application scope, wherein the carrier includes a printed circuit board. Π. If applying for a patent The flip-chip structure manufacturing process according to item 11 of the scope, wherein the carrier includes a ball-foot lattice array substrate. H. The flip-chip structure manufacturing process according to item 11 of the patent application scope, wherein the carrier includes an island-like structure. 15. An array substrate. 15. A flip-chip structure, including at least:-a wafer> a plurality of bonding pads, the bonding pads being located on the same side of the wafer; a conductive material disposed on each of the bonding pads; and A plurality of metal balls, each of which is disposed on one of the bonding pads, and is bonded to the bonding pads with the conductive material. 10. The flip-chip structure according to item 15 of the scope of patent application Of which these joints The material of the pad includes aluminum. I7- The flip-chip structure described in item I5 of the scope of patent application, wherein the material of the metal balls includes copper. 18. The flip-chip structure described in item 15 of the scope of patent application, The metal balls are subjected to an electroplating treatment in advance to form a plating layer on the surfaces of the metal balls. 19. The flip-chip structure according to item 18 of the scope of patent application, wherein the material of the plating layer is selected from gold, silver, tin, One of the materials in the group consisting of palladium, nickel, and combinations thereof. This paper size applies to China National Standard (CNS) A4 (210X297 mm) ϋ nn I n I n! II It n T n fi I ( (Please read the notes on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by male consumer co-operatives of the Ministry of Economic Affairs, printed by the Consumers' Cooperative of Central Standards Bureau of the Ministry of Economic Affairs, i439237 Μ 4 33 4i ^ I'.doc / OOS LPq Scope 20. The flip-chip structure described in item 15 of the scope of patent application, wherein the conductive material includes conductive glue. 21. The flip-chip structure described in item 15 of the scope of patent application, wherein the conductive material includes silver glue. . twenty two. The flip-chip structure as described in item I5 of the scope of patent application, wherein the conductive material includes anisotropic conductive adhesive. 23. The flip-chip structure as described in item 15 of the scope of patent application, wherein the conductive material includes anisotropic conductive 24. A semiconductor package at least comprising: a wafer; a plurality of bonding pads, the bonding pads are located on the same side of the wafer; a conductive material is disposed on each of the bonding pads; a plurality of metal balls, And each of the metal balls is respectively disposed on one of the bonding pads, and is connected to the bonding pads with the conductive material; and a carrier, the carrier has a plurality of contacts respectively connected to the metal balls. connection. 25. The semiconductor package according to item 24 of the scope of patent application, wherein the material of the bonding pads includes an inscription. 26. The semiconductor package according to item 24 of the scope of patent application, wherein the material of the metal balls includes copper. 27. The semiconductor package according to item 24 of the scope of patent application, wherein the metal balls are subjected to an electroplating treatment in advance to form a plating layer on the surfaces of the metal balls. 28. The semiconductor package as described in item 27 of the scope of patent application, in which the binding line (please read the precautions on the back before filling this page) This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 8 8 8 8 ABCD Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 6. The scope of the patent application The material of this ore layer is selected from the group consisting of gold, silver, tin, IG, nickel and combinations thereof Material. 29. The semiconductor package according to item 24 of the scope of patent application, wherein *, the conductive material includes a conductive adhesive. 30. The semiconductor package as described in claim 24, wherein the conductive material includes silver glue. 31. The semiconductor package according to item 24 of the scope of patent application, wherein the conductive material includes an anisotropic conductive adhesive. 32. The semiconductor package according to item 24 of the scope of patent application, wherein the conductive material includes an anisotropic conductive film. 33. The semiconductor package as described in claim 24, wherein the carrier includes a printed circuit board. 34. The semiconductor package as described in claim 24, wherein the carrier comprises a ball-foot grid array substrate. 35. The semiconductor package as described in claim 24, wherein the carrier includes an island array substrate. 36. A semiconductor package, at least comprising: a wafer having a first surface and a second surface; a plurality of bonding pads, the bonding pads being located on the first surface of the wafer; a conductive material disposed on each of the plurality of On a bonding pad; a plurality of metal balls 1 and each of the metal balls are respectively arranged on one of the bonding pads and are connected to the bonding pads with the conductive material; a carrier having a plurality of contacts , Separately with the gold (special-read the notes on the back before filling out this page)-= °. · Y This paper size applies the Chinese National Standard (CNS) A4 grid (2 丨 0X297) 嫠 ABCD 433 4i \ v t'.di &c; c / 0 02 6. The scope of patent application is ball connection; and a packaging material, the packaging material covers the chip. 37. The semiconductor package according to item 36 of the scope of patent application, further comprising a heat sink adhered to the packaging material. 38. The semiconductor package according to item 36 of the scope of patent application, wherein the material of the bonding pads is aluminum. 39. The semiconductor package according to item 36 of the scope of patent application, wherein the material of the metal balls includes copper. 40. The semiconductor package according to item 36 of the scope of patent application, wherein the metal balls have been electroplated in advance to form a plating layer on the surfaces of the metal balls. 41. The semiconductor package according to item 40 of the scope of patent application, wherein the material of the plating layer is one selected from the group consisting of gold, silver, tin, palladium, nickel, and combinations thereof. 42. The semiconductor package as described in claim 36, wherein the conductive material includes a conductive adhesive. 43. The semiconductor package as described in claim 36, wherein the conductive material includes a silver paste. 44. The semiconductor package according to item 36 of the scope of patent application, wherein the conductive material includes an anisotropic conductive adhesive. 45. The semiconductor package as described in claim 36, wherein the conductive material includes an anisotropic conductive film. 46. The semiconductor package as described in claim 36, wherein the carrier includes a printed circuit board. --------- A ------ Order ------ Bundle (please read the notes on the back and fill in this page again) Printed on paper Standards are applicable to Chinese National Standards (CNS) Α4 specifications (210 X 297 mm), Central Laboratories of Ministry of Economic Affairs, Shellfish Consumer Cooperative, IP East '7 A8 1 BS 4 3 3 41 \ v ί', d oc / () () 2 C8 _ D8 6. Patent application scope 47. The semiconductor package described in item 36 of the patent application scope, wherein the carrier includes a ball-foot grid array substrate. 48. The semiconductor package as described in claim 36, wherein the carrier includes an island array substrate. 49. A semiconductor package, comprising at least: a chip 'having a first surface and a second surface; a plurality of bonding pads' said bonding pads are located on a first surface of said wafer; a conductive material' is disposed at each of said bondings A plurality of metal balls ', and each of the metal balls is respectively disposed on one of the bonding pads and is connected to the bonding pads with the conductive material; a carrier' the carrier has a plurality of contacts, Respectively connected with the metal balls; and a packaging material 'the packaging material covers the wafer, but exposes the second surface of the wafer. 50. The semiconductor package according to item 49 of the scope of patent application, further comprising a heat sink adhered to the exposed surface of the wafer. 51. The semiconductor package according to item 49 of the scope of patent application, wherein the material of the bonding pads is aluminum. 52. The semiconductor package according to item 49 of the scope of patent application, wherein the materials of the metal balls include copper. 53. The semiconductor package according to item 49 of the scope of patent application, wherein the metal balls are subjected to an electroplating treatment in advance to form a plating layer on the surfaces of the metal balls. This paper size is applicable to Chinese National Standard (CNS) A4 (2 丨 0XW7mm) --------- Λ ------, 玎 ------ it {Please 4 · Read the notes on the back and fill in this page) A8 B8 4334t \\ r.doc / 002 U〇 6. Patent application scope 54. The semiconductor package described in item 53 of the patent application scope, wherein the material of the plating layer is selected from A material in a group of gold, silver, tin, palladium, nickel, and combinations thereof. 55. The semiconductor package according to item 49 of the scope of patent application, wherein the conductive material includes a conductive adhesive. 56. The semiconductor package according to item 49 of the application, wherein the conductive material includes silver paste. 57. The semiconductor package according to item 49 of the scope of patent application, wherein the conductive material includes an anisotropic conductive adhesive. 58. The semiconductor package according to item 49 of the scope of patent application, wherein the conductive material includes an anisotropic conductive film. 59. The semiconductor package as described in claim 49, wherein the carrier includes a printed circuit board. 60. The semiconductor package as described in claim 49, wherein the carrier comprises a ball-foot grid array substrate. 61. The semiconductor package as described in claim 49, wherein the carrier comprises an island array substrate. Binding " (谆 Read first ^: Notes on the face before filling in this!) Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 × 297 mm)
TW088105830A 1999-04-13 1999-04-13 Flip chip structure and its manufacturing method TW439237B (en)

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Publication number Priority date Publication date Assignee Title
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

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Publication number Priority date Publication date Assignee Title
KR100455727B1 (en) * 2002-01-07 2004-11-06 주식회사 하이닉스반도체 flip chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

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