JPH03256314A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPH03256314A JPH03256314A JP5542490A JP5542490A JPH03256314A JP H03256314 A JPH03256314 A JP H03256314A JP 5542490 A JP5542490 A JP 5542490A JP 5542490 A JP5542490 A JP 5542490A JP H03256314 A JPH03256314 A JP H03256314A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- recess
- positions
- semiconductor
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000005498 polishing Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 27
- 238000000034 method Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置製造において基板として使用され
る半導体ウェハーに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer used as a substrate in the manufacture of semiconductor devices.
従来、この種の半導体ウェハーの製造履歴および特性の
表示は、ロットＮＯおよび検査成績書として半導°体つ
ェハーの梱包に添付する形で行なわれており、添付され
たデータと個々の半導体ウェハーとの対応はレーザーマ
ーカー等により半導体ウェハー表面に特定の通し番号等
を記入する場合と梱包時の順番によって行なう場合とが
あった。Conventionally, the manufacturing history and characteristics of this type of semiconductor wafer have been displayed in the form of a lot number and inspection report attached to the packaging of the semiconductor wafer, and the attached data and individual semiconductor wafer In some cases, a specific serial number was written on the surface of the semiconductor wafer using a laser marker, and in other cases, this was done by marking the order of packaging.
上述した従来の方法のうち、前者は半導体装置を形成す
る半導体ウェハー表面に印字するため、印字された場所
およびその周辺に形成された半導体装置は不良になる他
、半導体装置の製造工程の進行により何重にもパターン
が重ね合わさった場合その判別が困難になる欠点があり
、後者は半導体ウェハーの梱包を解いた後、半導体製造
工程に適合する形にバッチを組み直す際または半導体製
造工程の各処理の時点で半導体ウェハーの取り違い等に
より順番が乱れ、添付された特性票と対応がとれなくな
る欠点があった。Of the conventional methods mentioned above, the former prints on the surface of the semiconductor wafer on which the semiconductor devices are formed, so the semiconductor devices formed in and around the printed area will be defective, and as the semiconductor device manufacturing process progresses, The disadvantage is that it becomes difficult to distinguish patterns when they are stacked many times over, and the latter is used when reassembling a batch into a form suitable for the semiconductor manufacturing process after unpacking the semiconductor wafer, or during each process in the semiconductor manufacturing process. At this point, there was a drawback that the order was disrupted due to a mix-up of semiconductor wafers, etc., and it became impossible to correspond with the attached characteristic sheet.
本発明の目的は、半導体装置を形成する半導体ウェハー
表面への組響を与えることなく、かつ工程の進行に伴な
うパターンの重ね合せにより書き込まれた符号の読み取
りが困難になることがない半導体ウェハーを提供するこ
とである。An object of the present invention is to provide a semiconductor device that does not affect the surface of a semiconductor wafer that forms a semiconductor device, and that does not make it difficult to read written codes due to the overlapping of patterns as the process progresses. The goal is to provide wafers.
〔課題を解決するための手段）
本発明の半導体ウェハーは、該半導体ウェハー側壁の周
方向の等間隔の複数の位置のうち、該半導体ウェハーに
与えられた２進数コートの「１」または「０」に対応し
た位置に凹部が形成されている。[Means for Solving the Problems] The semiconductor wafer of the present invention has a binary number coat of "1" or "0" given to the semiconductor wafer at a plurality of equally spaced positions in the circumferential direction of the side wall of the semiconductor wafer. A recess is formed at a position corresponding to "."
半導体ウェハー側壁に分類、識別のための表示を設ける
ので、半導体装置を形成する半導体ウェハー表面への影
響を与えることなく、かつ工程の進行に伴なうパターン
の重ね合せにより書き込まれた符号の読み取りが困難に
なることもない。Displays for classification and identification are provided on the side wall of the semiconductor wafer, so it is possible to read codes written by superimposing patterns as the process progresses without affecting the surface of the semiconductor wafer that forms semiconductor devices. It doesn't become difficult.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の半導体ウェハーの側面
図、第２図はその断面図である。FIG. 1 is a side view of a semiconductor wafer according to a first embodiment of the present invention, and FIG. 2 is a sectional view thereof.
この半導体ウェハーはスライス工程、面取り工程、鏡面
研磨工程終了後の側壁１の周方向の等間隔の位置Ａ−Ａ
、Ｂ−Ｂ、Ｃ−Ｃ，Ｄ−Ｄ、ＥＥ、Ｆ−ＦのうちＡ−Ａ
、Ｂ−Ｂ、Ｄ−ＤおよびＥ−Ｅの位置にＹＡＧレーザビ
ームが照射されて円状の凹部２が形成されている。This semiconductor wafer is placed at equidistant positions A-A in the circumferential direction of the side wall 1 after the slicing process, chamfering process, and mirror polishing process.
, A-A among B-B, C-C, D-D, EE, F-F
, BB, DD, and EE are irradiated with a YAG laser beam to form circular recesses 2.
本実施例ては、凹部２を「１」、凹部２の形成されてい
ない平坦部を「０」として用いるものであり、ＡからＦ
にかけてｒｌ １０１１０Ｊの２進数を示す。なお、凹
部２を「０」、平坦部を「１」として用いても何ら支障
は無い。In this example, the concave part 2 is used as "1" and the flat part where the concave part 2 is not formed is used as "0", and from A to F.
shows the binary number of rl 10110J. Note that there is no problem in using the recessed portion 2 as “0” and the flat portion as “1”.
第３図は本発明の第２の実施例の半導体ウェハーの側面
図、第４図はその断面図である。FIG. 3 is a side view of a semiconductor wafer according to a second embodiment of the present invention, and FIG. 4 is a sectional view thereof.
この半導体ウェハーはスライス工程、面取り工程、鏡面
研磨工程終了後の側壁１の周方向の等間隔の位置Ａ−Ａ
、Ｂ−Ｂ、Ｃ−Ｃ，Ｄ−Ｄ、ＥＥ、Ｆ−ＦのうちＡ−Ａ
、Ｂ−Ｂ、Ｄ−ＤおよびＥ−Ｈの位置にタイシンクソー
による切り込みの凹部３が形成されている。This semiconductor wafer is placed at equidistant positions A-A in the circumferential direction of the side wall 1 after the slicing process, chamfering process, and mirror polishing process.
, A-A among B-B, C-C, D-D, EE, and F-F
, B-B, D-D and E-H, recesses 3 are formed by cutting with a tie sink saw.
本実施例でも、第１の実施例と同様に凹部３を「１」、
凹部３の形成されていない平坦部を「０」として用いる
ものである。In this embodiment, similarly to the first embodiment, the recess 3 is set to "1",
The flat portion where the recessed portion 3 is not formed is used as “0”.
なお、本実施例においては結晶引上げ時のインゴット単
位になるがインゴット形成後より処理できる利点を有す
る。In this embodiment, the ingot unit is used when pulling the crystal, but it has the advantage that it can be processed after the ingot is formed.
以上説明したように本発明は、半導体ウェハー外周側壁
に等間隔で配された複数の位置のうち当該半導体ウェハ
ーに与えられた２進数コードの「１」または「０」に対
応した点に凹部を形成することにより、個々の半導体ウ
ェハーについて半導体装置を形成する半導体ウェハー表
面への影響を与えることなく、かつ工程の進行に伴なう
パターンの重ね合せにより書き込まれた符号の読み取り
が困難になることなく識別用の２進数コートを形成でき
る効果がある。As explained above, the present invention provides recesses at points corresponding to "1" or "0" of the binary code given to the semiconductor wafer among a plurality of positions arranged at equal intervals on the outer peripheral side wall of the semiconductor wafer. By forming a code on each semiconductor wafer, it becomes difficult to read the written code due to the overlapping of patterns as the process progresses, without affecting the surface of the semiconductor wafer that forms the semiconductor device. This has the effect that a binary code for identification can be formed without any need for a binary number code.
第１図は本発明の第１実施例の半導体ウェハーの側面図
、第２図はその断面図、第３図は本発明の′！Ｊ２の実
施例の半導体ウェハーの側面図、第４図はその断面図で
ある。
１・−・・・半導体ウェハー側壁、
２・・・・・・レーザービームの照射による凹部、３・
・・・・・タイシンクソーによる切り込みによる凹部。FIG. 1 is a side view of a semiconductor wafer according to a first embodiment of the present invention, FIG. 2 is a sectional view thereof, and FIG. 3 is a side view of a semiconductor wafer according to a first embodiment of the present invention. A side view of the semiconductor wafer of Example J2, and FIG. 4 is a cross-sectional view thereof. 1...Semiconductor wafer side wall, 2...Concavity caused by laser beam irradiation, 3...
...Concavity created by a cut made by a tie sink saw.
Claims (1)
うち、該半導体ウェハーに与えられた２進数コードの「
１」また「０」に対応した位置に凹部が形成されている
ことを特徴とする半導体ウェハー。[Claims] 1. In a semiconductor wafer, among a plurality of equally spaced positions in the circumferential direction of the side wall of the semiconductor wafer, a binary code given to the semiconductor wafer is "
1. A semiconductor wafer characterized in that a recess is formed at a position corresponding to ``1'' or ``0''.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5542490A JPH03256314A (en) | 1990-03-06 | 1990-03-06 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5542490A JPH03256314A (en) | 1990-03-06 | 1990-03-06 | Semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03256314A true JPH03256314A (en) | 1991-11-15 |
Family
ID=12998199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5542490A Pending JPH03256314A (en) | 1990-03-06 | 1990-03-06 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03256314A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5894172A (en) * | 1996-05-27 | 1999-04-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with identification function |
| US6877668B1 (en) | 1999-10-26 | 2005-04-12 | Komatsu Electronic Metals Co., Ltd. | Marking method for semiconductor wafer |
| JP2007095909A (en) * | 2005-09-28 | 2007-04-12 | Disco Abrasive Syst Ltd | Wafer having crystal orientation identifying portion of special shape |
-
1990
- 1990-03-06 JP JP5542490A patent/JPH03256314A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5894172A (en) * | 1996-05-27 | 1999-04-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with identification function |
| US6877668B1 (en) | 1999-10-26 | 2005-04-12 | Komatsu Electronic Metals Co., Ltd. | Marking method for semiconductor wafer |
| JP2007095909A (en) * | 2005-09-28 | 2007-04-12 | Disco Abrasive Syst Ltd | Wafer having crystal orientation identifying portion of special shape |
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