JPH03255542A - Dummy fault system - Google Patents

Abstract

PURPOSE:To generate the dummy fault of random contents by adding a simple circuit by moving a scan path by OR of a scan instructing signal and a dummy fault instructing signal and generating a dummy fault. CONSTITUTION:In an information processor which includes plural pieces of LSIs 20, 21 provided with a scan path and an error detecting circuit, and can operate the scan path independently by an LSI unit, the operation of the scan path of the LSIs 20, 21 is executed by OR of scan instructing signals 101, 102 for instructing the operation of the scan path to the LSIs 20, 21, and dummy fault instructing signals 104, 105 for instructing the generation of a dummy fault to the LSIs 20, 21. In such a manner, not only and error is generated by a dummy fault, but also a phenomenon being similar to an actual fault such as a data breakdown and the propagation of an error, etc., is generated, and the fault resisting function can be confirmed.

Description

[Detailed description of the invention] [Industrial application field] The present invention provides a plurality of LS Regarding the equipment, especially each LS Regarding the method of

■Generates a pseudo fault in the information processing unit including the chip [Prior art] Conventionally, this type of pseudo fault method detects a parity error by inverting one bit of a data line with a parity bit using a pseudo fault instruction signal. There are two methods: a method in which an error is generated, and a method in which a false fault instruction signal is ORed with an error detection signal output from an error detection circuit to make it appear as if an error has occurred.

[Problem to be solved by the invention]

In the former method mentioned above, it is necessary to insert an exclusive OR gate etc. for each bit of the data line.
It is inevitable that the delay time of the data line increases. −
Since the delay time of the main data line determines the clock frequency, inserting the gate on the main data line will degrade the performance of the entire system. Therefore, it becomes difficult to generate a false fault on the main data line.

On the other hand, in the latter method, although the influence on the delay time can be avoided, it is only possible to report error detection, and no abnormality occurs in processing other than failure processing. The purpose of pseudo-failure generation is to confirm the fault tolerance, performance, etc. of devices and systems.

Therefore, it is better not only to cause an error to occur due to a false failure, but also to cause a phenomenon that is closer to an actual failure, such as data destruction or error propagation. Therefore, the latter method is inferior in terms of confirming the fault tolerance function.

[Means to solve the problem]

The configuration of the false failure method of the present invention is such that in an information processing device that includes a plurality of LSIs each having a scan path and an error detection circuit, and is capable of operating the scan path independently for each LSI, The operation of the scan path of the LSI is executed by the logical sum of the scan instruction No. 8 which instructs the operation of the LSI and the pseudo fault instruction signal which instructs the LSI to generate a pseudo fault.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment shows an arithmetic processing device, which is connected to a diagnostic control device via a diagnostic control circuit 10 and an interface line 100 .

Large-scale integrated circuit (hereinafter referred to as LSI) 20 and LSI
21 includes a circuit that performs calculations. OR gate 30.
The OR gate 31 is a gate that performs a logical sum, and the switching circuit 40 switches between the scan-out signal 201 and the scan-out signal 202.

The operation in FIG. 1 will be explained. When the diagnostic control device instructs the diagnostic control circuit 10 to scan the LSI 20 via the interface line 100, the scan instruction signal 101 becomes "1", and the scan mode signal 301 is set to "1" through the OR gate 30. shall be. In the LSI 20, when the scan mode signal 301 becomes "1", each flip-flop (hereinafter referred to as
(abbreviated as FF) is shifted, and a shift out signal 20
The value of the FF connected to 1 is shifted out, and the switching circuit 4
0 to the diagnostic control circuit.

The diagnostic control circuit performs synchronization with the diagnostic control device and transfers shift-out data to the diagnostic control device. The number of clocks during scan mode is
By making the number similar to , all FFs are scanned out.

Next, the operation when the diagnostic control device instructs the LSI 20 to generate a pseudo fault will be described. When the diagnostic control circuit 10 outputs the false fault instruction signal 104 as “1”, O
The scan mode signal 301 is set to “1” through the R game) 30.
", and the LSI 20 executes the scan operation. However, in the case of a false fault instruction, the LSI 20 and the LSI 21
The scan mode signal 301 is suddenly turned off during processing operation.
Only Waku becomes “1”.

Therefore, only at the above clock time, each FF is updated by the scan path, unlike the expected value during processing, so each FF
A failure occurs in which the contents of the computer are destroyed. Thereafter, even if the scan mode signal becomes "0", the processing operation will not proceed normally and it can be expected that abnormal operation will start.

Scan instructions or pseudo failure instructions for LSI21 are also provided.
This can be done in the same way as above.

FIG. 2 is a diagram showing a scan path within the LSI 20.

The scan-in signal 103 shown in FIG. 1 is connected to the FF 51. Although not shown, the scan-out signal of the FF 51 is connected to the next FF.

In this way, FFs are connected one after another and FF52→FF
53→FF54→・・・・・・→Connected to FF55,
The output signal of the FF 55 is connected as a scan-out signal 201 to the diagnostic control circuit 10 via the switching circuit 40 shown in FIG.

Each FF sets the input signal when the scan mode signal 301 is “O”, and when the scan mode signal 301 is “O”, the input signal is set.
1'', scan-in data is set.

For example, for the FF 51, when the input signal is set, the data D1 is set, and when the scan-in data is set, the scan-in signal 103 is set. Regarding the FF 53, data D3 is set when the input signal is set, and when the scan-in data is set, the value of the scan-in data line 531, that is, the value of the FF 52 is set.

FIG. 3 is a time chart showing an example of operation.

At the 9th turn TO, the value "1" of the input data D2 is set in the FF 52. FF53. The value "1" of the input data D3 and the value "1" of the input data D4 are set to the FF 54, respectively. Similarly, at clock T1, FF5
2. FF53. "0", 0", 61" are set in the FF54.

FF52. FF53 has 2-bit data, and FF54 has parity pits and odd parity. In TO2T1, "1, 1.1" and "o, o, i" are set in FF52-FF54, so it is normal.

As the scan mode signal becomes "1" at clock T2, the value of input data D2-D4 becomes "1" at T2.
0,1. O'' is not set, but is set by the scan path, so the value of FF53 of T1 is “0” to FF54.
However, the FF52 value "0" of T1 is set to the FF53. The FF 54 is set to the same value as the input data D4, but the FF 53 is set to a value "0" which is different from the value "1" of the input data D3. Therefore, it appears that the value of FF53 has been destroyed.

Furthermore, regarding the FF 52, the scan input signal line 52
1, the value of the previous FF on the scan path (not shown) is set, so the value of that FF is set to “0”.
"or 1" will be set. If the value is "0", the parity of FF52-FF54 is normal, but if it is '1', the parity of FF52-FF54 is abnormal, and the parity error detection circuit 5 of FIG.
6, a parity error is detected.

In FIG. 3, the scan mode signal is set to “1” by clock T2.
”, but if the simulated failure instruction timing is a different clock, it will appear that a different failure has occurred. Therefore, the content of the simulated failure has a characteristic that it depends on the timing.

〔Effect of the invention〕

As explained above, the present invention makes it possible to generate a pseudo fault by moving the scan path and by adding a simple circuit, and it is also possible to generate a pseudo fault with random content. becomes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a block diagram showing a scan path within an LSI, and FIG. 3 is a time chart. 10...Diagnostic control circuit, 20.21...
・LSI, 30.31...OR gate, 40.
...Switching circuit, 51-55...FF, 5
6...detection circuit.

Claims (1)

[Claims] In an information processing device that includes a plurality of LSIs each having a scan path and an error detection circuit and is capable of operating the scan path independently for each LSI, a scan instruction signal instructing the LSI to operate the scan path; A pseudo-failure method characterized in that an operation of a scan path of the LSI is executed by a logical sum with a pseudo-fault instruction signal that instructs the LSI to generate a pseudo-fault.