JPH0587893A - Ordering circuit - Google Patents

Abstract

PURPOSE:To shorten the time necessary for the inspection of an ordering circuit having a scan buss. CONSTITUTION:Between flip flops 1-1 and 1-2. a two-input parity circuit 2-1 for generating the exclusive logic sum of the output signal of the flip flop 1-1 in the forestage and the output signal of a combination circuit 4 and a selector circuit 3-2 which selects the output signal of the two-input parity circuit 2-1 and outputs the output signal to the flip flop 1-2 in the posterior stage in random test mode are installed. The flip-flop 1-2 takes in the output signal of the two-input parity circuit 2-1 which is applied through a selector circuit 3-2 in synchronization with a clock signal. Such operation is carried out also in the posterior stage of the flip-flop 1-2. Accordingly, even if the scan-in operation is not carried out, each random value is set in each flip-flop 1-2-1-n and an ordering circuit can be operated, and even if the scan-out operation is not carried out, the influence of a trouble can be outputted from a scan-out terminal 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit, and more particularly to a sequential circuit having a scan path.

[0002]

2. Description of the Related Art Conventionally, when inspecting a sequential circuit having a scan path formed by flip-flops, a test pattern for a combinational circuit surrounded by scan paths is generated by an automatic test pattern generation algorithm, and the generated test pattern is generated. The following processing was performed for each. That is, the scan-in operation is performed to set the test pattern in each flip-flop forming the scan path, and the test pattern is given to the external input terminal of the combinational circuit. Then the sequential circuit 1
The clock is normally operated, the result is set in each flip-flop, and the scan-out operation is performed to read the value of each flip-flop, and the read value is compared with the expected value. The sequential circuit is inspected by performing the above processing for each test pattern.

[0003]

As described above, conventionally, since the scan-in and the scan-out are performed for all the generated test patterns, there is a problem that the inspection time becomes long.

An object of the present invention is to provide a sequential circuit that can reduce the inspection time.

[0005]

In order to achieve the above object, the present invention provides: (A) In a sequential circuit including a plurality of flip-flops forming a scan path, a flip-flop of a preceding stage is provided between the flip-flops. Select the output signal of the combination circuit when the operation mode is the normal operation mode, and the two-input parity circuit that takes the exclusive OR of the output signal of the combination circuit and the output signal of the combination circuit that becomes the input of the subsequent flip-flop. In the shift mode, the output signal of the preceding flip-flop is selected, in the random test mode, the output signal of the two-input parity circuit is selected, and a selector circuit for outputting the selected signal to the subsequent flip-flop is provided. It is a thing.

Further, according to the present invention, in order to improve the fault detection capability regarding the hold signal, (B) among the flip-flops having the hold signal, the 2-input parity circuit and the selector circuit are provided. In place of the above, a 3-input parity circuit that takes the exclusive OR of the output signal of the preceding flip-flop, the output signal of the combination circuit, and the hold signal, and the output of the combination circuit when the operation mode is the normal operation mode Signal or the output signal of the flip-flop having the hold signal, the output signal of the previous flip-flop in the shift mode, and the output signal of the 3-input parity circuit in the random test mode. And a circuit.

[0007]

In the configuration (A), the 2-input parity circuit and the selector circuit are provided between the flip-flops. The 2-input parity circuit takes the exclusive OR of the output signal of the front-stage flip-flop and the output signal of the combinational circuit which becomes the input of the rear-stage flip-flop in the normal operation mode. That is, when the influence of a fault existing in the sequential circuit propagates to either input of the 2-input parity circuit, the output signal of the 2-input parity circuit takes a value opposite to the normal value. If the operation mode is random test mode,
The selector circuit selects the output signal of the 2-input parity circuit and outputs it to the flip-flop in the subsequent stage. That is, the influence of the fault existing in the sequential circuit is sequentially propagated to the output side.

In the configuration of (B), the flip-flop having the hold signal is provided with a 3-input parity circuit instead of the 2-input parity circuit. This 3
The input parity circuit takes the exclusive OR of the hold signal, the output signal of the preceding flip-flop, and the output signal of the combinational circuit. That is, the 3-input parity circuit takes a value opposite to the normal value when any one of the above three signals is affected by the failure. When the operation mode is the random test mode, the selector circuit selects the output signal of the 3-input parity circuit and outputs it to the flip-flop in the subsequent stage.
That is, the influence of the fault existing in the sequential circuit is propagated to the output side.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The sequential circuit of this embodiment is a flip-flop (F / F).
1-1, 1-2, ..., 1-n, 2-input parity circuit (XOR) 2-1, 2-2 ,.
L) 3-1, 3-2, ..., Combination circuit 4, external input terminal 5, external output terminal 6, scan-in terminal 7,
It is composed of a scan-out terminal 8, a shift terminal 9 to which a shift control signal is applied, and a random test terminal 10 to which a random test control signal is applied.

The shift control signal and the random test signal applied to the shift terminal 9 and the random test terminal 10 are signals for controlling the operation mode of the sequential circuit. In this embodiment, when the shift control signal and the random test control signal are “1” and “0”, respectively, the operation mode is the shift mode, and when the shift control signal and the random test control signal are “0” and “1”, the random test mode is set. In the case of "0", the normal operation mode is set.

When the operation mode controlled by the shift control signal and the random test control signal is the shift mode, the selector circuit 3-1 selectively outputs the signal applied through the scan-in terminal 7 to select the normal operation mode and the random operation mode. In the test mode, the output signal 41- of the combinational circuit 4
1 is selectively output.

.. of the selector circuits 3-2, 3-3, ... When the operation mode is the shift mode
, Output signals 41-2, 41-3, ... Of the combinational circuit 4 in the normal operation mode,
2-input parity circuit in random test mode 2-
Output signals 43-1, 43-2, ... Of 1, 2, 2 ... are selectively output.

The 2-input parity circuits 2-1, 2-2, ... Are output signals 42- of the flip-flops 1-1, 1-2 ,.
, 42-2, ... and the output signal 41- of the combinational circuit 4
The exclusive OR with 2, 41-3 ,.

The flip-flops 1-1, 1-2, ... Take in the output signals of the selector circuits 3-1, 3-2, ... In synchronization with the clock signal.

FIG. 2 is a diagram showing the flow of signals in the normal operation mode, and the same parts as those in FIG. 1 represent the same symbols.

In the normal operation mode, that is, the shift terminals 9,
When both the shift control signal and the random test control signal input from the random test terminal 10 are "0", the output signals 41-1, 41-2, ... Of the combinational circuit 4 are selector circuits 3-1 and 3-2. , And are added to the flip-flops 1-1, 1-2 ,. The flip-flops 1-1, 1-2, ... Are selector circuits 3-1 and 3-.
2, output signal 41-of the combinational circuit 4 output from the ...
, 41-2, ... are taken in synchronization with the clock signal,
The value is output to the combination circuit 4 as output signals 42-1, 42-2, .... That is, the original function of the sequential circuit is realized by setting the operation mode to the normal operation mode.

FIG. 3 is a diagram showing a signal flow in the shift mode, and the same symbols as those in FIG. 1 represent the same parts.

In the shift mode, that is, the shift control signal input from the shift terminal 9 and the random test terminal 10,
When the random test control signals are "1" and "0", respectively, the selector circuit 3-1 selects the signal applied via the scan-in terminal 7, and the selector circuits 3-2 and 3-
, ... Select the output signals 42-1, 42-2, ... Of the flip-flops 1-1, 1-2 ,. The flip-flops 1-1, 1-2, ... Incorporate the output signals of the selector circuits 3-1, 3-2, ... In the preceding stage in synchronization with the clock signal, and output the values as output signals 42-1, 42. −
2, ... Are output to the combinational circuit 4 and the flip-flops 1-2, 1-3 ,. That is, by setting the operation mode to the shift mode, each flip-flop 1-
Scan-in operation for serially setting values from scan-in terminal 7 to 1, 1-2, ..., Each flip-flop 1
A scan-out operation of reading the values set in -1, 1-2, ... From the scan-out terminal 8 is realized.

FIG. 4 is a diagram showing the flow of signals in the random test mode, and the same symbols as in FIG. 1 represent the same parts.

In the random test mode, that is, the shift control signal and the random test control signal input to the shift terminal 9 and the random test terminal 10 are "0",
In the case of "1", the selector circuit 3-1 selects the output signal 41-1 of the combination circuit 4, and the selector circuits 3-2 and 3-
3, select output signals 43-1, 43-2, ... Of the 2-input parity circuits 2-1, 2-2 ,.

The flip-flop 1-1 takes in the output signal 41-1 of the combinational circuit 4 applied via the selector circuit 3-1 in synchronization with the clock signal, and outputs the output signal 4-1.
2-1 is output to the combination circuit 4 and the 2-input parity circuit 2-1. Also, flip-flops 1-2, 1-3, ...
Are selector circuits 3-2 and 3-in synchronization with the clock signal.
2-input parity circuit 2-1 which is added via 3, ...
The output signals 43-1, 43-2, ... Of 2-2, ... Are fetched and the output signals 42-2, 42-3 ,.

Here, the 2-input parity circuits 2-1 and 2-
2 ... are exclusive of the output signals 42-1 42-2 ... of the flip-flops 1-1 1, 1-2, ... In the preceding stage and the output signals 41-2 41-1 ... of the combinational circuit 4. Since a logical OR is used, if a fault exists in the sequential circuit and its influence propagates to either input of the 2-input parity circuits 2-1, 2-2, ..., 2-input parity circuit 2-1. , 2-
The output signal values of 2, ... Are opposite to the normal values. Therefore, by setting the operation mode to the random test mode, the influence of the fault existing in the sequential circuit is sequentially propagated through the flip-flops 1-1, 1-2, ... And is output from the scan-out terminal 8. ..

Next, the inspection method in this embodiment will be described.

First, the shift control signal and the random test control signal input to the shift terminal 9 and the random test terminal 10 are set to "1" and "0", respectively, to set the operation mode to the shift mode.

Then, a scan-in operation is performed to initialize each of the flip-flops 1-1 to 1-n and set the value of each of the flip-flops 1-1 to 1-n to a predetermined value. If there is an initialization function such as reset as a function of normal operation, it may be used.

Next, the shift control signal and the random test control signal applied to the shift terminal 9 and the random test terminal 10 are set to "0" and "1", respectively, to set the operation mode to the random test mode.

After that, a specific pattern is given to the external input terminal 5 to operate the sequential circuit for an appropriate number of clocks. Here, the specific pattern given to the external input terminal 5 is not a test pattern obtained using a test pattern algorithm, but an arbitrary pattern. The expected value output from the scan-out terminal 8 when the specific pattern is given to the external input terminal 5 and the sequential circuit is operated is simulated in advance.

When the sequential circuit is operated in the random test mode, the flip-flops 1-2, 1-3, ... Synchronize with the clock signal and the 2-input parity circuits 2-1 and 2-2 of the preceding stage are operated.
The output signals 43-1, 43-2, ... Of −2, ... Are fetched, and the fetched values are used as output signals 42-2, 42-3 ,.
Output to 2, 2-3, ....

Here, the flip-flops 1-2, 1-
, 3 take in the output signals 43-1, 43-2, ... of the two-input parity circuits 2-1, 2-2, ..., so that the values change considerably randomly, and the randomly changing values are combined. Given to circuit 4. In addition, when there is a failure in the sequential circuit, the effect is a 2-input parity circuit 2-
1, 2-2, ... and flip-flops 1-2, 1-3,
Is sequentially propagated to the output side via the ... And is sequentially output from the scan-out terminal 8. A failure can be detected by comparing the value output from the scan-out terminal 8 with the expected value obtained by simulation in advance.

Therefore, by operating the sequential circuit in the random test mode, various patterns are set in the respective flip-flops 1-1 to 1-n and the sequential circuit is operated without performing the scan-in operation. Can be carried out. Further, by operating the sequential circuit in the random test mode, the effect of the failure can be output from the scan-out terminal 8 without performing the scan-out operation. Therefore, the time required for the inspection can be shortened.

Finally, although a fault that is difficult to detect remains, a test pattern is generated by using an automatic test pattern generation algorithm using a scan path, and inspection is performed. Compared with the case where the test pattern is generated from the beginning by the automatic test pattern generation algorithm, the target failure is significantly reduced, so that the number of test patterns can be reduced and the inspection time can be reduced.

FIG. 5 is a block diagram of another embodiment of the present invention, in which the present invention is applied to the sequential circuit shown in FIG.

The sequential circuit shown in FIG. 6 is a hold signal 62-1, 62-2, ... Which is one of the output signals of the combinational circuit 55.
Selector circuits 53-1 and 53-2 controlled by
It has ...

The selector circuits 53-1, 53-2, ... Output signals 63 of the flip-flops 51-1, 51-2, ... When the hold signals 62-1, 62-2 ,.
The same flip-flop 5 is selected by selecting -1, 63-2, ...
By inputting the signals to 1-1, 51-2, ..., Even if a clock signal is input, the flip-flops 51-1, 51-2,
Hold so that the value of ... does not change. Further, when the hold signals 62-1, 62-2, ... Are “0”, the output signals 64-1, 64-2 ,.
The flip-flops 51-1, 51-2, ...

The sequential circuit of FIG. 6 has an external input terminal 56.
An external output terminal 57, a scan-in terminal 58, a scan-out terminal 59, a shift terminal 60 to which a shift control signal is input, and selector circuits 53-1 and 53- when the shift control signal is "0". Selector circuits 65-1, 65-2, ... Which select the output signals of 2, ..., And select the other signal in the case of “1”.

In the sequential circuit of FIG. 5 in which the present invention is applied to the sequential circuit of FIG. 6, a 2-input parity circuit 52 and a selector circuit 54-2 are provided between a flip-flop 51-1 and a flip-flop 51-2. It is provided. The same reference numerals as in FIG. 6 represent the same parts.

The 2-input parity circuit 52 includes an output signal 63-1 of the flip-flop 51-1 and a selector circuit 53-2.
XOR with the output signal of. Selector circuit 54
-2 is the output of the flip-flop 51-1 when the shift control signal applied to the output terminal 60 and the random test terminal 61 and the random test control signal are "1" and "0" (when the operation mode is the shift mode) Signal 63-
2-input parity circuit 5 when 1 is selected and is "0" or "1" (when the operation mode is the random test mode)
When the output signals of 2 are selected and both are “0” (when the operation mode is the normal operation mode), the selector circuit 53-2
Select the output signal of. The flip-flop 51-2
The configuration between the flip-flops in the subsequent stage is similar to that between the flip-flops 51-1 and 51-2.

Therefore, also in this embodiment, by operating the sequential circuit in the random test mode, various patterns are set in the flip-flops 51-1 to 51-n to operate the sequential circuit. This can be performed without performing the in operation, and the effect of the failure can be output from the scan out terminal 59 without performing the scan out operation.

FIG. 7 is a block diagram of still another embodiment in which the present invention is applied to the sequential circuit of FIG.

The sequential circuit of FIG. 7 has a flip-flop 51-
A 3-input parity circuit 66 and a selector circuit 65-2 are provided between 1 and the flip-flop 52-2. The same reference numerals as in FIG. 6 represent the same parts.

The 3-input parity circuit 66 takes the exclusive OR of the output signal 63-1 of the flip-flop 51-1, the output signal 64-2 of the combinational circuit 55 and the hold signal 62-2. The selector circuit 65-2 includes a shift terminal 60,
A shift control signal input to the random test terminal 61,
When the random test signals are "1" and "0" (when the operation mode is the shift mode), the output signal 63-1 of the flip-flop 51-1 is selected, and "0",
When it is "1" (when the operation mode is the random test mode), the output signal of the 3-input parity circuit 66 is selected, and when both are "0" (when the operation mode is the normal operation mode), the selector circuit 53 is selected. -2 output signal is selected.

When the embodiment of FIG. 7 and the embodiment of FIG. 5 are compared, the sequential circuit of FIG. 7 has a 2-input parity circuit 52 of FIG.
Has been replaced by the 3-input parity circuit 66,
Although the gate amount is slightly increased, the hold signal 62-2 is also input to the 3-input parity circuit 66, so that the failure detection capability for the hold signal is improved.

It should be noted that, as shown in FIG. 6, a sequential circuit including a flip-flop having a hold signal is used as compared with the sequential circuit shown in FIG.
Whether the embodiment shown in FIG. 7 or the embodiment shown in FIG. 7 is applied may be selected based on the gate amount margin, the failure detection rate, the distribution of undetected failures, and the like. ..

[0045]

As described above, according to the present invention, the two-input parity that takes the exclusive OR of the output signal of the preceding flip-flop and the output signal of the combinational circuit is provided between the flip-flops forming the scan path. With the circuit
In the random test mode, a selector circuit for selecting the output signal of the 2-input parity circuit and outputting it to the flip-flop in the subsequent stage is provided. Therefore, by operating the sequential circuit in the random test mode, various patterns can be obtained. Setting a flip-flop to operate a sequential circuit can be realized without performing a scan-in operation, and outputting the effect of a failure from a scan-out terminal can be realized without performing a scan-out operation. it can. Therefore, according to the present invention, there is an effect that the inspection time can be significantly shortened.

Further, according to the present invention, for a flip-flop having a hold signal, a three-input parity circuit which takes an exclusive OR of the hold signal, the output signal of the combinational circuit and the output signal of the preceding flip-flop. Is provided, there is an effect that the failure detection capability regarding the hold signal can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a signal flow in a normal operation mode of FIG.

FIG. 3 is a diagram showing a signal flow in a shift mode of FIG.

FIG. 4 is a diagram showing a signal flow in the random test mode of FIG.

FIG. 5 is a block diagram of another embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a sequential circuit including a flip-flop having a hold signal.

FIG. 7 is a block diagram of another embodiment of the present invention.

[Explanation of symbols]

 1-1 to 1-n; Flip-flops 2-1, 2-2, ...; 2-input parity circuit 3-1, 3-2, ...; Selector circuit 4; Combination circuit 5; External input terminal 6; External output terminal 7; Scan-in terminal 8; Scan-out terminal 9; Shift terminal 10; Random test terminals 51-1 to 51-n; Flip-flop 52; 2-input parity circuit 53-1, 53-2, ...; Selector circuit 54-1 , 54-2, ...; Selector circuit 55; Combination circuit 56; External input terminal 57; External output terminal 58; Scan-in terminal 59; Scan-out terminal 60; Shift terminal 61; Random test terminal 65-1, 65-2, ...; Selector circuit 66; 3-input parity circuit

Claims (3)

[Claims] 1. A sequential circuit including a plurality of flip-flops forming a scan path, wherein between the respective flip-flops, there is provided a combinational circuit which is an output signal of the front-stage flip-flop and an input of the rear-stage flip-flop. A 2-input parity circuit that takes the exclusive OR with the output signal, and the output signal of the combinational circuit when the operation mode is the normal operation mode, and the output signal of the flip-flop of the previous stage when the shift mode is selected, A sequential circuit comprising a selector circuit which selects an output signal of a 2-input parity circuit in the random test mode and outputs the selected signal to a subsequent flip-flop. 2. Among the flip-flops, for the flip-flop having a hold signal, instead of the 2-input parity circuit and the selector circuit, the output signal of the preceding flip-flop and the output signal of the combinational circuit And the exclusive OR with the hold signal 3
Input parity circuit, when the operation mode is the normal operation mode, the output signal of the combination circuit or the output signal of the flip-flop having the hold signal is selected, and in the shift mode, the output signal of the preceding flip-flop is selected, The sequential circuit according to claim 1, further comprising a selector circuit that selects an output signal of the 3-input parity circuit in the random test mode. 3. The selector circuit, in a normal operation mode,
3. The sequential circuit according to claim 2, wherein the output signal of the flip-flop having the hold signal is selected when the hold signal is valid, and the output signal of the combination circuit is selected when the hold signal is invalid.