JPS62249084A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit which does not require many test vectors at the time of a test, by bringing a random data to an internal generation by a flip-flop circuit having a random data generation mode. CONSTITUTION:A scan clock SCK is supplied to a clock input terminal 3, it is set to a scan mode, and a test data is inputted to a terminal 5, and transferred to flip-flops (FF) F1-Fn. When a random data generating clock GCK is supplied to a terminal 4, it becomes a random data generation mode. After the GCK is supplied by a necessary number of times, the terminal is set to a scan mode, and the data of the FF is led out of an output terminal. In accordance with whether its data has coincided with an expected value or not, whether an LSI is good or not is decided.

Description

[Detailed description of the invention] [Industrial application field] TECHNICAL FIELD This invention relates to an integrated circuit with testing functionality.

[Summary of the invention]

The present invention provides an integrated circuit configured with a combination of a flip-flop and a gate circuit, in which the flip-flop includes a first gate circuit controlled by a clock in a first mode, and a first gate circuit controlled by a clock in a second mode. a second gate circuit controlled by a clock in a third mode; a third gate circuit controlled by a clock in a third mode; an inverter circuit connected to the other ends of the second and third gate circuits; The fourth mode is controlled by cross cutting in the second and third modes. a series circuit of fifth and sixth gate circuits;
and a second inverter circuit connected to this series circuit, the first gate circuit is supplied with data from the first input terminal, and the second gate circuit is supplied with data from the second input terminal. The third gate circuit is supplied with data obtained by adding modulo 2 the data from the first and second input terminals, and a flip-flop output is obtained from the second inverter circuit. This allows for internal generation of random patterns during testing, improves observability and controllability, and facilitates operational testing.

[Conventional technology]

Digital circuits are basically composed of flip-flops and combinational gate circuits.

In LSI (Large Scale Integrated Circuits), when the circuit scale becomes very large, the number of flip-flops and combinational gate circuits placed on the same chip becomes very large, and therefore tests are required to determine the quality of the circuits. It becomes difficult.

Conventionally, LSI testing involves giving a test pattern to the LSI.
The internal state of the LSI is set, and the output pattern of the LSI is compared with an expected value to determine whether it is good or bad. It is easy to arbitrarily set the state of internal logic in an LSI that is close to the input terminal into which a test pattern is input in terms of signals, but it is difficult to output the result. In other words, controllability is good, but observability is poor. On the other hand, although it is easy to observe the output of a portion signal-wise close to the output terminal, it is difficult to arbitrarily set the internal logic. That is, the observation ability is good, but the control ability is not good.

Therefore, a scanvase test method has been proposed as a method for efficiently testing LSIs. In the scan path test method, a test mode is provided as an operation mode of the LSI, separate from the normal mode. In the test mode, a flip-flop in the LSI functions as a shift register.

As a result, data is serially transferred to each flip-flop by busing the gate circuit, and each flip-flop can be set to an arbitrary state. Furthermore, the output of each flip-flop is transferred through the gate circuit bus in test mode and can be taken out from the output terminal. That is, in the scan path test method, control ability is improved as well as observation ability is improved.

This scan path testing method is easy to automate because test steps can be established. Also, since both control ability and observation ability are improved, L
It is possible to perform not only a fault detection test to determine whether the SI is good or bad, but also a fault location test to determine in which part of the LSI a failure has occurred.

[Problem that the invention seeks to solve]

By the way, as mentioned above, the LS
When performing an operation test of I, 2fi test vectors are required to test an n-input combinational gate circuit. For this reason, as the circuit scale increases, a large number of test vectors are required for performing operational tests.

A method is known in which a random pattern is generated and an operation test is performed using this random pattern. This test method using random patterns can perform operational tests without using many test vectors. However,
Conventional testing methods using random patterns cannot perform highly accurate tests on areas with poor controllability.

Therefore, an object of the present invention is to provide an integrated circuit that can perform highly accurate operational tests without using many test vectors.

[Means for solving problems]

The present invention provides an integrated circuit constituted by a combination of a flip-flop and a gate circuit, in which the flip-flop is in a first mode controlled by a clock.
a second gate circuit 15 controlled by a clock in the second mode, and a third gate circuit 1 controlled by a clock in the third mode.
G and 1st. an inverter circuit 13 connected to the other ends of the second and third gate circuits; The fourth .controlled by the clock in the second and third modes. Fifth and sixth gate circuit 2
It has a series circuit of 0.21.22 and a second inverter circuit 23 connected to this series circuit, and data from the first input terminal 10 is supplied to the first gate circuit 14.
The data from the second input terminal 11 is supplied to the second gate circuit 15, and the data obtained by adding the data from the first and second input terminals 10.11 modulo 2 is supplied to the third gate circuit 16. This is an integrated circuit configured to receive a flip-flop output from the second inverter circuit 23.

[Effect]

Digital integrated circuits are constructed from a combination of flip-flops and gate circuits. The flip-flops arranged in this integrated circuit can be set to three modes. The first mode is a normal mode in which the flip-flop operates as a flip-flop for a combinational gate circuit. The second mode is a scan mode, in which the flip-flop functions as a shift register.

The third mode is a random data generation mode, in which random data is generated.

When performing an operation test, after setting the state of the flip-flop in scan mode, random data is generated in random data generation mode, and the set data is scanned out in scan mode and compared with the expected value. Since random data can be generated internally, a large number of test vectors are not required.

In the random data generation mode, this flip-flop is configured such that the modulo 2 addition data of the data input terminal 1 and the data input terminal TD is taken into the flip-flop. In the random data generation mode, the outputs of all flip-flops on the integrated circuit are fed into the combinational gate circuit. Then, modulo 2 addition data of the output of another flip-flop and the combinational gate circuit is taken into the flip-flop.

This generates random data.

〔Example〕

An embodiment of the present invention will be described in the following order.

a. Overall configuration, an example of a flip-flop C, another example of a flip-flop d, operation of one embodiment e, operation test in one embodiment C1 application example a, overall configuration A digital circuit is basically a combinational gate It consists of a circuit and a flip-flop. In Figure 1,
G (1,1) ~G (1,n) and G (2,1)
~G (2, n) is a combinational gate circuit arranged on the LSI, and F1 to Fn are flip-flops arranged on the LSI.

As shown in FIG. 2, these flip-flops F1 to Fn have two data input terminals RI and TD, three clock input terminals NC, TCI, and TC2, and one output terminal Q.
It has A combinational gate circuit G (1,1) is connected to the data input terminals of flip-flops F1 to Fn.
~G (1,n) outputs are supplied, respectively. The data input terminal TD of the flip-flop Fl is supplied with the output of the multiplexer M1, the data input terminal TD of the flip-flop F2 is supplied with the output of the flip-flop F1, and the data input terminal of the flip-flop Fn is supplied with the data input terminal TD of the flip-flop F2. T
D is supplied with the output of another flip-flop. A system clock CKI is supplied from the clock input terminal 1 to the clock input terminals NC of the flip-flops Fl and F2. Clock input terminal N of flip-flop Fn
System clock CK is input to C from clock input terminal 2.
2 is supplied. A scan clock SCK is supplied from the input terminal 3 to the clock input terminals TCI of the flip-flops F1 to Fn. A random data generation clock GCK is supplied from the clock input terminal 4 to the clock input terminals TC2 of the flip-flops F1 to Fn. The output terminals Q of the flip-flops F1 to Fn are supplied to the combinational gate circuits G(2,1) to G(2,n), respectively, and the output of the output terminal Q of the flip-flop 1F1 is the data input of the flip-flop F2. The output of the output terminal Q of the flip-flop F2 is supplied to the data input terminal TD of another flip-flop, and the output of the output terminal Q of the flip-flop Fn is supplied to one input terminal 7C of the multiplexer M1. Ru.

The other input terminal 7B of multiplexer M1 has terminal 5.
Data is supplied from A select signal is supplied from the terminal 6 to the multiplexer Ml.

Three modes can be set for these flip-flops F1 to Fn. The first mode is normal mode. In normal mode, clock input terminal N
The system clock is supplied to C, and the clock input terminal T
A high level is supplied to CI and TC2. In normal mode, flip-flops F1 to Fn operate as flip-flops for data supplied to the data input terminals.

The second mode is scan mode. The scan mode is used when the flip-flops F1 to Fn operate as shift registers.

In the scan mode, the scan clock is supplied to the clock input terminal TCI, and the clock input terminals NC and TC2
A high level is supplied to the In scan mode, flip-flops F1 to Fn operate as flip-flops for data supplied to data input terminal TD.

The third mode is a random data generation mode. In the random data generation mode, the clock input terminal TC2
A random data generation clock GCK is supplied to the clock terminals NC and TC2, and a high level is supplied to the clock terminals NC and TC2.

In the random data generation mode, the modulo 2 addition data of the data supplied to the data input terminal RI and the data supplied to the data input terminal TD is added to the flip-flop F1.
~Incorporated into Fn.

b. An example of a flip-flop The flip-flops F1 to Fn are constructed as shown in FIGS. 3 and 7.

FIG. 3 shows a dynamic type configuration.

In FIG. 3, a MOS transistor 14 is connected between the input terminal 10 and the input terminal of the inverter 13, and a MOS transistor 15 is connected between the input terminal 11 and the input terminal of the inverter 13.

Furthermore, input terminals 10 and 11 are connected to one and the other input terminals of EX-OR gate 12, and M
O3I-transistor 16 is connected. The gate of the MOS) transistor 14 is connected to the clock input terminal 17,
MOS) The gate of transistor 15 is clock terminal 1
8 and the gate of the MO3I transistor 16 is connected to the clock input terminal 19.

The output terminal of inverter 13 is MO3I - transistor 20
, 21, 22 are connected to the input terminal of the inverter 23 through a series connection. MOS) transistor 20, 21.2
The gates of 2 are connected to clock input terminals 24, 25, and 26, respectively. The output terminal of the inverter 23 is the output terminal 27
connected to.

Input terminals 10 and 11 correspond to the input terminals 1 and TD of the flip-flops F1xFn in FIG. 1, respectively. The output terminal 27 corresponds to the output terminal Q of the flip flora 7'F1 to Fn.

The clock input terminals I7 and 26 are supplied with system clocks GK and GK7 having opposite phases to each other.
It corresponds to the clock input terminal NC of. Scan clocks SCK and SCK having mutually opposite phases are supplied to the clock input terminals 18 and 24, and the clock input terminal 1
8 and 24 correspond to clock input terminals TCI of flip-flops F1 to Fn. Clock input terminal 19
and 25 are supplied with random data generation clocks GCK and GCK having mutually opposite phases, and the clock input terminals 19 and 25 correspond to the clock input terminal TC2 of the flip-flops Fl-Fn.

In the first mode used during normal operation, as shown in FIGS. 4B and 4C, the scan clock SCK
and random data generation clock GCK are maintained at high level, low level is supplied to clock input terminals 18 and 19, and high level is supplied to clock input terminals 24 and 25.

In this state, as shown in FIG. 4A, the system clock CK is supplied to the clock input terminal 26, and the inverted clock X is supplied to the clock input terminal 17.

Since the clock input terminals 18 and 19 are supplied with a low level, the MOS transistors 15 and 16 are maintained in the off state. Furthermore, since a high level is supplied to the clock input terminals 24 and 25, the MO3I-transistors 20 and 21 are maintained in the on state. When the clock CK supplied to the clock input terminal 17 becomes high level, the MOS transistor 14 is turned on, the data from the input terminal 10 is supplied to the inverter 13 via the MOS transistor 14, and the output of the inverter 13 is transferred to the MOS transistor 22. can be stored in a capacity of When the clock CK becomes high level, the MO3I-ranji disk 22 is turned on and the M
OS) The output stored in the capacitor of the transistor 22 is taken out from the output terminal 27 via the inverter 23.

Therefore, in this way, the clock input terminals 18 and 1
9 and clock input terminals 24 and 2.
5 and clock input terminals 26 and 1.
When X is supplied to the system clock CK and its inverted clock to the input terminals 11, data DO1Di, D2. ... (Figure 4 D
) is taken out from the output terminal 27 with a delay of one clock.

The second case when operating as a shift register during testing
In this mode, as shown in FIGS. 5A and 5C, the system clock CK and the random data generation clock G are
CK is maintained at high level, low level is supplied to clock input terminals 17 and 19, and clock input terminal 25
and 26 are supplied with a high level. In this state, as shown in FIG. 5B, the clock input terminals 24 and 1
8, the scan clock SCK and its inverted clock S
CK is supplied.

Since a low level is supplied to clock input terminals 17 and 19, MOS transistors 14 and 16 are maintained in an off state. Since the clock input terminals 25 and 26 are supplied with a high level, the MO5I-transistor 2
1 and 22 are kept on. When the scan clock signal supplied to the clock input terminal 18 goes high, MO3! - The transistor 15 is turned on, and the test data from the input terminal 11 is supplied to the inverter 13 via the MO5I transistor 15, and the inverter 1
The output of 3 is stored in the capacitance of a MOS transistor 20. When the clock supplied to the clock input terminal 24 rises to a high level, the MOS transistor 20 turns on, and MO5! - The output stored in the capacitor of the transistor 20 is taken out from the output terminal 27 via the inverter 23.

Therefore, in this way, the clock input terminals 17 and 1
9 and clock input terminals 25 and 2.
6 is supplied with a high level, and the scan clock SCK and its inverted clock S are supplied to the clock input terminals 24 and 18.
'CK is supplied, data TDO, TDL, TD2 . ...
(FIG. 5D) is taken out from the output terminal 27 with a delay of one clock.

In the third mode when generating random data,
As shown in FIGS. 6A and 6B, the system clock CK and scan clock SCK are maintained at high level, low level is supplied to clock input terminals 17 and 18, and high level is supplied to clock input terminals 24 and 26. is supplied. In this state, as shown in Figure 6C,
A random data generation clock GCK and its inverted clock GCK are supplied to clock input terminals 25 and 19.

Since low level is supplied to clock input terminals 17 and 18, MO3! - transistors 14 and 15 are kept off; Furthermore, since the high level is supplied to the MOS transistors 24 and 26, the MoS transistors 20 and 22 are maintained in the on state. When the random data generation clock GCK becomes high level, the MOS
) 6M0S transistor 16 that transistor 16 turns on
When ON, the output of IIIEX-OR gate 12 becomes M
It is supplied to the input terminal of the inverter 13 via the OS transistor 16, and the output of the inverter 13 is stored in the capacitor of the MOS transistor 21.

When the random data generation clock GCK rises to high level, the MO3I transistor 21 turns on, and the MO3
The output stored in the I-transistor 21 is taken out from the output terminal 27 via the inverter 23.

Therefore, in this way, the clock input terminals 17 and 1
8 and clock input terminals 24 and 2.
6 and clock input terminals 25 and 1.
When the random data generation clock GCK and its inverted clock GCK are supplied to the input terminals 10 and 9, as shown in FIG. 6F, the data DO, DI, D2 . ...
(Fig. 6D) and data TDO, T from input terminal 11
D.I.

TD2. ... (FIG. 6E) modulo 2 addition data is taken out from the output terminal 27 with a delay of one clock.

C. Other examples of flip-flops FIG. 7 shows a static type configuration.

In FIG. 7, a MOS transistor 34 is connected between the input terminal 30 and the input terminal of the inverter 33, and a MO3I-
A transistor 35 is connected.

Further, input terminals 30 and 31 are connected to one and the other input terminals of EX-OR gate 32, and M
OS transistor 36 is connected. The gate of the transistor 34 (MOS) is connected to the clock input terminal 37,
O3! -The gate of transistor 35 is clock input terminal 3
8, and the gate of the MOS transistor 36 is connected to the clock input terminal 39.

MOS+- in which the output terminals of the inverter 33 are connected in series
It is connected to an input terminal of an inverter 43 via transistors 40, 41, and 42, and is also connected to an input terminal of an inverter 47. The gate of the MOS transistor 40 is connected to the clock input terminal 44, the gate of the MO3I-transistor 41 is connected to the clock input terminal 45, and the MO3I-transistor 41 has a gate connected to the clock input terminal 45.
3I--gate of transistor 42 is clock input terminal 46
connected to.

The output terminal of the inverter 47 is a MOS) transistor 48,
It is connected to the input terminal of the inverter 33 via a series connection of 49.50. The gate of the MOS) transistor 48 is connected to the clock input terminal 51. The gate of the MOS) transistor 49 is connected to the clock input terminal 52. M
The gate of the OS transistor 50 is the clock input terminal 53
connected to.

An output terminal of inverter 43 is connected to output terminal 54 and is also connected to an input terminal of inverter 55 . The output terminal of the inverter 55 is connected to the input terminal of the inverter 43 via parallel-connected MOS transistors 56, 57, and 58.

The gate of the MOS transistor 56 is the clock input terminal 6
Connected to 0. The gate of the MOS transistor 57 is connected to the clock input terminal 61.

MOS) The gate of the transistor 58 is the clock input terminal 6.
Connected to 2.

Input terminals 30 and 31 correspond to the input terminals of flip-flops F1 to Fn and TD in FIG.

The output terminal 54 corresponds to the output terminal Q of the flip-flop blocks F1 to Fn.

The system clock C is connected to the clock input terminals 53 and 46.
K is supplied, and its inverted clock CK is supplied to clock input terminals 37 and 60. These clock input terminals 53, 46 and 37, 60 are connected to the flip-flop F
It corresponds to the clock input terminals NC of 1 to Fn. The clock input terminals 52 and 44 have a scan clock SC.
K is supplied, and its inverted clock SCK is supplied to clock input terminals 38 and 61. These clock input terminals 52.44 and 38.61 correspond to the clock input terminals TCI of flip-flops F1 to Fn.

A random data generation clock GCK is supplied to clock input terminals 5 and 45, and an inverted clock GCK thereof is supplied to clock input terminals 39 and 62. These clock input terminals 51.45 and 39.62 correspond to the clock input terminals TC2 of the flip-flops F1 to Fn.

In the first mode used during normal operation, a low level is supplied to the clock input terminals 38.39 and 61.62, and a high level is supplied to the clock input terminals 51, 52 and 44.45. In this state, the system clock CK is supplied to the clock input terminal 53.46, and its inverted clock -σ is supplied to the input terminal 37.60.
Balls are supplied.

Since a low level is supplied to clock input terminals 38.39 and 61.62, MO3I-transistors 35 and 3
6 and 57.58 are kept off. Since a high level is supplied to clock input terminals 51, 52 and 44.degree. 45, MOS transistors 48.49 and 40.
41 is maintained in the on state.

When the system clock CK goes low and the system clock CK goes high, the MOS transistor 34 is turned off and the MOS transistor 50 is turned on. Therefore, when the system clock CK falls and the system clock CK rises, data from the input terminal 30 is supplied to the inverter 33 via the MOS transistor 34, and while the system clock CK is at a high level, the output of the inverter 33 is is the inverter 47. It is fed back to the input terminal of the inverter 33 via the MO3I transistors 48, 49, 50. Therefore, data from the input terminal 30 is held in this loop while the system clock CK is at a high level.

Furthermore, while the system clock CK is at a high level, the output of the inverter 33 is output from the MOS transistor 40°41.42.
is supplied to the inverter 43 via.

When the system clock CK goes low and the system clock CK goes high, the MOS transistor 42 is turned off and the MOS transistor 56 is turned on. Therefore, when the system clock CK falls and the system clock CK rises, the output of the inverter 33 becomes MO
3I - is supplied to the input terminal of the inverter 43 through the transistors 40, 41, and 42, and while T is at a high level in the system clock, the output of the inverter 43 is supplied to the inverter 55.
, are fed back to the input terminal of the inverter 43 via the MOS transistor 56. Therefore, the system clock C
While K is at high level, the output data of inverter 33 is held in this loop.

The second case when operating as a shift register during testing
In this mode, the clock input terminals 37, 39 and 60.
A low level is supplied to clock input terminals 51 .
A high level is supplied to 53 and 45.46. In this state, the scan clock SCK is supplied to the clock input terminal 52.44, and the clock input terminal 38.61
The inverted clock SCK is supplied to the inverted clock SCK.

Since a low level is supplied to the clock input terminals 37.39 and 60.62, the MOS transistors 34.36
and 56.58 are kept off. Since a high level is supplied to the clock input terminals 51.53 and 45°46, the MOS transistors 48.50 and 41.4
2 remains on.

When the scan clock SCK goes low and the scan clock SCK goes high, the MOS transistor 35 is turned off and the MOS transistor 49 is turned on. Therefore, when the scan clock SCK falls and the scan clock SCK rises, data from the input terminal 31 is transferred to the inverter 3 via the MOS transistor 35.
3, and while the scan clock SCK is at high level, the output of the inverter 33 is fed back to the input terminal of the inverter 33 via the inverter 479M0S transistors 48, 49.50. Therefore, data from input terminal 31 is held in this loop while system clock SCK is at high level.

Furthermore, while the scan clock SCK is at a high level, the output of the inverter 33 is output from the MOS transistors 40, 41, 4.
2 to the inverter 43. When the scan clock SCK goes low and the scan clock m goes high, the MOS transistor 40 is turned off and the MOS transistor 57 is turned on. Therefore, the scan clock SCK falls and the scan clock SC
When K rises, the output of inverter 33 is supplied to the input terminal of inverter 43 via MOS transistors 40, 41, 42, and while scan clock SCK is at high level, the output of inverter 43 is supplied to inverter 55. M.O.S.
It is fed back to the input terminal of the inverter 43 via the transistor 56.

Therefore, while the scan clock SCK is at a high level, the output data of the inverter 33 is held in this loop.

In the third mode when generating random data,
A low level is supplied to clock input terminals 37.38 and 60.61, and clock input terminals 52.53 and 44.
46 is supplied with a high level. In this state, the random data generation clock GCK is supplied to the clock input terminals 51.45, and its inverted clock GCK is supplied to the clock input terminals 39.62.

Since a low level is supplied to the clock input terminals 37.38 and 60.61, the MOS) transistors 34, 35
and 56.57 are kept off. Since a high level is supplied to the clock input terminals 52, 53 and 44° 46, the MOS) transistors 49, 50 and 40.4
2 remains on.

When the random data generation clock m goes low and the random data generation clock GCK goes high, the MOS) transistor 36 is turned off and the MOS) transistor 48 is turned on. Therefore, the random data generation clock GCK falls, and the random data generation clock GCK falls.
When CK rises, the output of EX-OR gate 32 becomes MO.
The output of the inverter 33 is supplied to the inverter 33 via the S transistor 36, and while the random data generation clock GCK is at a high level, the output of the inverter 33 is supplied to the inverter 47, MO3I-
It is fed back to the input terminal of the inverter 33 via transistors 4B and 49.50. Therefore, while the random data generation clock GCK is at a high level, the output data of the EX-OR gate 32 is held in this loop.

Further, while the random data generation clock GCK is at a high level, the output of the inverter 33 is output to the MOS transistor 40.
, 41, 42 to the inverter 43. Random data generation clock GCK becomes low level,
When the random data generation clock GCK becomes high level, the MOS transistor 41 is turned off and the MOS transistor 58 is turned on. Therefore, when the random data generation clock GCK falls and the random data generation clock GCK rises, the output of the inverter 33 passes through the MOS transistors 40, 41, and 42 to the impark 430.
Random data generation clock GC is supplied to the input terminal.
While K is at a high level, the output of inverter 43 is output to inverter 55. Inverter 4 via MOS transistor 58
It is fed back to the input terminal of No. 3. Therefore, while random data is generated and r is at a high level, inverter 3
3 output data is held in this loop.

d. Operation of an Embodiment As mentioned above, when the flip-flops F1 to Fn supply the system clock CK to the clock input terminal NG,
It operates as a D flip-flop knob for the data supplied to the data input terminal, and when a scan clock SCK is supplied to the clock input terminal TC1, it operates as a D flip-flop knob for the data input terminal TD. Data generation clock GC
When K is supplied, the data supplied to the data input terminal and the data supplied to the data input terminal TD are added modulo 2, and the output of this addition is output with a delay of one clock.

In FIG. 1, during normal operation, system clocks CKI and CK2 are supplied to clock input terminal 1 and clock input terminal 2, and high level is supplied to clock input terminals 3 and 4.

Therefore, the system clock CKI or CK2 is supplied to the clock input terminal NC of the flip-flop F1xFn, and the combinational gate circuits G(1°l) to G(1,n)
The outputs of are supplied to flip-flops F1 to Fn, respectively. The outputs of flip-flops F1 to Fn are supplied to combinational gate circuits G(2°1) to G(2,n), respectively.

In this way, during normal operation, the flip-flop F
l to Fn are combinational gate circuits G(1,1) to G(1
, n).

When transferring data during a test, a scan clock SCK is supplied to the clock input terminal 3, and a high level is supplied to the clock input terminals 1, 2.4. Terminals 7A and 7B of multiplexer M1 are then connected.

Therefore, the scan clock SCK is supplied to the clock input terminals TCI of the flip-flops F1 to Fn. The data input terminal TD of the flip-flop F1 is supplied with the data from the terminal 5, the data input terminal TD of the flip-flop F2 is supplied with the output of the flip-flop F1, and the data input terminal TD of the flip-flop Fn is supplied with the data from the terminal 5. The output of the flip-flop is provided. Therefore, at this time, the flip-flops F1 to Fn operate as a shift register, and data from the terminal 5 is transferred to the flip-flops F1 to Fn.

When random data is generated during testing, a random data generation clock GCK is supplied to the clock input terminal 4, and a high level is supplied to the clock input terminals 1, 2 and 3. Terminals 7A and 7C of multiplexer Ml are then connected.

Therefore, the random data generation clock GCK is supplied to the clock input terminal TC2 of the flip-flop F1xFn. When the random data generation clock GCK is supplied to the clock input terminal TC2, the data supplied to the data input terminal TD and the data supplied to the data input terminal TD are added modulo 2, and the output of this addition is sent to the flip-flop. It is taken into F1 to Fn. The outputs of the combinational gate circuits G (1,1) to G (1,n) are supplied to the data input terminals of the flip-flops F l =F n, respectively. These combinational gate circuits G
The outputs of (1,1) to G (1,n) are determined by their inputs, and the combinational gate circuit G(1,1)
~G (1,n) is supplied with the output of another flip-flop. The data input terminal TD of the flip-flop F2 is supplied with the output of the flip-flop Fl, the data input terminal TD of the flip-flop Fn is supplied with the output of another flip-flop, and the data input terminal TD of the flip-flop Fn is supplied with the output of the other flip-flop.
The output of the flip-flop Fn is supplied to the data input terminal TD of No. 1 via the multiplexer M1. That is, the outputs of all the flip-flops are input to the combinational gate circuit, and the output of the combinational gate circuit is added modulo 2 to the output of a certain flip-flop, and then taken into the flip-flop. Therefore, at this time, a random pattern is generated.

e. Operational Test of One Embodiment The operational test of one embodiment of the present invention is carried out as follows.

First, the scan clock SCK is supplied to the clock input terminal 3, the terminals 7A and 7B of the multiplexer M1 are connected, and test data is input to the terminal 5 to set the scan mode. This test data is for flip-flops F1 to F
n, and flip-flops F1 to Fn are set to arbitrary states.

Next, the terminals 7A and 7C of the multiplexer M1 are connected, the random data generation clock GCK is supplied to the clock input terminal 4, and the random data generation mode is set. As a result, a random pattern is generated.

After the random data generation clock GCK is supplied the required number of times, the scan mode is set and the data set in the flip-flop is derived from the output terminal. This data is compared with a previously determined expected value. Passage or failure is determined by determining whether this data matches the expected value.

Of course, with this LSI, if a large number of test vectors can be prepared, the operation test can be performed in the same manner as the conventional scan path test method using the scan mode without using the random data generation mode.

Further, after determining pass/fail using the random data generation mode, the fault location may be inspected using the scan path test method.

f. Application Example Note that if an LSI capable of performing a scan path is configured as described above, a wiring area for performing the scan path is required, which increases the chip area. Therefore, the LSI has a three-layer structure, and the third layer is used for wiring the scan path.

Thereby, increase in chip area can be suppressed.

〔Effect of the invention〕

According to this invention, flip-flops arranged in an LSI can be set to scan mode and random data generation mode in addition to normal mode.

In the random data generation mode, data obtained by adding modulo 2 data from two input terminals is taken into a flip-flop, and random data is internally generated.

Therefore, an operation test can be performed without using a large number of test vectors. By setting the scan mode, the flip-flop can be set to any desired state and the output of each part can be observed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention, FIG. 2 is a block diagram of the basic configuration of a flip-flop in an embodiment of the invention, and FIG. 3 is an example of a flip-flop in an embodiment of the invention. Connection diagrams, FIGS. 4 to 6 are time charts used to explain an example of a flip-flop in an embodiment of this invention, and FIG. 7 is a connection diagram of another example of a flip-flop in an embodiment of this invention. be. Explanation of main symbols in the drawings Fl to Fn: flip-flops, G(1,1) to G
(1, n), G (2, 1) to G (2, n): combinational gate circuit, 1, 2. 3, 4: clock input terminal, 12, 32: EX-OR gate. Agent Patent Attorney Tadashi Sugiura Tomo To Ac

Claims (1)

[Claims] In an integrated circuit configured by a combination of a flip-flop and a gate circuit, the flip-flop has a first gate circuit controlled by a clock in a first mode, and a first gate circuit controlled by a clock in a second mode. a second gate circuit controlled by a clock; and a third gate circuit controlled by a clock in a third mode.
an inverter circuit connected to the other ends of the first, second, and third gate circuits; and an inverter circuit connected to the inverter circuit and controlled by a clock in the first, second, and third modes, respectively. a series circuit of fourth, fifth, and sixth gate circuits, and a second gate circuit connected to this series circuit.
an inverter circuit, the first gate circuit is supplied with data from the first input terminal, the second gate circuit is supplied with data from the second input terminal, and the third gate circuit is supplied with data from the second input terminal. An integrated circuit in which data obtained by adding modulo 2 the data from the first and second input terminals is supplied to the gate circuit, and a flip-flop output is obtained from the second inverter circuit.