JPH01233379A - Logic block for digital integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a surplus delay when a circuit to be tested operates normally, by providing a transfer gate for inputting an external input into an FF through none of auxiliary gates. CONSTITUTION:A logic block having a plurality of functions which is built by combining basic units comprising an FF 102 suited to the operation of a shift register and a plurality of auxiliary gates (NOR gate 104 and EXOR gate 105) arranged on the input side of the FF 102 is provided with transfer gates 109 and 110 for inputting an external input into the FF 102 through none of the auxiliary gates. With such an arrangement, aside from a signal path passing through an auxiliary gate necessary to perform many functions, a signal path is provided to allow direct inputting into FFs and is controlled by a transfer gate free of gate delay, thereby enabling the production of a logic block with little delay.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention facilitates logic function testing of digital integrated circuits, especially digital integrated circuits, and allows the testing to be performed even on extremely complex circuits. The present invention relates to logic blocks for digital integrated circuits that can be incorporated into the integrated circuit itself in a manner that allows implementation of the logic blocks.

[Prior art]

One method to facilitate logic function testing of highly multiplicative and complex integrated circuits is to incorporate test mechanisms such as a test pattern generator and test output evaluation section inside the integrated circuit to be tested. That's true. By doing this, the test pattern is embedded inside the integrated circuit and cannot be directly accessed from external terminals. It is now possible to easily perform logic function tests on parts of the circuit that have been difficult to test and for which sufficient test accuracy could not be obtained.

By the way, when a test mechanism is incorporated into an integrated circuit, a big problem is what kind of logic block should be incorporated as the test mechanism.

The logic block incorporated as a test mechanism not only has the functions necessary for testing, that is, the function of a test pattern generator and the function of a test output evaluation section, but also allows the integrated circuit incorporating the logic block to perform normal functional operations. It is desirable that no logic block be involved in the functional operation.

Conventionally known logical blows of this type include 1.
International test conference aInternat, opened in 1979
@BUILT-IN on pages 37 to 41 of the collection of papers of ional Te5t Conference)
LOGIC-BLOCK 0BSERVATION
BI whose configuration is centered on the linear feedback shift register shown in the paper titled TECHNIQUES'
There is something called LBO.

As an example of this BILBO type logical block, one consisting of four basic units is shown in FIG.

One basic unit includes a clip 70 tube 202 suitable for shift register operation, an AND gate 203, and a NOR
It consists of three auxiliary gates: a gate) 204 and an exclusive OR circuit (hereinafter referred to as the original OR gate) 205.
Four of these basic units are arranged and subjected to linear feedback by the EXOR gate 108 to form the entire logic block.

This logic block performs four types of functions depending on the values of the control signals CI, C2, and C3. Here, when the control signal C3 is 10", the multiplexer 206
It is assumed that when the control signal C3 is @1'', the output of the EXOR gate 208 is output.

When CI=02=C3==0'', this logic block operates as a shift register, Cl=C2=10', C
When 3="1", it is disconnected from the external input D - D and the scan input Sin, and becomes a linear feedback shift register and operates as a free random pattern generator. C1=
When 03=″″1″, C2;″0″, external input D1~
It acts as a multi-input code analyzer that compresses D4, and also ci
=@i'', C2=-1'', the logic block works as a mere latch. Therefore, by replacing the latches in the original circuit under test with this logic block, it is possible to incorporate a test mechanism with less overhead.

[Problem to be solved by the invention]

However, when the conventional logic block described above works as a normal latch, the external input passes through the AND gate 203 and the EXOR gate 205 to the flip 70 and the EXOR gate 205.
2, there will be a delay of two gate stages compared to when this logic block is not used, so if the circuit under test requires high speed, this two gate stage This delay is unacceptable and a fatal drawback.

SUMMARY OF THE INVENTION An object of the present invention is to improve upon the problems of the prior art described above and to provide a logic block for built-in testing that does not cause extra delay when the circuit under test is in a normal operating state.

[Means to solve the problem]

The cooking block of the present invention has a plurality of functions constructed by combining a plurality of basic units consisting of a flip-flop suitable for shift register operation and a plurality of auxiliary gates arranged on the input side of this clip 70 tube. The logic block is characterized in that it is provided with a transfer gate that inputs an external input to the flip 70 tube without passing through the auxiliary gate.

[Effect]

The present invention solves the problems in the prior art by employing the above configuration. In other words, in addition to the signal path that passes through the auxiliary gates necessary to perform multiple functions, a signal path that can be directly input to the flip-flop is provided, and this signal is transferred to the transformer 7 agate without gate delay. By controlling the path, a logic block with almost no delay can be obtained.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing the case where the present invention is applied to the conventional example described above.

In FIG. 1, a basic unit 101 includes a flip-flop 102, which can be used as a shift register unit such as a master-slave flip-flop, and an AND gate 103. It consists of three auxiliary gates: a NOR gate) 104 and an EXOR gate 105, a transfer gate 109 controlled by a control signal φ, and a transfer gate 110 controlled by a control signal φ complementary to the control signal φ. Ru.

This basic unit 101 is replaced by the conventional basic unit 20.
1, transfer gate 109.1
The only difference is that 10 is added.

Therefore, when the control signals φ="0" and φ="11" are set, the transfer gate 109ri is cut off, the transfer gate 110 becomes conductive, and exactly the same state as the conventional example is realized.

In other words, with the control signals φ and φ added to the tiller set like that, the control (H number c1 * cle es to e
When l ``eg'' cl is set to ``0'', the logic block operates as a four-stage shift register, and the scan output S is passed from the scan power S to the inverter 107i. A scan path to utvc will be formed. Note that the multiplexer 106 is e3 as in the conventional example.
"O" to scan human power Sin, e3=-1" to E
Seven outputs of the XOR gate 108 are output.

Next, el”e2="0" and == @ 1 #
When set, the logic block is separated from the external inputs D1 to D4 and the scan path S, operates as a pseudo-random pattern generator, and outputs to the external outputs Q1 to Q4. Also, cl = c3 = -1", C! = ""0
”, the logic block acts as a multi-input code analyzer that introduces external inputs D1-D4.

All of the above three seventh modes are in a mode for testing the circuit under test, and at this time the logic block of the present invention operates in exactly the same way as a conventional logic block.

In the case of the other mode of operation, which is the operation mode of the logic block when the circuit under test operates fi t, the striped block according to the present invention uses the newly added control signal φ. This is done by setting ``1'' to ``1''.

When setting control #16 cl = e2 = @l, the control signal ≠ complementary to the control signal φ becomes “0” 9. The flip-flop is connected to the auxiliary gate, and external inputs DI to D
4 is input directly to the flip-flop. In other words, in the logic block of the present invention, an external input that passes through two stages of gates in the conventional example is input to the flip-flop 102 only by passing through the transfer gate 109.

The transfer gate 109 only needs to be kept in a conductive state when the circuit under test operates normally, and unlike logic gates, there is no delay caused by changing the output due to a change in the signal input value when the signal arrives, and there is no delay other than the delay due to wiring. There is almost no delay.

〔Effect of the invention〕

By employing the configuration described above, the logic block of the present invention can be used without deteriorating circuit performance.
At the same time, testability can be achieved because there is no delay during normal operation.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing one embodiment of the present invention, and FIG. 2 is a schematic diagram showing a conventional example. 101, 201...basic units), 102.2
02...mark/flip-flop, 103,203...
...AND gate. 104.204...NOR gate, 105,
108,205゜208...EXOR gate,
106, 206...Multiplexer, 107.
207...Inverter, 109,110-...
...transfer gate, el e eg e cl
eφ, φ... Control signal, D1 to D4...
・・External input, Q −Q ・・・External output,
Sin...Scan human power, 5 out...
・Scan output. Agent: Patent Attorney Shinsuke Uchihara

Claims (1)

[Claims] A logic block having multiple functions constructed by combining a plurality of basic units each consisting of a flip-flop suitable for shift register operation and a plurality of auxiliary gates arranged on the input side of the flip-flop. . A logic block for a digital integrated circuit, characterized in that a transfer gate is provided for inputting an external input to the flip-flop without passing through the auxiliary gate.