JP2001318125A - Circuit, system and method for lbist control determining maximum scanning channel length automatically - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an LBIST system in which an integrated circuit determines the longest channel of a scan core automatically. SOLUTION: An integrated circuit (10) comprises a combination circuit (13) and a plurality of scanning channels(SC) each having some number of elements (EC). A scanning channel having more than one elements includes first and last elements. In a scanning channel having one element, that element is both the first and last elements of a scanning channel. Selected elements are coupled to have an effect on the operation of a combination circuit. The integrated circuit further comprises a circuit (24) for inserting a specified pattern, while coupling, into the first elements of a plurality of scanning channels, a circuit (26) for detecting a specified pattern in the last elements of a plurality of scanning channels, and circuits (22, 23) for determining the number of elements in a longest scanning channel in response to the detection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to built-in self-test for integrated circuits and, more particularly, to a test controller that can be easily adapted to a variety of different integrated circuit designs.

[0002]

2. Description of the Related Art Due to the complexity of applications of modem integrated circuits,
The need for thorough testing when these devices are assembled has greatly increased. Typically, such tests are performed at the beginning of the life cycle of a device. If the device passes the test criteria, it is shipped for final use in the application. To facilitate this test, test circuits are often included in the integrated circuit, and the use of such circuits is commonly referred to as built-in self-test (BIST).
-Self-test). As described further below, BIST circuits often include a number of storage registers interconnected to form a circuit called a scan chain by those skilled in the art. Here, each register of the chain is usually configured as a flip-flop. To perform a test, given a test pattern, the test pattern is written to a scan chain register and the state of the integrated circuit is determined to evaluate whether it properly reflects the proper operation of the integrated circuit. Further, in this regard, prior to the advent of the BIST system, various test patterns were generated using a scan chain as described above to test using a tester external to the integrated circuit, and the test patterns were integrated into the integrated circuit. Was scanned into the scan chain and tested. However, more recently, BISTs have been developed, which include BIST controllers in many modern integrated circuits,
The need for an off-chip tester has been substantially reduced because the ST controller itself generates the test patterns. BIS
T has various related technologies. For example, a logic BIST (ie, “LBIST”) for testing a combinational logic circuit, a memory BIST for testing a memory circuit, and the like.

[0003] By way of further background, yet another, newer feature in the field of LBIST systems is the addition of an architecture to the LBIST, referred to by the acronym STUMPS, by those skilled in the art. This is "self
-Test using MISR / parallel
SRSG "(MSIR / self-test using parallel SRSG), where the MISR is" multi
iple inputsignature regis
ter (multi-input signature register)
SRSG stands for shift register sequence
This is an abbreviation of "nice generator" (shift register sequence generator). As described further below, the STUMPS architecture includes a variety of different scan paths called "channels." Each channel is also comprised of a number of interconnected storage registers, eg, flip-flops. In scan mode, L
After the BIST controller loads each test pattern into the multiple channels, the device is switched to its functional mode and operates for one or more clock cycles,
This changes the state of many of the nodes in the node group of the circuit. The state change includes a change that affects the storage contents of one or more scan channel registers in the scan channel register group. Thereafter, the device is returned to the scan mode and the data of the scan channel is shifted out and evaluated to determine if the expected result occurs. This confirms proper device operation or reveals device problems.
In addition to evaluating the scan channel data, the status and signals of other devices may be evaluated (eg, via an integrated circuit output pin) to determine if the device has performed properly in response to the test.

While the STUMPS architecture has significantly advanced the effectiveness of BIST and LBIST, we have noticed that the STUMPS architecture has significant drawbacks. Specifically, STUMPS
Further arising in connection with the multiple scan channels of the architecture is the fact that channels typically have different numbers of scan registers (or "cells"). According to those skilled in the art, these cell numbers are said to form the length of each scan channel. Thus, by applying this term to the foregoing, the scan channels may be said to be of different lengths. In any case, assuming this aspect, the LBIST controller must know the length of the longest scan channel. Thus, when the test pattern is loaded, LBIS
The T controller can correctly load the scan test pattern on the channel and control the LBIST test correctly. In the prior art, to satisfy this requirement, the longest scan channel length is hard coded into the LBIST controller when the controller is designed and formed. However, as with other aspects of circuit design, when a value is hard coded into an integrated circuit, the flexibility of the circuit is limited in relation to that value. For example, the LBIST once formed and hard-coded
The controller is restricted for use with the STUMPS architecture with the longest scan channel equal to the hard-coded value. As another example, if the length of the longest scan channel is changed during development of the integrated circuit, the planned hard-coded value is also changed so that the LBIST controller operates properly. Appropriate care must be taken.

[0005]

SUMMARY OF THE INVENTION In view of the above,
We present a preferred embodiment of the LBIST STUMPS architecture below. This preferred embodiment seeks to address and reduce and, where possible, eliminate the aforementioned disadvantages.

[0006]

SUMMARY OF THE INVENTION In a preferred embodiment, an integrated circuit including a combinational circuit is provided. The integrated circuit also includes a plurality of scan channels. Each of the plurality of scan channels includes a number of scan elements. For any of a plurality of scan channels having a number of scan elements greater than one, the scan channel includes a first element of the scan channel and a last element of the scan channel. For any one of a plurality of scan channels having a number of scan elements equal to one element, the one element is both the first element and the last element of the scan channel. Further, the selected scan elements are coupled to affect the operation of the combinational circuit. The integrated circuit further includes a circuit for coupling the predetermined pattern into a first element of each of the plurality of scan channels, and a circuit for detecting the predetermined pattern in the last element of each of the plurality of scan channels. Also includes circuits. Finally, the integrated circuit further includes a circuit responsive to the detection circuit for determining a number of scan elements in a longest scan channel of the plurality of scan channels. Other circuits, systems, and methods are also disclosed and claimed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an integrated circuit product indicated generally at 10. In the preferred embodiment, the integrated circuit product 10
Are various types of circuits, such as microprocessors,
Application Oriented Integrated Circuit (ASIC: application)
specific integrated circ
uit), digital signal processor (DSP), ST
LBI using UMPS or equivalent architecture
It can be one of the other devices desirably provided with the ST function. Note that the integrated circuit product 1
A zero may include numerous circuits, connections, and signals, but is not shown to simplify the present description. Integrated circuit product 10 shows only enough detail to illustrate the concept of LBIST operation as compared to all typical operations. In any event, some of those shown in FIG. 1 are known to those skilled in the LBIST art, but have been further refined as described below.

[0008] Integrated circuit 10 includes a scan core 12 known to those skilled in the art. Scan core 12 includes a number of scan channels, generally designated by the abbreviation "SC" (for "scan channel"). Also, by way of example, scan core 12 includes four such scan channels. In order to distinguish these scan channels from each other in the following description, each scan channel is represented by a numeral and an SC.
It is expressed by combining with the abbreviation of For example, the first scan channel is represented as SC1, the second scan channel is represented as SC2, and so on. Each scan channel includes a number of registers or storage elements. As mentioned earlier, the register or storage element is usually a flip-flop, the output of one flip-flop of one channel being connected to the input of the next successive flip-flop of that channel. For purposes of explanation, each storage element in FIG. 1 is represented by the abbreviation "E" (for "element"). This abbreviation "E" is followed by a channel abbreviation indicating the scan channel to which the element belongs. For example, each element represented as EC1 is an element of the scan channel SC1, and each element E
C2 is an element of the scan channel SC2, and so on. Also, for each scan channel, the element includes a subscript indicating the order of the elements along that channel. By examining the subscript for the last element in a channel, the total number of elements in that channel can be determined. For example, since the scan channel SC1 includes EC1 ₅ from EC1 _1, scan channel SC1 is (EC1 ₅ subscript "5"
It can be seen that this includes a total of 5 elements. It should also be noted in this connection that scan channels often do not all have the same number of storage elements. Therefore, for example, in scan core 12, scan channel SC1 has five storage elements, scan channel SC2 has eight storage elements, scan channel SC3 has six storage elements, and scan channel SC4 has four storage elements.
Storage elements. It should be noted that the number of these elements is merely an example, and in practice the number of storage elements in a scan channel can range from one to several hundred.

Before proceeding, it should be noted that FIG.
For simplicity, the scan channel elements are not explicitly shown connected to other circuits. But,
The use of these elements is well known for the purpose of testing such other circuits, where various different elements are connected to various different nodes or operating circuits for testing purposes. To illustrate this connection and relationship in a simple manner, integrated circuit 10 is shown to include a combinational logic block 13 connected to scan core 12 only entirely. The various scan channel elements are connected in various ways to the block 13 so that when the integrated circuit 10 is in the functional mode, the states stored by one or more of the elements in the group of elements are applied to the circuits in the block 13. And may affect the state stored by one or more elements in the group of elements. Combinational logic block 1
3 includes combinational logic as the name implies, and may include other types of circuits that are tested in combination with scan core 12. Either way, and as will be further appreciated, in scan mode, each scan channel operates as a shift register. This allows
The bits loaded into the first element of the scan channel are shifted to the next successive element of the channel,
The same applies to the remaining elements of each channel.
Therefore, different test bits can be arranged in each scan channel. Next, the integrated circuit 10 is switched to the functional mode and operates for one or more clock cycles. During this time, the combination of the scan channel element group and the block 13 operates as a functional circuit. Also, the function mode operation changes the state at a similar number of nodes in the node group of the combinational logic block 13. Thereafter, the integrated circuit 10 is returned to the scan mode, the data of the scan channel is shifted out,
Evaluated to determine if expected results occur.
This confirms the correct operation of the device or reveals a problem with the functional circuits of integrated circuit 10 (ie, scan core 12 and combinational logic block 13). In addition to evaluating scan channel data, the state and signals of other devices can be evaluated to determine whether integrated circuit 10 has operated correctly in response to a test.

Before proceeding, it should be noted that FIG.
Has been described as an ordinary flip-flop by way of example only. Therefore, other types of scan channel elements, where the elements commonly have the form of a scan chain as described above, are also considered to be within the scope of the present invention. For example, another type of such a scan channel element known to those skilled in the art is a multiplexer scan flip-flop, where the storage element comprises a multiplexer followed by a flip-flop. As another example, another type of scan channel element known to those skilled in the art is a clocked scan flip-flop, which operates in response to two different clocks. One clock is a scan clock for clocking data into the flip-flop,
Another clock is a functional clock for operating the flip-flop during operation in the functional mode. A final example of a scan channel element known to those skilled in the art and that can be constructed using the teachings of the present invention is an LSSD configuration consisting of two latches per element, where the latch is a master clock, Operates in response to a test clock and a slave clock. One skilled in the art can ascertain further examples.

Next, an integrated circuit 10 known to those skilled in the art.
Looking at additional aspects of the integrated circuit 10,
Includes additional BIST related circuitry. In one embodiment, the additional BIST related circuitry is a pseudo-random pattern generator (PRPG).
block 14) XO
R gate block 16 and a multiple input signature register (MISR: multiple input si
(g.g., a register). However, in alternative embodiments, each of these blocks may be replaced by other BIST performing circuits. In any case, blocks 14, 16, and 1
8 is controlled by the LBIST controller 20. As will be explained later, the LBIST controller 20 not only includes the circuits and methods for controlling these circuits according to the prior art, but also operates with the preferred method of the present invention. Integrated circuit 10
To further illustrate the similarities and differences between the present invention and the prior art, the following first describes blocks 14, 16, and 18 with respect to the prior art.
After the description, preferred embodiments of the present invention will be described in detail.

The LBIST controller 20 supplies one or more seeds to the PRPG block 14 and in response to the PRP
The G block 14 outputs a parallel stream of a pseudo random pattern bit sequence. After all, PRPG block 14
Are converted into bits used in the scan channel of the scan core 12. More specifically, these bit sequences are output by the PRPG block 14 to the XOR gate block 16. The XOR gate block 16 further manipulates these bits and provides them to the scan channels of the scan core 12, as will be described in more detail below.

An XOR gate block 16 is provided to remove some of the correlation between adjacent bit streams from the PRPG block 14. In particular, examining adjacent bit streams from the PRPG block 14 allows skilled artisans to identify significant levels of correlation between the streams, despite the pseudo-random operation of the PRPG block 14. . Thus, XOR gate block 16 uses a group of XOR gates (sometimes referred to by those skilled in the art as a cloud or phase shifter of XOR gates) to de-correlate these streams. XOR gate block 16 also often includes shifting the bit stream by a shift number that exceeds the maximum length of the scan channel of scan core 12. Finally, it should be noted that if the number of scan channels exceeds the number of outputs provided by PRPG block 14, XOR gate block 16 may also operate to allow some level of fanout. is there. In any case, the output of XOR gate block 16 is coupled (via a multiplexer described below) to the input of a scan channel in scan core 12.

The MISR block 18 provides an additional level of efficiency for processing the output of the scan channel. First, as described above, when the input scan test is performed, the output of the scan channel is checked to determine whether the device (here, the integrated circuit 10) operates correctly.
Further, in this context, MISR block 18 compresses data received as output from each scan channel. More specifically, this compression method uses a "signature" (sign) representing the data output from the scan channel.
a. This output is generally available outside of integrated circuit 10 and can be examined for signatures to determine test results. Further in this regard, as previously described, FIG. 1 is simplified in various respects and does not illustrate other circuits or the like that may be included in integrated circuit 10. One such other circuit is associated with another type of scan test, often referred to as a boundary scan test. This boundary scan test is IEEE1
A 149.1 boundary scan controller may also be included. This aspect is mentioned here because the signature output by the MISR block 18 can be used with such tests and with such a boundary scan controller.

Next, the remaining aspects of the integrated circuit 10 shown in FIG. 1 will be described. These aspects relate to preferred embodiments of the invention and are shown in certain respects to cooperate with the items already described. These additional aspects relate to the data input and output paths of the scan core 12 and to the operation of the LBIST controller 20 (and the circuitry to perform such operations). Each of these aspects is described below.

For the data inputs of the scan core 12, a set of multiplexers, each partially represented by the abbreviation M, is coupled between the output of the XOR gate block 16 and the respective input of the scan channel. Therefore, for each output of the XOR gate block 16 and each input of the scan channel, a corresponding multiplexer is provided, whose input is connected to receive data from the XOR gate block 16 and whose output is connected to the scan channel input. Connected. For reference, the name of each multiplexer is also given the same number as the number used by the corresponding scan channel. For example, multiplexer M1 corresponds to scan channel SC1, and multiplexer M2 corresponds to scan channel SC2. In addition to the connections described so far, each multiplexer M1 to M4 has a second input coupled to receive data from bus DB1.
As will be described later, the LBIST controller 20 supplies this data to the data bus DB1. Furthermore, the LBIST controller 20 also outputs a 4-bit control signal called MUX_CONTROL here. This signal is coupled to control bus CB. The control bus CB includes four control leads,
4 bits of UX_CONTROL are assigned to multiplexer M1
To each of the M4 control inputs. Given these connections, and in accordance with the preferred method described below, the LBIST controller 20 controls the MUX_CONT
The multiplexers M1 to M4 are controlled by setting the ROL to different states. During a certain period, all the multiplexers M1 to M4 are connected to the XOR gate block 1
6 to the scan channel, and during other periods, all multiplexers M1 to M4 use data bus D
Send the data from B1 to the scan channel. In practice, this preferred approach also allows control bus CB to be a one-conductor bus that indicates the same state to each of multiplexers M1-M4. In this case, the multiplexer M1
To M4 operate similarly to the others.

With respect to the output of the scan core 12, the MI
In addition to being connected to the SR block 18, each scan channel output is also connected to the data bus DB2. The data bus DB2 is connected to the LBIST controller 20. In this manner, and for reasons that will be described in detail below, the data output of scan core 12 is LBIS
It can be used for processing by the T controller 20.

FIG. 2 shows a block diagram of the LBIST controller 20 of FIG. 1, but the blocks of FIG. 2 are only those blocks relevant to the implementation of the method of the preferred embodiment. Therefore, L
The BIST controller 20 controls the PRP as in the connection shown in FIG.
Numerous other aspects, such as the control functions required to provide control signals to the G block 14 and the MISR block 18, can be included. Nevertheless, such additional aspects have not been shown or described in order to simplify the figures and the following description. Again, as an introduction, FIG.
Describes the preferred operation of the block of FIG. From this description, those skilled in the art will be able to ascertain numerous alternatives for constructing each such block. Further, in this context, the blocks merely provide a logical description of the function. Therefore, the actual hardware / software that realizes such a function may be such that blocks are combined or further divided based on a given configuration.

In the block of FIG. 2, the LBIST controller 20
Includes a state machine 22. As explained in more detail in FIG. 3, the state machine 22 controls the overall flow of the method. Furthermore, the state machine 22 includes a counter 23. The counter 23 monitors a count, here called SCAN_COUNT. Finally, SCAN_COUNT represents the length of the longest scan channel in scan core 12, which is the target of the preferred embodiment, as described in detail below.
The state machine 22 outputs MUX_CONTR as one output.
An OL signal is provided to the control bus CB. As previously described, control bus CB controls multiplexers M1 through M4 such that data from XOR gate block 16 or data from data bus DB1 is coupled to the scan channel. State machine 22 has a second output, which, as described in more detail below, is a PATTER
The N_CONTROL signal is applied to the pattern generator block 24.
Combined to give.

The pattern generator block 24 sets one of the two different bit patterns to the N of the data bus DB ₁ .
(For example, N = 4).
In a preferred embodiment, the first of the two patterns is the first of the two patterns, while all bits are in the first logical state (eg, all binary zeros). Becomes a second logic state (eg, all binary ones) in which all bits are complementary to the first logic state. Finally, choose between the two patterns is output to the data bus DB _1, which pattern generator block 24 receives from the state machine 22 PATTERN_C
This is performed in response to the ONCONTROL signal.

The LBIST controller 20 further includes a pattern change detection block 26. Pattern change detector block 26 receives the bit output of the scan channels that are connected to the data bus DB _2. As explained in detail below,
Pattern change detector block 26 examines these bits to detect the particular type of change in the received bits. When this change is detected, pattern change detector block 26 outputs signal CHANGE_DETECTED to state machine 22.
Give to. As described in detail below, state machine 2
2 further performs the preferred method. The specific type of pattern detection performed by block 26 is also described below. In connection with the description, a preferred circuit configuration for detecting such a pattern will be described.

FIG. 3 shows the scan core 12 of the integrated circuit 10.
Method 3 of Operation of LBIST Controller 20 to Determine Length of Longest STUMPS Scan Channel in
0 shows a flowchart. The flow of method 30 is controlled entirely by state machine 22. As will become apparent in the following description, additional functions of the other blocks of FIG. Method 30 begins at step 32. In step 32, state machine 22
Provides the first state PATTERN_CONTROL to the pattern generator block 24. PATTERN_C
In response to the ONCONTROL signal, the pattern generator block 24 starts outputting the first of the two bit patterns. For example, it is assumed that this pattern is composed of all binary zeros. Therefore,
These 0 is connected to the data bus DB _1. at the same time,
Since the state machine 22 sets the MUX_CONTROL signal to the first state, each of the multiplexers M1 to M4 sets 0 from the data bus DB1 to the scan channel SC1 to S.
Connect to the input of C4. As understood from the previous description, the pattern of all binary 0 is shifted into the first element of SC4 from each scan path SC1 (i.e., each element _{EC1 1, EC2 1, EC3 1} , EC4 1) . Further, at step 32, state machine 22 maintains the same control for an integer number of N clock cycles. This connects an integer number N instances of the first pattern to the scan channel. This shifts each previous instance of the first pattern in the direction of the next element of each scan channel. In the preferred embodiment, the integer N is chosen to be a number sufficiently larger than would be practically expected for the length of the longest scan channel. For example, as described above, a scan channel typically consists of one to several hundred elements. Therefore, given those numbers, N is preferably set to a larger number. Thus, for example, let N be equal to 1,000. Therefore,
Upon completion of step 32, ie, 1,000 clock cycles, the all-0 pattern is shifted through the elements of all scan channels of scan core 12. Further, since N is sufficiently longer than the longest scan channel of scan core 12, completion of step 32 causes all elements of all scan channels to store binary zero values. Next, method 30 includes step 34
Proceed to.

At step 34, state machine 22 clears the SCAN_COUNT value of counter 23. Furthermore,
State machine 22 by controlling the pattern change detector block 26, the pattern received from the data bus DB _2, i.e., starts the evaluation of all patterns output from the scan channel SC1 from all SC4. More particularly, below, the more apparent reason, pattern change detector block 26 by initiating the evaluation of the data of the data bus DB _2, first it is loaded into the scan channels in step 32 It detects when it indicates a second bit pattern different from the pattern. In a preferred embodiment, the second pattern comprises bits complementary to the first pattern. However, alternative approaches are possible, as will be explained later. Either way, in this example where the first pattern loaded into the scan channel in step 32 is all binary zeros,
Pattern change detector block 26 begins evaluating data on data bus DB2 to detect when the data exhibits a second pattern of all binary ones. It should be noted in this regard that one logic configuration that performs this detection is one that is configured using multiple AND gates.
That is, it can be a multi-input logic AND gate. The output of this gate is CHAN
Give the GE_DETECTED signal. As is known to those skilled in the art, such a logic gate changes its output from a logic low level to a logic high level only when all of its inputs go to a logic high level. Therefore,
When the pattern change detector block 26 detects that all the outputs of the scan channels SC1 to SC4 are high, the state of the CHANGE_DETECTED signal transitions and communicates the change to the state machine 22. It should be further noted that the use of AND gates is only for explanation of logic, and a more realistic component is to use logical NAND gates. This is because a logical NAND gate can be configured with fewer transistors than an equivalent product of an AND gate.

In step 36, state machine 22 provides the second state PATTERN_CONTROL to pattern generator block 24. PATTERN_CONTR
In response to the OL signal, the pattern generator block 24 starts outputting a second bit pattern of the two bit patterns. As previously described in step 34, in one embodiment, the second pattern comprises bits complementary to the first pattern. In this example, this second pattern is composed of all binary ones. Therefore, since these 1 is connected to the data bus DB _1, SC multiplexers M1 through M4 from each scan path SC1
4 the first element (i.e., respectively, from elements EC1 ₁ to EC4 ₁₎ is sent. Step 36
Now, for this first set of binary ones connected to the scan channel, the state machine 22
Increment the N_COUNT value. At this point, if only one set of binary ones is connected to the scan chain,
The value of SCAN_COUNT will be equal to one. Next, the method proceeds to step 38.

Step 38 includes a pattern change detector block 26 as to whether the output of the scan channel has all changed from a first pattern (eg, binary 0) to a second pattern (eg, binary 1). Represents the determination by. If this change has not occurred, method 30 returns from step 38 to step 36. Conversely, if a pattern change has occurred from binary 0 to binary 1, method 30 proceeds from step 38 to step 40. These will be described separately below.

The method 38 comprises steps 38 to 36
Is shown by applying this example of method 30 to the scan channel shown in FIG. For this, it should be noted in each instance of step 38, data data which is coupled to the pattern change detector block 26, which is evaluated in step 38, i.e. the final element (i.e. each scan channel elements EC1 _5, EC2 _8, EC3 _6, and E
C4 ₄ ). Further, before these elements binary 0 is (at Step 32) loading, only binary 1 1 set is shifted into elements EC1 _1, EC2 _1, EC3 _1, and EC4 _1, EC1 ₅ , EC2 _8, EC3 _6, and EC4 ₄ values all equal to still 0. As a result, at this point, the CHANGE_DETECTED signal indicates that the pattern received by the pattern change detector
It does not indicate that it is hexadecimal 1. As a result, method 30
The flow returns to step 36.

When the step reaches the next point in time, the same operations as described above are performed. However, in order to understand the result of this operation, the description will be continued with the example of the four scan channels of the scan core 12 in FIG. In particular, at this point in the example, step 36 shifts the pre-existing values in the scan channel by scanning the second set of binary ones into the first element of scan channels SC1 through SC4. I do. Thus, since this second set of binary ones shifts the first set of binary ones (scanned in to the first element of the scan channel of the previous instance of step 36), they are the first set of each scan channel. Proceed to the second element. Therefore, at this point, each scan channel SC1 to S
All other scan channel elements store binary 0, while the first and second elements of C4 store binary 1 values. Further, SCAN_C
Since OUNT is incremented again, at this time 2
Is stored. As explained earlier, step 3
Upon completion of step 6, method 30 proceeds to step 38.

Step 38 operates as previously described. In step 38, the pattern change detector block 26
Determines whether the last element of each scan channel stores a second pattern value (eg, a logical one). However, as described in the previous paragraph, at the current point of the example, these last elements each store a binary zero value. Therefore, CHANGE_DETECTE
The state of D does not change and the method flow returns to step 36
Return to

As will be apparent to those skilled in the art from the foregoing, in this example, steps 36 and 38 are repeated many times. It should be further noted in this connection that step 36 is
Means that the value of SCAN_COUNT will be equal to four. Moreover, at that time, binary 1 has reached the last element of scan channel SC4, i.e. the element EC4 _4. However, also at this time, the last element of the scan channel SC1, the last four elements of the scan channel SC2, and the last two elements of the scan channel SC3 still store a binary 0 value. As a result, when step 38 is reached following the fourth occurrence of step 36, the pattern change detector block 26 will have three binary 0 inputs and one binary 1 input, and CHANGE_D
No change occurs in ETECTED. Therefore, the flow returns to step 36 again.

The application of the preferred embodiment is based on step 36 of the present example.
Are further obtained by examining the fifth, sixth and seventh occurrences of. At the fifth occurrence of step 36, all elements of scan channels SC1 and SC4 store a binary one. However, the scan channel SC
2 last three elements (ie EC2 ₆ , E
C2 ₇ and EC2 ₈ ) and the last element of scan channel SC3 (ie, EC3 ₆ ) store binary zero. Accordingly, method 30 returns to step 36. At the sixth occurrence of step 36, all elements of scan channels SC1 and SC4 continue to store binary ones, and at this point all elements of scan channel SC3 also store binary ones. However, the last two elements of the scan channels SC2 (i.e., EC2 ₇ and EC2 ₈₎ is still stored binary 0. Accordingly, method 30 returns to step 36 again for the seventh occurrence of step 36. As a result, the binary 1 reaches the last previous element of the scan channel SC2. The method 30 then returns to step 36 again for the eighth occurrence of step 36.

At the eighth occurrence of step 36, a set of binary ones is again applied to the inputs of all scan channels. Then, as can be seen from the state before those elements, the scan channel SC
2 of the last element, i.e. binary 1 reaches EC2 _8. In addition, in the previous occurrence of step 36, all other scan channels SC1, SC3, and SC4 elements have also stored a binary one. Thus, at this point, the four outputs of scan core 12 all provide a binary one value to data bus DB ₂ , and thus to pattern change detector block 26. Next, method 30 proceeds to step 38 once again.

In this example, after step 38 is reached, if step 36 occurs eight times, the value of SCAN_COUNT becomes 8
And the data bus DB ₂ provides an all binary one to the pattern change detector block 26. In response to the complete set of binary ones, pattern change detector block 26 detects that a second pattern has been detected. As previously described, in this example, this detection is performed by a logical AND operation, and the CHANGE_DETECTED signal transitions positive in response to all inputs being at a logical high level. Since this signal transition now indicates that all the last elements of the scan channel are outputting the second pattern, method 30 proceeds to step 40.

Step 40 represents the completion of method 30. At this point, the value of SCAN_COUNT is
Equal to the length of the longest scan channel in. Thus, it should be noted that at step 40 the method 30 electronically determined the length of the longest scan channel. As a result, this value can be used in various ways as desired by those skilled in the art. For example, this value is required for additional BIST operations, and in fact, in the preferred embodiment, the number of times scan test data is shifted through successive elements of scan core 12 during scan mode, ie, each channel's This value is used to determine the number of shifts starting from the first shift-in of the scan test pattern into the first scan element and continuing with successive shifts through successive elements of the scan channel. Other uses of the longest scan channel length can be ascertained by those skilled in the art. In any case, in step 40, the length of the longest scan channel is automatically determined and LBIST
It is not necessary to hard-code the controller 20 or otherwise provide it in a fixed manner on the device. Finally,
Although not shown in FIG. 3, when the longest scan channel of the scan core 12 is determined and it is desired to perform the LBIST operation, the MUX_CONTROL is switched to the second state, and the multiplexers M1 to M1 are switched.
4 sends the data from the XOR gate block 16 to the scan core 12.

As can be seen from the foregoing, the above embodiments provide an improved circuit system and method that allows an integrated circuit to automatically determine the longest channel in a scan core. Such an approach has a number of advantages, especially when compared to the shortcomings of the prior art approach of hard-coding this length parameter into an integrated circuit. One advantage is that when the design of the integrated circuit is modified, the system can be incorporated early in the design of the device, redesigning later or designing based on pre-existing hard-coded length parameters. No changes are needed. As another advantage, the method 30 can be used with different LBIST controllers for different circuit designs, and those designs do not require modifications based on different maximum length scan channels. The skilled person can ascertain still other advantages. Indeed, yet another advantage is that the embodiments have been described in detail, but various substitutions, modifications or changes may be made to the above description without departing from the scope of the invention. For example, Method 3
Although 0 indicates various separate steps, some of these steps may be combined or divided into additional sub-steps. As another example, in the above example, the first pattern used in step 32 is all 0, and step 36 (and the repetition of step 36)
Shows the case where the second pattern used in is all ones, these patterns are interchanged and
In step 2, an all 1 pattern can be used, and in step 36, an all 0 pattern can be used. Of course, in this latter case, the specific circuitry in the pattern change detector block 26 that detects the latter pattern will require modification, as will be appreciated by those skilled in the art. As yet another example, the preferred embodiment uses first and second patterns that are all in the same binary state, but other patterns may be used in more complex configurations and the second pattern may be used. More complex detection circuitry is required to determine when all scan channels of scan core 12 have completely passed. As yet another example, BI
Various modifications may be made to the illustrated circuit to achieve the ST operation. For example, another type of pattern generator may be used in place of the PRPG block 14 or the MISR
Another type of response analysis circuit may be used in place of block 18. Therefore, these and other examples further illustrate the scope of the present invention. The scope of the invention is defined by the claims.

With respect to the above description, the following items are further disclosed. (1) An integrated circuit, comprising a combinational circuit and a plurality of scan channels, each of the plurality of scan channels including a certain number of scan elements, and a certain number of scan elements more than one element For any of the plurality of scan channels, the scan channel includes a first element of the scan channel and a last element of the scan channel, and for any of the plurality of scan channels with an equal number of scan elements as one element, The one element being both the first element and the last element of the scan channel, wherein the selected scan elements are coupled to affect the operation of the combinational circuit; The first element of each A circuit for coupling a predetermined pattern into the plurality of scan channels, a circuit for detecting a predetermined pattern in the last element of each of the plurality of scan channels, and a plurality of scan channels in response to the detection circuit. And a circuit for determining the number of scan elements in the longest scan channel.

(2) The integrated circuit according to (1), wherein prior to the operation of the circuit for coupling a predetermined pattern to the first element of each of the plurality of scan channels, the plurality of scan channels are connected to each other. An integrated circuit that also includes circuitry for setting all values of all elements of each channel to a predetermined state.

(3) The integrated circuit according to (2), wherein the predetermined state includes a first binary state, and wherein the predetermined pattern is complementary to the first binary state. An integrated circuit comprising: (4) The integrated circuit according to claim 3, wherein said predetermined state includes binary 0 and said predetermined pattern includes binary 1.

(5) The integrated circuit according to (4), wherein the detection circuit performs a logic A operation on a value output by the last scan element of each of the plurality of scan channels.
An integrated circuit including a circuit for performing an ND operation. 6. The integrated circuit of claim 5, further comprising: a pattern generator for generating a bit pattern; and a response analysis circuit coupled to receive a bit state from each of the last elements of the scan channel. An integrated circuit including:

(7) The integrated circuit according to item 6, wherein the pattern generator includes a pseudo-random pattern generator for generating a pseudo-random bit pattern, and further includes a gate circuit coupled to the pseudo-random pattern generator. And a gate circuit for providing a set of output test bits by dissociating the pseudo-random bit pattern, and coupling the set of output test bits to each of the first elements of the scan channel during a test mode. And an integrated circuit.

(8) The integrated circuit according to (7), wherein said circuit for coupling the output test bit set to each of the first elements of the scan channel during a test mode comprises a plurality of scan channels. An integrated circuit responsive to a defined number of scan elements in the longest scan channel of the integrated circuit. (9) The integrated circuit according to (6), wherein the response analysis circuit includes a multiple-input signature register.

(10) The integrated circuit according to item 3, wherein
An integrated circuit further comprising a pattern generator for generating a bit pattern, and a response analysis circuit coupled to receive a bit state from each of the last elements of the scan channel.

(11) The integrated circuit according to item 10, wherein the pattern generator includes a pseudo-random pattern generator for generating a pseudo-random bit pattern, and further includes a gate circuit coupled to the pseudo-random pattern generator. A gate circuit for providing an output test bit set by determining the inverse correlation of the pseudo-random bit pattern, and for coupling the output test bit set to each of the first elements of the scan channel during a test mode. And an integrated circuit including the circuit.

(12) The integrated circuit according to item 10, wherein the response analysis circuit includes a multi-input signature register.

(13) The integrated circuit according to item 1, wherein
Prior to the operation of the circuit for combining a predetermined pattern into the first element of each of the plurality of scan channels, all values of all elements of each of the plurality of scan channels are set to a predetermined state. The number of scan elements in the longest scan channel among the plurality of scan channels is constituted by an estimated integer M of scan elements, and the circuit for setting all values is a sequence of integers X. An integrated circuit comprising: a circuit for scanning a predetermined state into a first element of a first scan channel, wherein X is greater than M.

14. The integrated circuit according to claim 13, wherein said predetermined state includes a binary 0, and said predetermined pattern includes a binary 1. (15) The integrated circuit according to (14), wherein the detection circuit includes a circuit for performing a logical AND operation on a value output by a last scan element of each of a plurality of scan channels. Integrated circuit.

(16) The integrated circuit of clause 15, further comprising a pattern generator for generating a bit pattern, and a response coupled to receive a bit state from each of the last elements of the scan channel. An integrated circuit including an analysis circuit.

(17) The integrated circuit according to item 16, wherein the pattern generator includes a pseudo-random pattern generator for generating a pseudo-random bit pattern, and further includes a gate circuit coupled to the pseudo-random pattern generator. A gate circuit for providing an output test bit set by determining the inverse correlation of the pseudo-random bit pattern, and for coupling the output test bit set to each of the first elements of the scan channel during a test mode. And an integrated circuit including the circuit.

(18) The integrated circuit according to (16), wherein the response analysis circuit includes a multiple-input signature register. 19. The integrated circuit of claim 1, wherein selected ones of the scan elements are coupled to affect operation of the circuit in addition to the combinational circuit.

(20) A method for operating an integrated circuit having a plurality of scan channels each including a certain number of scan elements, wherein a predetermined pattern is combined in a first element of each of the plurality of scan channels. Wherein, for any of a plurality of scan channels having a number of scan elements greater than one, the scan channel includes a first element of the scan channel and a last element of the scan channel; For any one of a plurality of scan channels with an equal number of scan elements as one element, said one element being both the first element and the last element of the scan channel; And multiple Detecting a predetermined pattern in each last element of the scan channels; and responsive to the detecting step, determining a number of scan elements in a longest scan channel of the plurality of scan channels. An operation method of an integrated circuit.

(21) The method of operating an integrated circuit according to item 20, wherein each of the plurality of scan channels is provided with a predetermined pattern in combination with the first element of each of the plurality of scan channels. A method of operating an integrated circuit, further comprising the step of setting all values of a first element of a channel to a predetermined state. (22) The method for operating an integrated circuit according to item 21, wherein
Responsive to a predetermined number of scan elements in a longest scan channel of the plurality of scan channels, coupling an output test bit set to each of the first elements of the scan channel during a test mode. How the circuit works.

(23) The method of operating an integrated circuit according to paragraph 22, wherein in response to the predetermined number of scan elements in the longest scan channel among the plurality of scan channels being equal to an integer N, A method of operating an integrated circuit, the method further comprising coupling an output test bit set N times to each of the first elements of a scan channel during a scan mode.

(24) An integrated circuit (10) including a combinational circuit (13). The integrated circuit also includes a plurality of scan channels (SC1 to SC4). Including the number scan elements in each of the plurality of scan channels (EC1 ₁ from EC4 _5). For any of a plurality of scan channels having a number of scan elements greater than one, the scan channel includes a first element of the scan channel and a last element of the scan channel. For any one of a plurality of scan channels having a number of scan elements equal to one element, the one element is both the first element and the last element of the scan channel. Further, the selected scan elements are coupled to affect the operation of the combinational circuit. The integrated circuit further includes a circuit (2) for coupling the predetermined pattern into the first element of each of the plurality of scan channels.
4) and a circuit for detecting a predetermined pattern in the last element of each of the plurality of scan channels (2)
6) is also included. Finally, the integrated circuit further includes, in response to the detection circuit, a circuit (22, 23) for determining a number of scan elements in a longest scan channel of the plurality of scan channels.

[Brief description of the drawings]

FIG. 1 shows a scan core 1 having a large number of scan channels
FIG. 2 is an electrical diagram of an integrated circuit 10 provided with an integrated circuit 2.

2 is a block diagram of the LBIST controller 20 of FIG. 1 in a block configuration area to achieve the method of the preferred embodiment.

FIG. 3 is a flowchart of a preferred method of the LBIST controller 20 of FIG. 2 for determining the length of the longest STUMPS of the scan core 12.

[Explanation of symbols]

10 Integrated Circuit 13 Combinational Logic Block 14 Pseudo Random Pattern Generator (PRPG) Block 16 XOR Gate Block 18 Multiple Input Signature Register (MISR) Block 22 State Machine 23 Counter 24 Pattern Generator Block 26 Pattern Change Detector Block 30 Method 32 First pattern scan-in step 36 Second pattern scan-in step 38 Scan channel output change determination step EC Scan channel element SC Scan channel

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Anthony Flyearth UK Northern Ireland, North Hampton, Duston, Duston Wildes 65 F-term (reference) 2G032 AA01 AC03 AC10 AG04 AH04 AK16 AK19 5F038 DF01 DF04 DF11 DT06 DT07 DT08 DT10 EZ20

Claims (2)

[Claims] 1. An integrated circuit, comprising: a combinational circuit; a plurality of scan channels, each of the plurality of scan channels including a certain number of scan elements; For any one of the plurality of scan channels, the scan channel includes the first element of the scan channel and the last element of the scan channel, and for any one of the plurality of scan channels having the same number of scan elements as one element. The one element is both the first element and the last element of the scan channel, wherein the selected scan elements are coupled to affect the operation of the combinational circuit; Scan channel A circuit for combining a predetermined pattern in each of the first elements; a circuit for detecting a predetermined pattern in the last element of each of the plurality of scan channels; A circuit for determining the number of scan elements in the longest scan channel among the plurality of scan channels. 2. A method for operating an integrated circuit having a plurality of scan channels, each including a number of scan elements, comprising: combining a predetermined pattern in a first element of each of the plurality of scan channels. In any of a plurality of scan channels having a number of scan elements greater than one, the scan channel includes a first element of the scan channel and a last element of the scan channel; For any one of a plurality of scan channels having an equal number of scan elements to one element, said one element being both the first element and the last element of the scan channel; , Multiple scans Detecting a predetermined pattern in each last element of the channel; and determining, in response to the detecting step, a number of scan elements in a longest scan channel of the plurality of scan channels. How the circuit works.