JP2000304823A - Integrated circuit and its fault detecting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit capable of easily obtaining a high fault detection rate of a flip-flop or a logic gate to be provided with fault detection in any internal signal condition by building a fault detection circuit in an integrated circuit having at least a flip-flop and a logic gate, and to provide an integrated circuit capable of achieving a high fault detection rate using more simple test pattern than a conventional fault detection system with a small number of terminals, and its fault detection system. SOLUTION: This fault detection system is constituted so that outputs of flip-flops 1, 2, 4 to be detected their faults and a logic gate to be inspected its fault are input to one terminal of an exclusive OR gate for detecting a fault, and a test signal for detecting a fault is input to the other terminal for detecting a fault, so that the system detects the fault by the above constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit and a system for detecting a failure of the integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a failure detection method of an integrated circuit,
Japanese Patent Application Laid-Open No. Hei 04-215080 is known.

This system is a failure detection circuit for detecting a failure of a logic gate formed in an integrated circuit. In this method, an output signal of a logic gate for detecting a fault is input, and a fault detection circuit including a plurality of exclusive OR gates for determining whether the logic is normal or abnormal is provided for an integrated circuit to be detected. It is provided separately from the functional unit.

This system is characterized in that it has a selector for switching the output signal of the failure detection circuit to at least one of the output terminals of the integrated circuit and outputting the output signal according to an external control signal.

[0005] However, in the conventional fault detection circuit, the result when the normal case and the case where a plurality of logic gates inside the integrated circuit fail is the same, and it is not possible to determine whether the fault has occurred or not. There is a drawback that occurs. Further, the conventional fault detection circuit has a disadvantage that an error cannot be detected when a plurality of faults occur simultaneously in a logic gate and a flip-flop formed inside the integrated circuit.

On the other hand, a so-called scan-path failure detection method is known as a failure detection method for a flip-flop circuit formed in an integrated circuit.

[0007] The failure detection method by the scan path method is as follows.
A selector is added to the input portion of all flip-flops inside the integrated circuit, and the switching of the selector is repeated to repeatedly scan and fetch scan data and test the combinational circuit, thereby increasing the failure detection rate of the semiconductor integrated circuit. is there.

In this method, a minimum of (the number of flip-flops + 1) clocks is required for one test. Therefore, if the test is performed n times in order to obtain a high failure detection rate, {(number of flip-flops + 1) × 2} × n patterns are required.

As described above, the failure detection method using the scan path method has a disadvantage that the test pattern for confirming the operation of the integrated circuit in all states is complicated and not simple.

That is, the scan path method has a defect that the fault detection method of the flip-flop has a high fault detection rate, but has a complicated test pattern and a large number of terminals for fault detection.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to incorporate a fault detecting circuit in an integrated circuit having at least a flip-flop and a logic gate, and to easily detect a fault in any internal signal state. An object of the present invention is to provide an integrated circuit capable of obtaining a high gate fault detection rate.

Another object of the present invention is to provide an integrated circuit in which at least a flip-flop and a logic gate are integrated and integrated, in which a higher failure detection rate can be obtained with a smaller number of terminals using a simpler test pattern. It is to provide.

Still another object of the present invention is to provide an integrated circuit fault detection system.

[0014]

According to the present invention, a flip-flop, a logic gate, an output of the flip-flop and an output of the logic gate are input to one input terminal, and a fault is input to the other input terminal. An exclusive-OR gate for detecting a failure, to which a test signal for detection is input, to obtain an integrated circuit.

According to the present invention, in an integrated circuit failure detection system having at least a flip-flop and a logic gate, the output of the flip-flop to be detected for failure and the output of the logic gate to be detected for failure are exclusive. An input to one input terminal of the OR gate, and a test signal for detecting a failure is input to the other input terminal of the exclusive OR gate to detect a failure. A fault detection scheme is obtained.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an integrated circuit according to the present invention and a fault detection method for the integrated circuit will be described.

An integrated circuit according to the present invention is an integrated circuit having at least a flip-flop and a logic gate, wherein an exclusive-OR for detecting a fault between the output of the flip-flop to be detected and the output of the logic gate to be detected. It is configured to input to one input terminal of the gate and to input a test signal for failure detection to the other input terminal.

To detect a fault in a flip-flop of an integrated circuit having such a configuration or a logic gate having a predetermined logic function, the output of the flip-flop to be detected for fault or the output of the logic gate is one of the exclusive OR gates. , And a test signal for fault detection is input to the other input terminal of the exclusive OR gate.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an integrated circuit according to an embodiment of the present invention;

[First Embodiment] FIG. 1 is a diagram showing a configuration of an integrated circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of an integrated circuit that does not incorporate the failure detection circuit corresponding to FIG.

FIG. 1 and FIG. 2 show an example of a configuration for explaining an integrated circuit and a fault detection method for the integrated circuit according to the present invention. The configuration includes at least a flip-flop to be detected and a logic gate to be detected. I have.

The integrated circuit of FIG. 1 according to the first embodiment of the present invention incorporates a fault detection circuit for detecting a fault in two flip-flop FF circuits 1, an FF circuit 2, and a logic gate 3.

In FIG. 1, the input signals DIN1, DIN
2 are input to the FF circuit 1 and the FF circuit 2, respectively. The clock signal (hereinafter, referred to as CLK) and the reset signal (hereinafter, referred to as RST signal) are supplied to the FF circuit 1,
It is connected to the inputs of the FF circuits 2 and 4.
The outputs of the FF circuit 1, FF circuit 2 and logic gate 3 to be detected for failure are connected to one input terminals of two-input exclusive OR gates 5 to 7, respectively. Further, the other input terminals of the two-input exclusive OR gates 5 to 7 are connected to test input terminals 8 to 10 for detecting faults, respectively.

Next, the operation of the integrated circuit according to the first embodiment of the present invention, that is, the operation of the integrated circuit incorporating the fault detection circuit in the fault detection system will be described with reference to FIG. 1 and FIGS.

FIGS. 3 and 4 are timing charts showing the operation of the fault detection system for an integrated circuit according to the present invention.

Referring to FIG. 3, in the integrated circuit of FIG.
IN1 is a fixed value of "1", input DIN2 is a fixed value of "0", and all "0" are fixed to test input terminals 8 to 10 connected to inputs of two-input exclusive OR gates 5 to 7. When a value is input, the output of the 2-input AND gate circuit 3 becomes C
As shown in (2), the value becomes a fixed value of "0", and the operation becomes insufficient for failure detection.

Referring to FIG. 4, input D in the integrated circuit of FIG.
IN1 is a fixed value of “1”, input DIN2 is a fixed value of “0”, and a signal that regularly changes to test input terminals 8 to 10 connected to inputs of two-input exclusive OR gates 5 to 7 When a pattern is input, the output A of the two-input exclusive OR gate 5 and the output B of the two-input exclusive OR gate 6 become A and B, respectively. As a result, the output of the two-input AND gate 3 becomes C.

The regular signal patterns TEST1 to TEST3 to be input to the test input terminals 8 to 10 are input such that the farther from the output terminal, the longer the cycle of the test input signal. By setting the regular signal pattern to 2 @ n clock cycles, it is possible to detect failures in all states. Here, n is a total count of flip-flops and logic gate circuits.

FIG. 5 is a timing chart when the FF circuit 1 of the integrated circuit of FIG. 1 has failed, FIG. 6 is a timing chart when the FF circuit 2 of the integrated circuit of FIG. 1 has failed, and FIG. 7 is an integrated circuit of FIG. The timing charts when the AND gate of the circuit fails are shown.

Next, a timing chart when the FF circuit 1 of FIG. 1 has failed will be described with reference to FIG.
FIG. 5 shows a time chart when the FF circuit 1 of FIG. 1 fails and a fixed value of “0” is output.

Originally, the output of the FF circuit 1 must output a fixed value of "1", but continues to output a fixed value of "0". As a result, the output A of the two-input exclusive OR gate 5 becomes A, which is inverted as compared with the case of A in FIG. Further, the output C of the two-input AND gate circuit 3 and the output D of the two-input exclusive OR gate 7 become C and D in FIG. 5, which is different from the case of C and D in FIG. Therefore, the output result OUT of FIG.
Is different from the waveform of OUT in FIG. 4 and the failure can be detected.

As shown in the timing chart of FIG.
Considering a case where a regular signal pattern is not input to the test input terminals 8 to 10, even if the FF circuit 1 fails and a fixed value of “0” is output, the output result OUT is a fixed value of “0”. Is output, and the result is the same as in the case where there is no failure. However, as shown in FIG. 4, a fault can be detected by inputting a regular signal pattern to the test input terminals 8 to 10.

Next, a timing chart when the FF circuit 2 of FIG. 1 has failed will be described with reference to FIG.
FIG. 6 shows a time chart when the FF circuit 2 fails and a fixed value of “1” is output.

Originally, the output of the FF circuit 2 must output a fixed value of "0", but continues to output a fixed value of "1". As a result, the output B of the two-input exclusive OR gate 6
Becomes B in FIG. 6, and is inverted as compared with the case of B in FIG. Therefore, the output result OUT of FIG. 6 is different from the waveform of OUT of FIG. 4, and the failure can be detected.

Considering the case where a regular signal pattern is not input to the test input terminals 8 to 10 as shown in FIG.
If the output of the circuit 2 fails and a fixed value of “1” is output, the output result OUT outputs a fixed value of “1”, and the result is different from the case where there is no failure. In this case, a failure can be detected even when a regular signal pattern is not input to the test input terminals 8 to 10.

Next, a timing chart when the two-input AND gate circuit 3 shown in FIG. 1 has failed will be described with reference to FIG. FIG. 7 shows a time chart when the 2-input AND gate 3 fails and outputs a fixed value of "1".

In the figure, the output of the two-input exclusive OR gate 7 is D. Therefore, the output result OUT of FIG.
Is different from the OUT waveform of FIG.

As shown in FIG. 3, test input terminals 8 to 1
Considering a case where a regular signal pattern is not input to 0, if the 2-input AND gate 3 fails and outputs a fixed value of “1”, the output result OUT outputs a fixed value of “1”. The result is different from the case where there is no failure. Also in this case, fault detection can be performed without inputting a regular signal pattern to the test input terminals 8 to 10.

As described above, according to the integrated circuit and the fault detection method for the integrated circuit according to the present invention, it is possible to detect a fault of a flip-flop or a logic gate which is incorporated in all the integrated circuits and is to be detected.

Even if the number of flip-flops and logic gates incorporated in the integrated circuit increases, if a two-input exclusive OR gate is configured corresponding to the flip-flop or logic gate for detecting a fault with the same configuration as that shown in FIG. Good.

FIG. 8 is an enlarged circuit diagram of the integrated circuit according to the first embodiment of the present invention. This integrated circuit includes flip-flop FF circuits 21 to 25, a two-input AND gate 31, a three-input AND gate 41, and a two-input OR gate 5.
Two-input exclusive OR gates 61 to 68 for detecting a fault are configured to detect one fault.

FIG. 8 shows an increase in the number of flip-flops and logic gate circuits in comparison with FIG.
Similarly, the output of the flip-flop or the logic gate to be detected for failure is connected to one of the two-input exclusive OR gate,
A test input terminal may be provided for the other input.

The method of detecting a failure of this integrated circuit is described in the first embodiment.
The description is omitted because it is performed in the same manner as described above.

[Embodiment 2] FIG. 9 is a circuit diagram of an integrated circuit according to Embodiment 2 of the present invention.

The integrated circuit according to the second embodiment of the present invention
An FF circuit 1, an FF circuit 2, an FF circuit 4, a two-input AND gate 3 having a predetermined logic function,
And two-input exclusive OR gates 5 to 7 for detecting a failure of the FF circuit 2 and the two-input AND gate 3, and a test signal generating means 11. FF circuit 1 to be detected for failure,
The outputs of the FF circuit 2 and the two-input AND gate 3 are connected to one input of two-input exclusive-OR gates 5 to 7, respectively, and the other input of the two-input exclusive-OR gates 5 to 7 generates a test signal. Test signal outputs Q1, Q2, Q0 output from the means 11 are connected respectively.

In the integrated circuit of the first embodiment shown in FIG. 1, a test signal for detecting a failure of the integrated circuit must be supplied from the outside to be tested. In this embodiment, the test signal generating means 11 is provided inside the integrated circuit. It is characterized by having. FIG.
In the above, a down-count circuit is incorporated as the test signal generating means 11. FIG. 10 shows test signal generating means 1.
4 shows a timing chart relating to a down count circuit which is 1. When the reset signal is released, the two-input exclusive OR gates 5 to 6 are synchronized with the timing of CLK.
Test signals Q1, Q2, and Q0 are respectively input to one of the inputs.

By incorporating the test signal generating means 11 for detecting a failure in the integrated circuit in the integrated circuit as described above, a dedicated test terminal for detecting a failure in the integrated circuit becomes unnecessary.

The method of detecting a failure of the FF circuit 1, the FF circuit 2, and the logic gate 3 of the integrated circuit according to the second embodiment is described in the first embodiment.
Since this is performed in the same manner as the integrated circuit failure detection method described above, the description is omitted.

[0049]

According to the present invention, in an integrated circuit having at least a flip-flop and a logic gate, an exclusive-OR for detecting a failure between the output of the flip-flop to be detected and the output of the logic gate to be detected. By adopting the integrated circuit fault detection method described above, the integrated circuit is configured to input to one input terminal of the gate and to input a test signal for fault detection to the other input terminal. This makes it possible to detect a fault in a flip-flop or a logic gate, thereby obtaining a high fault detection rate.

Further, by forming a down-counting circuit inside the integrated circuit as a test signal generating means for detecting a fault, the number of terminals for detecting a fault can be reduced as compared with the conventional fault detecting method. Thus, there is an effect that a high fault detection rate of an integrated circuit can be obtained with a simple test pattern.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an integrated circuit in which a failure detection circuit according to the first embodiment of the present invention is not incorporated.

FIG. 3 is a timing chart for explaining the operation of the first embodiment according to the present invention.

FIG. 4 is a timing chart for explaining the operation of the first embodiment according to the present invention.

FIG. 5 is a timing chart for explaining the operation of the first embodiment according to the present invention.

FIG. 6 is a timing chart for explaining the operation of the first embodiment according to the present invention.

FIG. 7 is a timing chart for explaining the operation of the first embodiment according to the present invention.

FIG. 8 is an enlarged circuit diagram of the integrated circuit according to the first embodiment of the present invention.

FIG. 9 is a circuit diagram of an integrated circuit according to a second embodiment of the present invention.

FIG. 10 is a timing chart illustrating an operation of the down-count circuit.

[Explanation of symbols]

 1, 2, 4 FF circuit 5-7, 61-68 2-input exclusive OR gate 3, 31 2-input AND gate 8-10 Test input terminal 11 Test signal generating means 41 3-input AND gate 51 2-input OR gate

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA01 AB01 AC03 AD07 AG07 AK01 AK15 AL05 5F038 BE01 DF01 DT07 DT08 DT12 EZ20 5J056 AA03 BB60 CC14 CC17 FF01 FF07 FF09 GG14

Claims (6)

[Claims] 1. A fault in which an output of the flip-flop and an output of the logic gate are respectively input to one input terminal of a flip-flop, a logic gate, and a test signal for fault detection is input to the other input terminal. An exclusive-OR gate for detection. 2. The integrated circuit according to claim 1, wherein said flip-flop, said logic gate, and said exclusive OR gate are integrated. 3. An integrated circuit failure detection system having at least a flip-flop and a logic gate, wherein an output of the flip-flop to be detected for failure and an output of the logic gate to be detected for failure are each one of exclusive OR gates. A fault detection method for detecting a fault by inputting a test signal for fault detection to the other input terminal of the exclusive OR gate. 4. A flip-flop, a logic gate, and a fault in which the output of the flip-flop and the output of the logic gate are input to one input terminal and a test signal for fault detection is input to the other input terminal. An integrated circuit, wherein an exclusive OR gate for detection and test signal generating means for generating the test signal are integrated. 5. The integrated circuit according to claim 4, wherein a down-count circuit is used as said test signal generating means. 6. An integrated circuit failure detection system having at least a flip-flop and a logic gate, wherein an output of the flip-flop to be detected for failure and an output of the logic gate to be detected for failure are each one of exclusive OR gates. And a test signal from the down-count circuit is input to the other input terminal of the exclusive OR gate to detect a fault.