JP2000206199A - Lsi designing technique for packaging inspection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to detect at which terminal an anomaly has occurred by providing as inspecting circuit inside a LSI and detecting that the logical level of an unused input terminal becomes anomalous due to a mounting failure, etc. SOLUTION: The logical level of an output signal 'DCT' of a multiple-input NAND circuit 6 is observed. It is normal when the logical level is 'low', and an anomaly has occurred when it is 'high'. In the case that 'DCT' is 'high', only output signals 'DCT(2n-1)' (odd numbers) of an NAND circuit 5 are observed for specifying failure locations. In the case that only 'DCT3' is, for example, 'high' here, the location of 'NC-IN2' or 'NC-IN3' is suspected of developing a failure. 'DCT2' and 'DCT4' are further observed, and a failure has occurred in 'NC-IN2' in the case that 'DCT2' = 'high' and that 'DCT4' = 'low'. In the case that 'DCT4' = 'high' and that 'DCT2' ='low', a failure has occurred in 'NC-IN3'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI design method for mounting inspection.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional LSI (large-scale integrated circuit).
It is a block diagram of. Reference numeral 1 denotes an LSI capable of freely designing a function desired by a user, and reference numeral 4 denotes an internal circuit which is the center of the function of the LSI 1.

If there is an unused input terminal in the LSI 1, in order to stabilize the logic level (voltage level), the terminal is subjected to pull-up or pull-down, and the logic level is changed to "High" level or "Low".
Must be fixed to level. However, when the mounting failure of the LSI 1 occurs, there may be a case where it becomes impossible to stabilize the logic level of the unused input terminal.

[0004]

In the above-described conventional LSI design method, when a failure occurs at an unused input terminal for some reason, the logic level becomes unstable, and the L level becomes unstable.
The operation of the SI itself may be adversely affected. In addition, it is difficult to predict the cause of such a situation. As described above, when the logic level of the unused input terminal becomes unstable, there is a problem that it is impossible to take a countermeasure because the cause is not known.

Accordingly, the present invention can detect that the logic level has become unstable due to a mounting failure or the like when the logic level (voltage level) of an unused input terminal in an LSI is fixed. It is an object of the present invention to provide an LSI design method for mounting inspection that can detect which terminal has an abnormality.

[0006]

According to the present invention, a test circuit is provided in an LSI, and when the logic level of an unused input terminal of the LSI becomes abnormal due to a mounting defect or the like in the test circuit. This is an LSI design method for mounting inspection, characterized in that it is possible to detect that fact and to detect at which terminal an abnormality has occurred.

With this configuration, when the logic level (voltage level) of an unused input terminal in an LSI is fixed, it is possible to detect that the logic level has become unstable due to a mounting failure or the like. An LSI design method for mounting inspection that can detect whether an abnormality has occurred in a terminal can be realized.

[0008]

According to the first aspect of the present invention, an inspection circuit is provided inside an LSI, and the logic level of an unused input terminal of the LSI becomes abnormal due to a mounting defect or the like in the inspection circuit. In this case, it is possible to detect the occurrence of an abnormality and to detect at which terminal an abnormality has occurred.
This is a design method.

According to a second aspect of the present invention, it is possible to detect at which terminal an abnormality has occurred by using a logic circuit for the inspection circuit and preparing the same number of logic circuits as the number of terminals of the LSI. And

According to a third aspect of the present invention, there is provided a switching circuit capable of switching between two modes (a mode for performing an inspection and a mode in a normal operation state).

In the above configuration, when the logic level of the unused input terminal of the LSI is abnormal in the inspection circuit, it can be detected, and moreover, which terminal is abnormal can be detected. . Further, by devising the inspection procedure, the inspection is performed while narrowing down the terminal in which the abnormality has occurred, so that the inspection time can be reduced.

FIG. 1 is a block diagram of an LSI according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the same operation, and FIG.
FIG. 4 shows a truth table of the D circuit, and FIG. 4 shows the same operation (inspection procedure)
FIG. 5 is a diagram showing a truth table of the inspection circuit, and FIG. 6 is a circuit diagram showing the same operation.

In FIG. 1, reference numeral 1 denotes an LSI capable of freely designing a function desired by a user, 2 denotes an inspection circuit capable of detecting when the logical level of an unused input terminal is abnormal,
Reference numeral 3 denotes a switching circuit for switching the output terminal between the normal operation mode and the test mode so as to use the output terminal properly, and reference numeral 4 denotes an internal circuit which is the center of the function of the LSI 1.

The operation of the LSI 1 will be described with reference to FIGS. 2, 3, 4, and 5. In the test circuit of FIG. 2, it is assumed that the logic level of the unused input terminals (NC-IN1 to NC-IN6) of the LSI is fixed at the “High” level. Here, FIG. 3 shows the NAND circuit 5 and the multi-input NAN.
6 is a truth table of the D circuit 6. The output of the NAND circuit becomes “Low” when all inputs are “High”, and the output becomes “High” when at least one input becomes “Low”.

A specific inspection procedure will be described below with reference to the flowchart of FIG. 4 and the truth table of the inspection circuit of FIG. First, the output signal of the multi-input NAND circuit 6 is "
Observe the logic level of the DCT "signal (step 1),
If "Low", it is normal, and if "High", it is considered that some abnormality (such as mounting failure) has occurred (step 2). Next, the “DCT” signal is “Hig
h ”, a NAN is used to identify the location where the defect has occurred.
Only the "DCT (2n-1)" signal (odd number), which is the output signal of the D circuit 5, is observed (steps 3 and 4). Here, for example, only the signal of “DCT3” is “Hig
h "(step 5), it is" NC-IN2 "or" NC-I "
N3 ".

Furthermore, in order to specify a defective portion, "DCT"
3 “DCT2” and “DCT” before and after the signal.
4 is observed (step 6). "DCT2" =
If “High” and “DCT4” = “Low”, “
It is considered that a defect has occurred in “NC-IN2” (steps 7 and 8), and “DCT4” = “High”
h ”and“ DCT2 ”=“ Low ”, then“ NC-I ”
It is considered that a failure has occurred in N3 ″ (steps 9 and 10).

As described above, the "DCT" signal and the "DCT"
By observing the "(n)" signal, it is possible to detect which terminal is at the "Low" level among the unused input terminals fixed at the "High" level. Can be easily identified. In addition, since the inspection is performed while narrowing down the terminal where the abnormality has occurred,
Inspection time can also be reduced.

When the output terminal of FIG. 1 is used in a normal operation state, it is necessary to use the switching circuit 3 to switch to the normal operation mode. The description with reference to FIG.
It is possible to switch between the normal operation state and the inspection state by the “LECT” signal.
When the “T” signal is set to “High” level, normal signals “SIG1 to 7” are output from “OUT1 to 7”, and “
When the “SELECT” signal is set to “Low” level,
The inspection signals “DCT1 to 6” and “DCT” are output to “OUT1”.
7 is output as described above.
The ECT "signal makes it possible to switch between the normal operation state and the inspection state.

[0019]

As described above, according to the present invention, L
When the logic level (voltage level) of an unused input terminal is fixed in the SI, it is possible to detect that the logic level has become unstable due to a mounting failure or the like. Can be detected. Further, by devising the inspection procedure, the inspection is performed while narrowing down the terminal in which the abnormality has occurred, so that the inspection time can be reduced. Further, it is possible to switch between the inspection state and the normal operation state.

[Brief description of the drawings]

FIG. 1 is a block diagram of an LSI according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing a truth table of the NAND circuit according to one embodiment of the present invention;

FIG. 4 is a flowchart showing an operation (inspection procedure) according to the embodiment of the present invention;

FIG. 5 is a diagram showing a truth table of the test circuit according to the embodiment of the present invention;

FIG. 6 is a circuit diagram showing the operation of one embodiment of the present invention.

FIG. 7 is a block diagram of a conventional LSI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LSI 2 Inspection circuit 3 Switching circuit 4 Internal circuit 5 NAND circuit 6 Multi-input NAND circuit

Claims (3)

[Claims] An inspection circuit is provided inside an LSI, and when the logic level of an unused input terminal of the LSI becomes abnormal due to a mounting defect or the like, the inspection circuit detects that fact. An LSI design method for mounting inspection, wherein the method is capable of detecting at which terminal an abnormality has occurred, as well as possible. 2. A test circuit comprising a logic circuit,
2. The L for mounting inspection according to claim 1, wherein a logic circuit is prepared by the number of SI terminals to detect which terminal is abnormal.
SI design method. 3. An LSI design method for mounting inspection according to claim 1, further comprising a switching circuit capable of switching between two modes (a mode for performing an inspection and a mode for a normal operation state). .