JPH07151830A - Fault detection circuit - Google Patents

Abstract

PURPOSE:To easily detect a fault in a state that a highly integrated LSI has been mounted on a board regarding a fault detection circuit used to inspect the LSI mounted on the board. CONSTITUTION:In the circuit which detects a fault in an LSI mounted on a board in a mounted state, a test signal 3 which is input to an input pin 2 from a test land 4 and an ordinary operating output 6 from a logic circuit 5 are changed over according to an operating mode 7. Thereby, a test output is output directly to an output pin 9 from an output selector circuit 8. When a signal at a test land 11 connected to the output pin 9 is detected, a fault which is caused due to a mounting operation can be detected easily. In addition, the fault can be detected easily by the test signal whose pattern is comparatively short.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection circuit for detecting a failure of a highly integrated LSI mounted on a substrate.

[0002]

2. Description of the Related Art In recent years, as digital circuits have become highly integrated and at the same time, digitalization of signal processing circuits has advanced, fault detection on board mounting has become a major issue.

The structure of a conventional failure detection circuit for an LSI mounted on a board will be described with reference to FIG. In this failure detection circuit, when an LSI is mounted and then an inspection is performed, a test land group 101 provided on the substrate using a push-up jig or the like is used.
From the test signal 102 to the input pin group 1 of the LSI 103
Enter 04. In the LSI 103, an output signal that has undergone normal signal processing by the internal logic circuit 105 is output from the output pin group 106. An output test signal 108 is output from the output test land 107 using a push-up jig or the like.
To detect. By analyzing the output test signal 108, it is possible to detect a mounting failure such as a defective soldering of the input pin or the output pin or a short circuit between the pins.

[0004]

However, in the above configuration, since the normal signal processing is performed on the test signal input to the LSI, in order to detect the mounting defect of the input pin and the output pin, The test signal must be created in consideration of the signal processing of the actual operation, and the test signal also becomes long.

An object of the present invention is to provide a failure detection circuit which can easily detect a failure on a board with a relatively easy circuit configuration.

[0006]

In order to solve the above-mentioned problems, a first invention is to provide a first test land for inputting a test signal to an input pin of an LSI mounted on a substrate, and the inside of the LSI. An output selector circuit for switching the test signal and a normal operation output output from a logic circuit inside the LSI according to an operation mode, and a first for detecting an output signal of the output selector circuit output from an output pin of the LSI. The failure detection circuit is provided with two test lands and detects a failure in mounting of an input pin and an output pin of an LSI.

The second invention, in addition to the first invention,
The failure detection circuit is characterized in that an input selector circuit is provided for switching a plurality of test signal groups according to a failure inspection mode.

Further, in addition to the second aspect of the present invention, the third aspect of the present invention is characterized in that a flip-flop that receives the output signal of the input selector circuit and operates by a clock signal input from the outside of the LSI is provided. It is a fault detection circuit.

[0009]

The present invention has a highly integrated LSI having the above-mentioned configuration.
With the board mounted on the board, a test signal externally input to the LSI can be directly output to the output pin.

Therefore, it is possible to easily detect a mounting failure that occurs when the LSI is mounted on the substrate, with a short test signal. Further, since the circuit can be configured with a relatively easy circuit, the failure detection circuit can be easily incorporated in the LSI.

[0011]

【Example】

(Embodiment 1) First, an embodiment of the first invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the first invention.

Input pin 2 of LSI 1 mounted on the board
The first test land 4 for inputting the test signal 3 to the
The test signal 3 in the SI 1 and the normal operation output 6 output from the logic circuit 5 in the LSI 1 are set in the operation mode 7
And an output selector circuit 8 for switching the output selector circuit 8 and a second test land 11 for detecting the output signal 10 of the output selector circuit 8 output from the output pin 9 of the LSI 1. By comparing the detected test signal output 12 with the LSI,
It is possible to detect a failure in the mounting of the input pin and the output pin of the.

If there is no problem in mounting on the board, the test signal 3 input from the first test land 4 is directly output to the output pin 9 without being processed by the logic circuit inside the LSI. . Therefore, the test signal used for the failure detection can be generated without considering the logic circuit inside the LSI, so that the failure detection can be easily performed with a relatively short pattern.

(Embodiment 2) First, an embodiment of the second invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the second invention. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

The first test land group 16 for inputting the test signal group 15 to the N input pin groups 14 of the LSI mounted on the board and the test signal group 15 inside the LSI 1
An input selector circuit 18 that switches the output signal 19 according to the failure inspection mode 17
And the normal operation output 6 output from the logic circuit 5 inside the LSI 1 are switched by the operation mode 7 to select the test signal used in the failure inspection mode 17 from the test signal group 15.

This makes it possible to detect a failure in mounting the input pin and the output pin. Also,
According to the second embodiment configured as described above, compared with the first embodiment, even when the total number of input pins of the LSI for detecting a failure is larger than the total number of output pins, the test signal input inside the LSI is increased. Faults can be detected by switching between. Further, it can be realized by a relatively easy circuit.

(Embodiment 3) First, an embodiment of the third invention will be described with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the third invention. Further, the same parts as those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the third embodiment, in addition to the second embodiment, the output signal 19 of the input selector circuit 18 is used as an input, and the input selector circuit output from the flip-flop 22 latched by the clock signal 21 input from the outside of the LSI is used. By switching the output latch signal and the normal operation output 6 output from the logic circuit 5 inside the LSI according to the operation mode 7, the change of the test signal output 12 is controlled by the clock signal 21 regardless of the change of the test signal group 15. be able to.

As a result, as compared with the first and second embodiments, even when different input pins of a plurality of LSIs are connected to the same test land, the clock signal of the flip-flop is controlled. ， It is possible to output different test signals. Further, it is possible to share a test land for test input with respect to a plurality of LSIs, and it is possible to reduce the area occupied by the test land on the mounting board. Further, it can be realized by a relatively easy circuit.

[0020]

As is apparent from the above embodiments, according to the present invention, the test signal input from the outside into the LSI and the normal operation output output from the logic circuit inside the LSI are set to the operation mode. L by switching by
It is possible to easily detect a failure in mounting in the SI mounted state on the board. Further, since the test input used for the fault detection is directly output without being processed by the logic circuit inside the LSI, the test input can be easily generated and the fault detection can be performed with a relatively short pattern.

[Brief description of drawings]

FIG. 1 is a block diagram showing a failure detection circuit according to an embodiment of the first invention.

FIG. 2 is a block diagram showing a failure detection circuit according to an embodiment of the second invention.

FIG. 3 is a block diagram showing a failure detection circuit according to an embodiment of the third invention.

FIG. 4 is a block diagram showing a configuration example of a conventional failure detection circuit.

[Explanation of symbols]

 1 LSI 2 Input Pin 3 Input Test Signal 4 First Test Land 5 Logic Circuit 6 Normal Operation Output of Logic Circuit 7 Operation Mode Signal 8 Output Selector Circuit 9 Output Pin 11 Second Test Land 12 Output Pin 14 Input Pin Group 15 Input test signal group 16 First test land group 17 Fault inspection mode signal 18 Input selector circuit 19 Input selector circuit output 21 Clock signal 22 Flip-flop

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuji Miwa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Tadayuki Masumi, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Yuichi Ishikawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A circuit for detecting a failure in mounting an LSI mounted on a board, comprising: a first test land for inputting a test signal to an input pin of the LSI mounted on the board;
An output selector circuit for switching the test signal inside the LSI and a normal operation output output from a logic circuit inside the LSI according to an operation mode;
A second test land for detecting the output signal of the output selector circuit output from the output pin of
A failure detection circuit characterized by detecting a failure in mounting of an input pin and an output pin of I. 2. A circuit for detecting a failure in mounting an LSI mounted on a board, wherein the N of the LSI mounted on the board is detected.
A first test land group for inputting a test signal group to each input pin group, an input selector circuit for switching the test signal group in the LSI according to a failure inspection mode, an output signal of the input selector, and an inside of the LSI. An LSI includes an output selector circuit that switches a normal operation output output from a logic circuit according to an operation mode, and a second test land for detecting an output signal of the output selector circuit output from an output pin of the LSI. Failure detection circuit characterized by detecting a failure in mounting of the input pin and the output pin of the. 3. A circuit for detecting a failure in mounting an LSI mounted on a board, wherein the N of the LSI mounted on the board is detected.
A first test land group for inputting a test signal group to each input pin group; an input selector circuit for switching the test signal group in the LSI according to a failure inspection mode; and an output signal of the input selector as an input, LS
A flip-flop that operates with a clock signal input from the outside of I, an output latch signal of the input selector circuit that is output from the flip-flop, and a normal operation output that is output from the logic circuit inside the LSI are switched according to the operation mode. An output selector circuit and a second test land for detecting an output signal of the output selector circuit output from the output pin of the LSI are provided, and a failure in mounting the input pin and the output pin of the LSI is detected. And the fault detection circuit.