JPH0331233B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scan pass circuit, and more particularly to a scan pass circuit that tests a logic unit incorporating a scan pass by supplying a scan clock from the outside and scan data whose bits change in response to the scan clock.

In recent years, with the adoption of large-scale integrated circuits (LSI) in information processing equipment, the integration of logic circuits, logic devices, and processors has become more prominent, making it possible to integrate highly complex logic functions with high density. On the other hand, testing for failures in these logic units has become increasingly difficult due to the complexity of circuits and devices and restrictions on the number of input/output terminals of LSIs. For this reason, the configuration of such a logic unit is sometimes devised in advance so that it can be easily tested for failures.

Conventionally, this type of scan pass circuit is called the so-called scan pass method, in which a signal is used to switch between normal operation and failure test operation, and a group of flip-flops that serve as internal storage elements for normal sequential circuit operation are interconnected. A shift register (scan path) is constructed using the 3D circuit, making it possible to separate sequential circuits into combinational circuits and test them. Scan data supplied in bit series from the tester to the logic unit under test is output via a scan path, and this output data is compared with expected value data for the scan data in the tester and tested.

In such a conventional configuration, even if an error occurs due to a failure in the data transfer path between the tester and the logic unit, the tester determines that the error is due to a failure in the logic unit, resulting in incorrect test results. It has the disadvantage of causing In particular, when using a maintenance processor as a tester to test a processor such as a central processing unit or input/output control unit, the data transfer path becomes long and large-scale, so the above-mentioned drawbacks are exacerbated. That will happen.

The purpose of the present invention is to be able to isolate faults in the logic unit under test and the data transfer path, and
The object of the present invention is to provide a scan pass circuit that can perform appropriate error processing.

The circuit of the present invention is a scan circuit that can test a logic unit with a built-in scan path by externally supplying a scan clock and scan data whose bits change in synchronization with the scan clock, and which adds parity to the scan data at fixed bit intervals. a counter located near the logic unit that counts the constant bit interval length of the scan data as a maximum count value from the time when the scan clock is applied; an error detection circuit that performs a data parity check; and a gate circuit that generates a set clock that blocks passage of the scan clock only at each maximum count value and inputs the scan data to the scan path in response to the set clock. and a parity generation circuit that generates parity based on output data from the scan path, and a multiplexer that outputs the parity from the parity generation circuit for each of the maximum count values and outputs the output data at other times. It is characterized by:

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing one embodiment of the present invention, this embodiment includes a counter 1, a parity check circuit 3, a flip-flop 4, a parity generation circuit 8, a multiplexer 9, two shift registers 2 and 7, An inverter 5 and an AND circuit 6 are provided in the same package as the logic circuit 10, and a scan clock 11 and scan data 12 whose bits change in synchronization with the scan clock 11 are supplied in bit series from a tester (not shown). This is a test system for testing a logic circuit 10. The logic circuit 10 includes flip-flops 101, 102, 103...1
0N (N is any integer), and constitutes a scan path in this order.

Scan data 12 consists of 8 data bits and a parity bit added to the end, totaling 9 bits.
It is made up of bits. Counter 11 is 9
It is a forward counter that counts the number of clocks of the scan clock 11 in response to the rising edge of the waveform of the scan clock 11, and outputs an 8 count signal 13 when counting 8 times and a 9 count signal 14 when counting 9 times. .

The shift register 2 inputs the scan data 12 one bit at a time in synchronization with the scan clock 11, and outputs the bits in parallel to the parity check circuit 3 after the input is completed. The parity check circuit 3 performs a parity check on the scan data input from the shift register 2 in response to the 9 count signal 14.
If a parity error is detected as a result of the parity check, a parity error signal 19 is sent to the tester.

The flip-flop 4 is always in the reset state and outputs "0", so the inverted output 15 of the flip-flop 4 and the scan clock 11
satisfies the AND condition in the AND circuit 6,
A set clock 16 is output. counter 1
When the flip-flop 4 outputs the 8 count signal 13, the flip-flop 4 becomes set in response to the inverted signal (by the inverter 5) of the scan clock 11 and outputs "1". Therefore, the AND circuit 6 cannot perform an AND operation, and only at this time the set clock 16 is blocked.

During normal operation, the logic circuit 10 performs a series of logical operations under the control of a control means (not shown), and during testing, it sets scan data 12 on a scan path in which N flip-flops from flip-flop 101 to flip-flop 10N are connected in series. 16, and the result of the response to this scan data 12 is output as scan output data 17 in bit series. As mentioned above, since the set clock 16 is blocked when the 8 count signal 13 is generated, that is, at the parity bit of the scan data 12, the parity bit is not input to the scan path.

The shift register 7 inputs the scan output data 17 one bit at a time in synchronization with the set clock 16, and outputs the bits in parallel to the parity generation circuit 8 after the input is completed. Parity generation circuit 8 generates parity based on scan output data 17 input from shift register 7 and outputs it to multiplexer 9 .

The multiplexer 9 outputs the scan output data 17 while the 8 count signal 14 is not generated, and when the 8 count signal 14 is generated, that is,
When the parity generation circuit 8 generates parity, it receives each parity and sends both of them as output data 18 in bit series to the tester.

FIG. 2 shows a waveform diagram of the important parts of the circuit described above.

Now, when testing the logic circuit 10, the tester supplies the scan clock 11 and a series of scan data 12, and the tester compares the output data obtained as described above with the expected value data for the series of scan data 12. . This comparison is performed only on the data bits of the scan data 12.

As a result of the comparison in the tester, if both data match, it is determined that no error has occurred in the logic circuit 10. When the two data do not match, it is assumed that an error has occurred in the logic circuit 10, and a fault diagnosis is performed based on the comparison result.

Further, if the parity error signal 19 is input, it is assumed that there is a failure in the forward data transfer path to the tester, and if the parity error signal 19 is not input, the forward data transfer path is considered to be normal. The output data 18 is also subjected to a parity check in the tester, and is also used to detect failures in the data transfer path to and from the tester.

According to the present invention, by employing the above-described configuration, it becomes possible to isolate failures between the logic unit to be tested and the data transfer path, so that appropriate error handling can be performed.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a waveform diagram of the embodiment. 1... Counter, 2, 7... Shift register,
3... Parity check circuit, 4... Flip-flop, 5... Inverter, 6... AND circuit, 8...
...Parity generation circuit, 9...Multiplexer, 1
0...Logic circuit, 11...Scan clock, 1
2...Scan data, 13...7 count signal, 14...8 count signal, 15...Inverted output of flip-flop 4, 16...Set clock, 17...Scan output data, 18...Output data, 19... Parity error signal, 101,
102, 103,...10N...Flip-flop.

Claims (1)

[Scope of Claims] 1. In a scan pass circuit capable of testing a logic unit with a built-in scan pass by externally supplying a scan clock and scan data whose bits change in synchronization with the scan clock, parity is determined at fixed bit intervals of the scan data. a counter which performs the supply in addition to the above, and is located near the logic unit, and performs a count from the time when the scan clock is applied to the constant bit interval length of the scan data as a maximum count value; an error detection circuit that performs a parity check on scan data; and a gate that generates a set clock that blocks passage of the scan clock only at each maximum count value and inputs the scan data to the scan path in response to the set clock. a parity generation circuit that generates parity based on output data from the scan path; and a multiplexer that outputs the parity from the parity generation circuit for each of the maximum count values and outputs the output data at other times. A scan pass circuit is provided.