JPH0298218A - Data compression circuit - Google Patents

Abstract

PURPOSE:To improve the reliability by forming the circuit with two sets of shift registers and a feedback loop not including a NOT element reaching an input line of the shift registers, and receiving an output of the registers, an external data input signal and its NOT signal. CONSTITUTION:The circuit consists of two sets of shift registers 1, 2 and a feedback loop 3 receiving a data input signal DI from an output line of registers 11-15, 21-25 forming the shift registers 1, 2 and an external wire and receiving its NOT signal, inverse of D1 and a feedback loop 3 not including a NOT element reaching the input line of the shift registers 1, 2. Even if a single direction multiple fault takes place in the inside of the data compression circuit, since no NOT element is included, bits of corresponding shift registers due to a fault are not both inverted, and at least one bit is not effected with a fault. Accordingly, there is no case where the data being compressed is incorrect and the data cannot be detected, the system with high reliability is built up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data compression circuit, particularly a circuit that compresses a 1-bit serial data series, and more specifically, to a circuit that compresses a 1-bit serial data series, and more specifically, to a circuit that compresses a unidirectional multiple fault in the circuit. This invention relates to a data compression circuit that does not output erroneous data even if it occurs.

[Conventional technology]

In built-in self-testing in which a fault detection circuit is mounted on an LSI chip or board, the output sequence when a test input sequence is added to the circuit under test is compressed, and then compared with a reference value. It is often done to determine the presence or absence of a failure.

In this case, the data compression circuit is an LFSR that determines the feedback structure according to the given generator polynomial.
(linear feedback shift register) is often used. For example, in Fig. 4, the generating polynomial is Xs+XS
This is the configuration of the LFSR in the case of +X3+X+1. In FIG. 4, the shift register consists of eight registers 101 to 1.
08, the feedback loop is also composed of four exclusive OR gates 31-34. The input data input signal DI is compressed by the shift register and feedback loop having the above configuration, and the data output signal Do can be taken out from the LFSR as compressed data.

[Problem to be solved by the invention]

However, with conventional LFSRs, if a failure occurs inside the LFSR, the correctness of the compressed data is not guaranteed, and even if there is a failure in the circuit under test, the compressed data will not fail. It could happen that it would match the case where it does not exist.

In other words, there were cases in which a failure in the circuit under test could not be detected due to a failure in the LFSR.

Therefore, a method has been considered in which failures in the LFSR are detected by lining up two identical LFSRs and comparing the results, but even with this method, unidirectional multiple failures occur inside the data compression circuit. If it exists, the correctness of the compressed data cannot be guaranteed.

Therefore, even if the above method is used, it will be affected by unidirectional multiple faults, and when used for data compression for determining the presence or absence of faults in the circuit under test as described above. However, due to such unidirectional multiple faults, the existence of faults in the circuit under test may be overlooked, which also results in a lack of reliability.

An object of the present invention is to provide a data compression circuit that can eliminate the influence of unidirectional multiple faults even if they exist in the data compression circuit and improve reliability. There is a particular thing.

[Means to solve the problem]

The data compression circuit of the present invention has two sets of shift registers, the outputs of the registers constituting these shift registers, an external data input signal, and its negation signal as input,
It is characterized by consisting of a feedback loop that does not include a negative element and reaches the input line of the shift register.

[Effect]

In the present invention, two sets of shift registers are provided, and a data compression circuit is configured without using a negative element.
If the configuration is configured without using a negation element, even if a unidirectional multiple fault occurs inside the data compression circuit, the corresponding pinto values of both shift registers will be lost due to the failure because no negation element is included. are never inverted, and the value of at least one of the bits is not affected by a fault. Therefore, in the present invention, even if there is a fault inside the data compression circuit, the compressed data remains unchanged. With two sets of shift registers, it is possible to maintain the relationship of inverted values while ensuring that no errors occur.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data compression circuit of the present invention.

As shown in FIG. 1, the data compression circuit includes two sets of shift registers 1.2 and a feedback loop 3 that does not include a negative element.

The shift register 1.2 receives the two outputs of the feedback loop 3 as inputs, and the feedback loop 3 receives the registers 11 to 15 .
21 to 25 output lines and external data input signal DI
and its negation signal DI are input. Further, as outputs of the data compression circuit, a data output signal Do as compressed data and a negation signal DO as its negation value are sent out from two data output lines.

In this way, the data compression circuit has two sets of shift registers 1 and 2, the output lines of the registers 11 to 15, 21 to 25 constituting the shift registers 1 and 2, and the external data input signal DI and its negation. The feedback loop 3 receives the signal DI and does not include a negation element and extends to the input line of the shift register 1.2.

According to the data compression circuit with such a configuration, even if a unidirectional multiple fault occurs inside the circuit,
It is possible to solve the problem of not being able to guarantee the correctness of compressed data as in conventional methods.

This focuses on the following points.

In the feedback loop of the data compression circuit, it is necessary to realize an exclusive OR function, but two sets of shift registers are provided, and one shift register is always set to the inverted value of the contents of the other shift register. By doing so, it is possible to realize an exclusive OR function without using a negation element. In other words, when a negative value of a signal line consisting of Obtainable.

Consider the case where a unidirectional multiple fault, that is, a stuck-at-0 fault in a plurality of signal lines or a stuck-at-1 fault in a plurality of signal lines occurs inside a data compression circuit configured without using any negation elements. In the case of a stuck-at-0 fault, the value inside the shift register, which should be "1" under normal conditions, becomes "1" due to the fault.
There is a possibility that the value becomes 0, but since it does not include a negation element, a malfunction will not cause a 0 to become a 1. In other words, the values of the corresponding bits in both shift registers are both inverted. The value of at least one of the bits is not affected by the fault.The same is true for a stuck-at-1 fault, where the values of the corresponding bits of both shift registers change due to the fault. It is impossible to put it away.

The data compression circuit according to the present invention utilizes this fact, and even if there is a failure inside the data compression circuit, the compressed data maintains the relationship of inverted values in the two sets of shift registers and does not become erroneous. I can guarantee that.

In other words, when a unidirectional multiple fault occurs in a data compression circuit, conventionally, even if two identical LFSRs are arranged and the results are compared, the fault in the LFSR is detected. However, in the case of this data compression circuit, based on the principle described above, the data in the two shift registers 1 and 2 after compression are both It is possible to detect errors in data due to discrepancies between two pieces of data, without causing incorrect values and their negative values. Therefore, it has a high degree of reliability even in the case of unidirectional multiple faults. To provide a data compression circuit in which the presence of a fault in a circuit under test is not overlooked due to unidirectional multiple faults in the data compression circuit even when determining a fault in the circuit under test. Can be done.

Figure 2 shows that the generator polynomial for data compression is X8+X'+
This is a specific example of a data compression circuit according to the present invention in the case where 8 registers 101 to 1 are
08 and 201 to 208, a feedback loop consisting of four exclusive OR circuits 301 to 304 that do not include negation elements, and an input line for the data input signal DI. It is composed of an input line for the negation signal DI, an output line for the data output signal Do, and an output line for the negation signal DO.

In the case of the configuration shown in Figure 2, the input data sequence of arbitrary length is processed by a shift register and a feedback loop.
The data is compressed to the length of the focus, and then the compressed data and its negative value can be read out from the two data output lines.

A feedback loop that does not include a negation element, in this example a feedback loop that consists of exclusive OR circuits 301 to 304, can be specifically realized by the following configuration.

That is, FIG. 3 shows an example of the internal configuration of an exclusive OR circuit that does not include a negation element. As shown in FIG.
, 12 and its negative value 11.12 are input, and the signal value 11
, ■ A function that outputs the exclusive OR of 2 and its negation value of 0 is created by OR gates 41 and 42 and AND gates 51 to 54.
This is achieved without using any negation elements.

In this way, in this data compression circuit configured without using any negative elements, even if a unidirectional multiple fault occurs inside the circuit, the data in the two shift registers after compression is The data will not both be an incorrect value and its negative value, and it is possible to detect an error in the data based on a mismatch between the two pieces of data.

In addition, in the above, the generating polynomial is XII+XS+X30X+
1, but even if other generator polynomials are given, if two shift registers of length equal to the degree of the generator polynomial are used, and there is a first-order term in the generator polynomial, then n counting from the input side of the shift register
By configuring the output of the th register to be fed back to the input of the shift register while performing exclusive OR with the feedback line, a circuit configuration for any generator polynomial can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, even if there is a unidirectional multiple fault in the data compression circuit, there is no possibility that the compressed data is incorrect and cannot be detected. This is useful when constructing a sexual system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the data compression circuit of the present invention, FIG. 2 is a diagram showing the configuration of a specific example thereof, and FIG. 3 is a diagram showing an example of an exclusive OR circuit that does not include a negation element. , FIG. 4 is an explanatory diagram of the conventional method. 1.2...Shift register 3...Feedback loop 11~15.21~25.101~108.201~2
08...Register

Claims (1)

[Claims] (1) Two sets of shift registers, inputting the outputs of the registers constituting these shift registers, an external data input signal, and its negation signal,
A data compression circuit comprising a feedback loop that does not include a negation element and reaches an input line of a shift register.