JP2725706B2 - In-device monitoring system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-device monitoring system for monitoring a device by inserting a test pattern into an empty bit of a main signal.

[Conventional technology]

2. Description of the Related Art Conventionally, as shown in FIG. 2, this type of in-apparatus monitoring system has been provided with test pattern check circuits 11, 12, and 13 on a main signal line 110 at predetermined intervals to perform in-apparatus monitoring.

[Problems to be solved by the invention]

The conventional in-device monitoring system described above has a problem that the error is propagated as is apparent from FIG. 2 and a problem that the fault location cannot be clarified because the error propagates. Atsuta.

[Means for solving the problem]

In the in-apparatus monitoring system according to the present invention for monitoring an apparatus by inserting a test pattern into an empty bit of a main signal, the first test pattern output from the first test pattern generation circuit and the first main signal are compared with each other. A first test pattern insertion circuit for inputting and inserting a first test pattern into a vacant bit of the first main signal and outputting the same as a second main signal; A test pattern check circuit for checking a pattern, a second test pattern output from a second test pattern generation circuit, and a second main signal are input and inserted into empty bits of the second main signal. A second test pattern insertion circuit that replaces the first test pattern with a second test pattern and outputs the second test pattern as a third main signal; a second main signal, a third main signal, and a test pattern Inputs the switching control signal outputted from the Ekku circuit is obtained by providing a switching circuit for switching the second main signal and the third main signal.

[Action]

In the present invention, propagation of a main signal in a state where an error has occurred in a test pattern is suppressed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an in-apparatus monitoring apparatus for explaining an embodiment of an in-apparatus monitoring system according to the present invention.
In the figure, a first test pattern insertion circuit 1
The main signal 101 and the first test pattern 102 output from the first test pattern generation circuit 2 are input, and the first test pattern 102 is inserted into an empty bit of the first main signal 101 and output. . The test pattern check circuit 3 is the first
The second main signal 103 output from the test pattern insertion circuit 1 is inputted to check the test pattern.
The second test pattern insertion circuit 4 outputs the second test pattern 104 output from the second test pattern generation circuit 5.
And the second main signal 103 are input, and the test pattern inserted in the empty bit of the second main signal 103 is replaced. The switching circuit 6 receives the second main signal 103, the third main signal 105 output from the second test pattern insertion circuit 4, and the switching control signal 106 output from the test pattern check circuit 3 as a second input. Switching between the main signal 103 and the third main signal 105 is performed.

 Next, the operation will be described.

First, the main signal 101 is input to a first test pattern (hereinafter referred to as TP) insertion circuit 1. The first TP 102 output from the first TP generation circuit 2 is also input to the first TP insertion circuit 1, and the first TP 102 is inserted into an empty bit of the main signal 101. The second main signal 103 into which the first TP 102 has been inserted is input to the TP check circuit 3, where the TP is checked. TP
Of the switching control signal 106
Is output as The second main signal 103 is input to the second TP insertion circuit 4. The second TP, which is the output of the second TP generation circuit 5, is also input to the second TP insertion circuit 4, where the first TP 102 inserted in the first main signal 103 is converted to the second TP.
It is replaced with TP 104 and output as the third main signal 105. Now, suppose that the first TP insertion circuit 1 and the second TP insertion circuit 4
Even if there is an error in the TP between the new second
By replacing the TP 104, the TP error will be eliminated. The switching circuit 6 receives the second main signal 103, the third main signal 105, and the switching control signal 106 as inputs. The switching circuit 6 outputs the third main signal 105 when there is an error in the TP of the second main signal 103, and outputs the second main signal 103 when there is no error in the TP of the second main signal 103. Operates as it is. The switching circuit 6 is adapted to switch the second main signal
Switching control signal 106 as a result of checking TP of 103
Is controlled by

〔The invention's effect〕

As described above, according to the present invention, the replacement of the test pattern inserted in the empty bit of the main signal and the check are performed, and the result of the check of the test pattern is used as a control signal as a control signal and the main signal which is not replaced. By switching between the main signal and the test pattern, the main signal having an error in the test pattern can be prevented from continuing to propagate. Also,
When the present invention is connected in multiple stages, there is an effect that the output of the test pattern check circuit is monitored to determine the error occurrence section.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an in-device monitoring system according to the present invention, and FIG. 2 is a block diagram showing a conventional example. 1... First test pattern insertion circuit, 2... First test pattern generation circuit, 3... Test pattern check circuit, 4... 2nd test pattern insertion circuit, 5. Circuit, 6 Switching circuit, 10
1 ... first main signal, 102 ... first test pattern, 10
3 ... second main signal, 104 ... second test pattern, 10
5 ... third main signal, 106 ... switching control signal, 107 ...
... the fourth main signal.

Claims (1)

(57) [Claims] A first test pattern output from a first test pattern generation circuit and a first main signal, wherein the first test pattern is output from a first test pattern generating circuit; And inserts a first test pattern into empty bits of the first main signal,
A first test pattern insertion circuit that outputs the main signal of the first test pattern, a test pattern check circuit that receives the second main signal and checks the first test pattern, and an output from the second test pattern generation circuit. Receiving the second test pattern and the second main signal,
A second test pattern insertion circuit that replaces the first test pattern inserted in the empty bit of the main signal with the second test pattern and outputs the second test pattern as a third main signal; And a switching circuit that receives the switching control signal output from the test pattern check circuit and switches between the second main signal and the third main signal. In-device monitoring system.