JPS5916303B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device used in an electronic computer or the like, and more particularly to a data processing device that detects failures using parity bits.

Conventionally, fault detection in logic circuits in electronic computers has been carried out by using the widely known parity check method based on parity prediction, or by duplicating devices without adding parity bits to detect faults. .

However, in the former case, as logic circuits are becoming more and more integrated into LSIs, the mounting space occupied by the hardware for parity prediction becomes enormous compared to the hardware for failure detection.
The latter method has the disadvantage that it requires both a fault detection hardware and a target hardware. FIG. 1 shows the configuration of a device that employs the latter duplex method.

Of the operand data held in the A register 1, B register 2, and C register 3, two data to be added are selected by the register selection circuit 4 and input to the binary adder 5.

The added result is given to the D register 6, and the output data is sent to the coincidence detection circuit T. The other E register 8, F register 9, G register 10, register selection circuit 11, and binary adder 12 are duplicated in the same manner as in the above series of operations.
operates, the addition result is given to the H register 13, the output data is sent to the coincidence detection circuit T, and the output from the D register 6 and the output from the H register 13 are compared to determine whether or not a fault has occurred. The purpose of the present invention is to duplicate only the minimum necessary logic circuits and perform a parity check by merging the resulting data bits from one logic circuit and the resulting parity bits from the other logic circuit. It is an object of the present invention to provide a data processing device which eliminates the drawbacks of the conventional device by maintaining a fault detection rate equivalent to that of the conventional device and reducing the amount of fault detection hardware.

The device of the present invention includes a first data holding circuit that holds first data and its parity bit, and a second data holding circuit that holds second data having the same content as the first data and its parity bit. 2 data holding circuits, and the first and second data holding circuits.
the first data and the second data from the data holding circuits respectively.
a duplex arithmetic processing means having two processing means so as to perform the same arithmetic processing on each data supplied with the data; and a parity bit generator for generating a parity bit based on the calculation result from one of the processing means of the duplex arithmetic processing means. The method is characterized in that the processing result of the other processing means of the duplex processing means is used as data, and a parity bit generated from the parity bit generation means is added to this data before being transmitted.

Next, the present invention will be explained in detail with reference to the drawings. A first embodiment of the present invention shown in FIG. 2 shows an apparatus for performing binary addition and subtraction, in which an A register 21, a B register 22} and a C register hold operand data to which a parity bit P has been added. Out of the 23 outputs, data from 2 of the registers each containing a parity bit to be operated on is input to the register selection circuit 24, and the 2 data selected here are sent to the line 28. Whether or not there is an error in the data input to the binary adders 5 and 12 and the parity check circuit 27, which are provided as data bits excluding the parity bits via the input terminal 29 and the parity check circuit 27. is obtained at the output of the parity check circuit 27.

Binary adders 5 and 12 are connected via the lines 28 and 29.
The data bits input to the register 26 are operated on by the binary adders 5 and 12, and the resulting data bits are given from the binary adder 5 to the D register 26.
The output of the parity generation circuit 25 connected to the adder 12 is obtained, and the result obtained by adding the parity bit to the data bit is obtained in the D register 26 as an operation result. The output of the D register 26 is supplied on line 32 to the parity check circuit 27, which checks the parity check circuit 27 to determine if there is a failure in the series of logic circuits operating with the binary adders 5 and 12, the parity generator 25 and the D register 26. Check circuit 2
The output of 7 is obtained. In this way, in the present invention, a certain part of the logic circuit (2
By duplicating the advance adders 5 and 12) to generate and check parity bits, it is possible to reduce the amount of hardware detected for failure without deteriorating the failure detection rate.

The second embodiment of the present invention shown in FIG. 3 is a device that performs left shift processing, and this device includes a J register 41, a K register 42, and a shift number designation circuit that inputs the data of the J register 41. 48, and a duplex shift circuit 45 that shifts to the left by the number specified by 48.

The data stored in the K register 42 is sequentially supplied to the duplication shift circuit 45 to the blank portion (ie, the right end) when the data is shifted to the left as described above.

The result shifted by the duplex shift circuit 45 is fed back to the J register 41, and once stored there, a parity bit is added by a parity generation circuit (not shown) in the J register 41. Parity is checked via signal line 43.

Based on the comparison result, it is possible to check whether or not there is a failure in the shift circuit that performs a series of shift operations.

In addition to converting the hardware necessary for performing the shift processing into an LSI, the parity check circuit, parity generation circuit, and duplication processing circuit necessary for failure detection are incorporated into the register C and shift C. Appropriate fault detection can be achieved with fewer additional hardware.

By having a parity check circuit, duplication of some logic circuits, and a parity generation circuit, the present invention makes it possible to obtain a fault detection rate equivalent to a system requiring more fault detection hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional configuration for detecting a failure, FIG. 2 is a diagram showing a first embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention. 1...A register, 2...B register, 3...C register, 4...register selection circuit, 5...binary Adder, 6...
D register, 7... Coincidence detection circuit, 8...
...E register, 9...F register, 10...
...G register, 11...Register selection circuit, 12...Binary adder, 13...H
Register, 21...A register with parity added, 22...B register with parity added, 23...C register with parity added, 2
4...Register selection circuit that selects including the gerity bit, 25...Parity bit generation circuit, 26...D register with parity added, 2
7... Parity check circuit, 28, 29...
...Data bit line, 30, 31...Parity bit line, 41...J register, 42...
... K register, 43, 44 ... Parity check output line, 45 ... Duplex shift circuit,
46...Shift result output data line, 47...
...Shift number specification circuit.

Claims (1)

[Claims] 1. A first data holding circuit that holds first data and its parity bit; and a second data holding circuit that holds second data that has the same content as the first data and its parity bit. and a duplex operation processing means having two processing means supplied with first data and second data from the first and second data holding circuits, respectively, and performing the same arithmetic operation on each data; parity bit generating means for generating a parity bit based on the calculation result from one of the processing means of the arithmetic processing means, the calculation result of the other processing means of the duplex calculation processing means being used as data, and the data A data processing device characterized in that a parity bit generated by the parity bit generation means is added and transmitted.