JPH0691428B2 - Flip-flop circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a flip-flop circuit for temporarily storing information in a logic device, and in particular, α rays emitted from a trace amount of radioactive substances in a semiconductor package material. The present invention relates to a flip-flop circuit improved so that a soft error does not occur due to such reasons.

[Background of the Invention]

FIG. 19 shows an example of the logical configuration of the flip-flop circuit. This circuit outputs the content of the data input 61 applied through the input terminal In ₁ to the positive side output terminal 64 when the clock input 62 applied through the input terminal In ₂ is in the “1” state, It has a function to output the inverted contents of the data input 61 to the output terminal 63 on the negative side. Data when the clock input 62 is "1" before the clock input 62 is in the "0" state. Memorizes the contents of the input 61, stores the stored contents in the positive output terminal 64, and inverts the stored contents in the negative output terminal.
It has a function to output to 63. In the figure, 69
A is an inverter, 66A to 66C are OR gates, 67 is an AND gate,
65 is a feed back line.

FIG. 20 is a conventional circuit configuration diagram for realizing the flip-flop of FIG. This circuit uses an Emitter Coupled Logic (E) as a basic gate.
CL current circuit), constant current source 718,728,738
One gate is formed for each of the above. Focusing on the gate corresponding to the constant current source 718, the input terminal of this gate is the base of each of the transistors 711 and 712, and the NOR output and the OR output are obtained from the common collector of the transistors 711 and 712 and the collector of the transistor 713, respectively. The same applies to the other gates.

Next, the operation corresponding to the AND gate 67 in FIG. 19 will be described with reference to FIG. In the circuit of FIG. 20, the OR output of each of the three gates is obtained from the collectors of the transistors 713, 723, 733 as described above, but in this circuit, the three collectors are commonly connected (703), and the emitter output follower It is output to 64 via the transistor 701. The OR outputs of the three gates are logically ANDed by connection 703. On the other hand, the NOR output of each gate is output via the emitter-follower transistors 714, 724, 734. Since the emitters of these transistors are commonly connected (704), the NOR outputs of the three gates are logically ORed. Be taken. This is equivalent to the negation of the AND output AND by De Morgan's theorem. Therefore, the 20th
The positive side output 64 and the negative side output 63 are obtained by the circuit configuration shown in the same manner as in FIG. For details of the circuits shown in FIGS. 19 and 20, see Japanese Patent Application No. 57-81426.

By the way, in recent years, it has become clear that a memory or a flip-flop circuit causes a soft error due to α rays emitted from a very small amount of radioactive substances in a semiconductor package material. FIG. 21 shows a state where α rays are incident on the semiconductor chip, and shows a case of a bipolar transistor. 126, 127, and 129 are Emitta,
Base and collector regions, 130 is collector 129 and substrate
This is the depletion layer of the PN junction formed by 131. When the α-ray enters, electron-hole pairs are generated along the locus 120.
Among the electron-hole pairs generated in each region, the electron-hole pairs generated in the depletion layer 130 and the substrate 131 have the greatest influence on the circuit operation. Focusing on the electrons, the electrons generated in the depletion layer 130 are attracted and collected by the collector by the electric field of the PN junction. In addition, the electrons generated in the substrate 131 reach the depletion layer 130 by diffusion and thereafter are collected in the collector as in the above. Therefore, the influence of α-ray incidence appears as current noise, and the current flows from the collector of the transistor into which the α-ray is incident to the substrate.

Since the above properties are related to the bipolar transistor, the situation is the same whether it is a memory or a logic LSI. For example, a soft error report on a bipolar memory is reported in the Institute of Electronics and Communication Engineers, Trans.IECE, Vol 63-
C, No.2 (1980-2) (Mitsuda, et al .; "Soft error in high-speed bipolar RAM due to α particles"). On the other hand, regarding the logic (logic) LSI, there is no report that a soft error has occurred. This is because the logic LSI has a larger circuit current and a larger signal amplitude than the memory LSI. However, in the future, as the device becomes more miniaturized and its performance becomes higher, the parasitic capacitance will decrease, so that the amount of accumulated charge will decrease, and soft error will become a problem even in logic LSI.
Furthermore, as a problem peculiar to logic LSIs, since there are many signal pins, CCB (Control
A chip connection method called "LED Collapse Bonding" is being adopted (for example, IEEE J. State Circuit, Vol.
SC-14, No. 5, pp818-822 (1979-11)), in this method, the solder balls are arranged on the entire surface of the chip, but the radioactive isotope (for example, Ra , Am, etc.) can cause a soft error in the logic LSI. Since this solder ball is bonded to the chip, it is impossible to cover the chip with some material to shield the α-rays, and a circuit resistant to the α-rays is required.

As an α-resistant circuit for a logic LSI, there is one previously filed by the present inventors (Japanese Patent Application No. 59-67653), which changes the reference potential of the circuit according to the current noise of the α-ray. Yes, the differential circuit was applied. The differentiating circuit is not necessarily good in terms of the stability of the circuit operation because it relies heavily on the noise waveform.

[Object of the Invention]

Therefore, an object of the present invention is to provide a flip-flop circuit that is resistant to radiation such as α rays and does not cause a soft error.

[Outline of Invention]

Therefore, in the present invention, the first gate circuit to which at least one external input signal is input, and the second gate circuit which receives the output signal of the first gate circuit and gives the signal used as the output of the flip-flop And a third gate circuit, wherein the third gate circuit receives a feedback signal from the second gate circuit and outputs the output signal of the third gate circuit from the second gate circuit. To give to the second
And the third gate circuit and the second gate circuit form a feedback loop.
The first gate circuit includes a plurality of bipolar transistors connected to each other, at least one control electrode of the plurality of bipolar transistors is provided with the external input signal, and at least one of the plurality of bipolar transistors is specified. In a flip-flop circuit configured to give the voltage of the collector of the bipolar transistor as the output signal of the first gate circuit to the second gate circuit, wherein the second gate circuit has a potential of the collector. To prevent the level of the feedback signal from the second gate circuit to the third gate circuit from changing when it temporarily falls below a high level due to a soft error in the particular bipolar transistor. Is configured.

Example of Invention

Prior to the description of the present invention, a problem caused by α rays in a flip-flop circuit will be described in detail by taking a bipolar transistor as an example. FIG. 22 shows the current switching unit of the ECL circuit and shows how the current noise due to α rays is equivalently expressed. In this figure, α rays are incident on the transistor 223, and the noise source is 227. FIG. 23 shows what kind of fluctuation the noise caused by α rays causes in the signal level. 320
Indicates the potential of the collector of the transistor 223 in FIG. 22, for example, and noise such as 321 and 322 is generated by the α-ray noise source 227.

The operation of losing the flip-flop information due to this noise will be described. As shown in FIG. 20, the flip-flop feed back line 65 is connected from the collectors of the transistors 713, 723 and 733 connected in common to the bases of the transistors 722 and 732 which are the input terminals of the gates via the emitter follower transistor 701. Therefore, when α-rays enter any of the transistors 713, 723, 733, the noise shown in Fig.
321,322 occurs, and it is fed back. In that case, even if noise 321 occurs when the potential of the collector is at a low level, the potential is merely lowered to a lower level, so that the low information of the flip-flop is not lost. On the other hand, when the collector potential is at the high level, noise 322 is generated and is fed back, the potential of the feedback back approaches the reference potential V _BB, and when the noise is large, the feedback back potential that should be logically high level. Becomes lower than V _BB , the current in the ECL circuit switches and the information is lost.

Not only ECL circuits, but also other bipolar circuits such as TTL
In (transistor / transistor logic) circuit,
The mechanism of the soft error due to the decrease of the collector potential is similar. In addition, the field effect transistor (FE
Also in the case of T), the source and drain of the FET correspond to the collector layer 129 of the bipolar transistor of FIG. 21, and the same error operation appears. That is, in the case of N channel due to the incidence of α rays, a current flows from the drain to the substrate, and the drain potential drops.

FIG. 1 is a schematic configuration diagram of the present invention. Reference numeral 1 is a circuit forming a feedback loop, which is the minimum unit necessary for storing information. Here, this unit is called a latch, and an input control circuit 2 for supplying input signals Vin ₁ , Vin ₂ etc. to the latch 1 and an output signal from the latch 2
A circuit including an output control circuit 3 for controlling Vout ₁ , Vout _2, etc. is called a flip-flop circuit. The flip-flop circuit of the present invention is a duplicate of an element that causes an error in the elements constituting the feedback loop in the conventional latch so that the latch 1 does not cause a soft error due to α rays or the like. .

The simple duplication on a flip-flop basis doubles the number of flip-flops and further requires an error determination circuit, resulting in a large number of required circuits.

In the present invention, only the element that causes information destruction is duplicated, and the duplicated signal is processed according to the possible error mode. Therefore, the soft error can be effectively reduced drastically while the increase in the number of elements due to the duplication is minimized.

FIG. 2 is an example of the latch 1 used in the present invention. This figure shows the case of RS latch using NOR circuit. For the operation of the conventional circuit such as RS latch, see, for example, Yojiro Yokoi "Digital IC Practical Circuit Manual" (Radio Engineering Co., Ltd.).
Etc. are explained. In FIG. 2, the part added to the conventional circuit is the circuit within the broken line 20. NOR circuit 2
Corresponding to 1,22, it is duplicated by NOR circuits 23,24.
If the NOR circuits 21 to 24 cause an error mode from a logic high level to a low level due to the incidence of α rays,
Since the R circuits 25 and 26 are provided, the error signal is not fed back. For example, when Q is high level, NO
The output of R circuit 22 and 24 is high level, but the circuit 22 or 24
Even if an α ray enters, the OR circuit 26 prevents Q from being at a low level unless the circuits 22 and 24 simultaneously enter an α ray.

The error mode is the same as above, but from Low level to Hig
When there is an error in the h level, as shown in Fig. 3,
Combining the duplicated signals with the AND circuits 35 and 36 can prevent the error signal from being fed back. In FIGS. 2 and 3, the gate forming the latch is NOR, but the same applies to the case of NAND.

FIG. 4 is another example of the latch 1 of FIG. In this figure, the OR circuit 41 and the AND circuit 42 form a feedback loop. The part added to the conventional circuit is the part surrounded by the broken line 40. In the present embodiment, only the AND circuit 42 and the inverter 44 generate an error signal from the logic high level to the low level.
If the signal has a mode and the signal is duplicated, the OR circuit
ORed at 41. The NAND circuit 43 and the inverter 44 can be replaced with a single AND circuit, but the configuration of this embodiment is simpler depending on the elements used. As in the present embodiment, in the present invention, duplication need only be performed for gates that may cause an error.
The increase in the number of elements due to the duplication is minimized.

Similar to FIG. 4, FIG. 5 is for preventing a soft error by adding the circuit 50 to the latch composed of the OR circuit 51 and the AND circuit 52. In the error mode, only AND circuit 52 and inverter 54 change from High level to L, as in FIG.
Can error to ow level.

FIG. 6 is a block diagram of a D-type flip-flop using the latch of FIG. The first of the conventional flip flops
Compared with FIG. 19, it is characterized in that a circuit 60 is added. The input signals of this circuit 60 are the positive side output 64 and the negative side output 63 of this flip-flop circuit, and the negative side output 63.
Is inverted by the inverter circuit 69, so that the OR gate
The two input signals to 68 are logically in phase. Therefore, in normal operation without the influence of α rays, the feed back signal 65 works exactly the same as the flip-flop shown in FIG.

A circuit configuration for realizing FIG. 6 may be as shown in FIG. Here, except for the circuit 70, the configuration is exactly the same as the conventional flip-flop circuit shown in FIG.
The inverter 69 in FIG. 6 corresponds to 71 in FIG. Further, the OR gate 68 in FIG. 6 is logically ORed because the emitters of the transistors 72 and 701 are connected (753) in FIG. Similar to FIG. 6, in FIG. 7 as well, in the normal operation without the influence of α rays, the flip-flop circuit logically operates exactly like the conventional flip-flop circuit.

Next, the operation when the α ray is incident in FIG. 7 will be described. The effect of α rays is that the transistor 713,
When α rays enter the collector of either 723 or 733,
It appears that the potential of the collector is lowered. Therefore, the common collector potential 703 is logically Hig.
There is a problem at the h level. In other words, when the logical high level is lowered due to α-ray noise to the extent that it is considered to be the low level, if it is fed back, the flip-flop will be inverted and information will be lost. In the conventional flip-flop, this inversion cannot be avoided because the common collector potential 703 is fed back through the emitter follower as it is. on the other hand,
In the flip-flop of FIG. 7 according to this embodiment, the circuit 70
The feed back signal 65 is connected to the common collector potential 703 and the inversion signal of the negative side output 63 of the latch by the connection 73.
Made in R. Therefore, even if the common collector potential 703 logically changes from the high level to the low level due to α-ray noise, if the inverted signal of the negative side output 704 remains at the high level, the feedback back signal 65 is at the high level. The latch circuit information is not lost. Negative output 70
Since the inversion signal 74 of 4 is obtained from a transistor different from the common collector potential 703, the inversion signal 74 of the common collector potential 703 and the negative side output 704 is simultaneously High by one α line.
The level cannot be lowered to the low level. On the other hand, when the common collector potential 703 is at the Low level, the negative side output 704 is at the High level, so there is a risk that the 704 will be pulled down due to α ray noise. However, in this case, no error occurs unless α-rays are simultaneously incident on the negative side transistors of the current switch represented by the constant current sources 728 and 738. That is, transistor 721
(Or 722) and 731 (or 732) collectors can simultaneously ignore the probability that α rays are incident. Therefore, the soft error of the latch circuit due to the α-ray incidence is almost negligible.

FIG. 8 shows a method of constructing the circuit 70 in FIG. 7, which uses an ECL circuit in which the constant current source 803 is switched by the transistors 801 and 802.

FIG. 9 shows another construction method of the circuit 70 in FIG. 7, in which the feedback back signal 65 is obtained from the collector of the transistor 901 through the emitter follower.

In the above embodiment, the flip-flop negative side output 63 is used as it is as the input signal to the inverter 71.
That is, the connection OR of the transistors 714, 724, 734 is used, but three transistors are newly provided separately from these transistors, and the transistors 714, 724, 734 are respectively provided.
It is also possible to connect in the same manner as above and input to the inverter 71.

Further, in the above embodiment, the positive output 64 of the latch is the same emitter follower transistor as the feedback signal 65.
Although it is obtained by the 701, it can also be obtained by a separate transistor. That is, the transistor 70
Common collector 703 of transistors 713,723,733 as in 1
Connect the base to and get the positive output 64 from the Emitter.

Another circuit configuration method for realizing FIG. 6 is shown in FIG. In this circuit, the flip-flop negative side output 704 is not used as the input signal to the circuit 70 as shown in FIG. 7, but the negative side collector potentials 11 and 12 of the current switch represented by the constant current sources 718, 728 and 738, respectively. The circuit speed of the feed back can be increased by directly inputting signals 13 and 13 to the circuit 70. At this time, the NOR gate 14 is used instead of the inverter 71. This gate 1
In Fig. 4, the number of inputs of the circuits in Figs.
You can use the circuits shown in Figures 1 and 12. That is, the 7th
In the figure, the OR of the output on the negative side of each current switch is taken and inverted by the circuit 71.
The circuit speed can be increased because it is done with. Also,
As the NOR gate, a circuit such as that shown in Fig. 13 can be used as a combination of stability by using a constant current source as shown in Fig. 11 and high speed by non-thresholding as shown in Fig. 12. Is. Here, the division ratio of the resistors 335 and 336 is determined in consideration of the speedup and the signal level. In addition, the capacitance 338
Is a speed-up capacity and can speed up NOR output.

In the circuit of FIG. 10, the output on the negative side of the latch is not shown, but it can be the same as that of FIG.
Also for the positive side output 64, separate emitter follower transistors can be used for the output and for the feedback as described in FIG.

Another embodiment of the present invention is shown in FIG. Compared with the embodiment of FIG. 6, the present embodiment does not have the OR gate 68, but instead, the number of inputs of the OR gates 66B and 66C is changed from 2 inputs to 3 inputs. If the number of inputs can be increased, this can increase the circuit speed. The specific structure of each gate shown in FIG. 14 can be the same as in the case of the embodiment shown in FIG.

Yet another embodiment of the present invention is shown in FIG. This embodiment differs from the conventional ones in that a vertically stacked ECL circuit, so-called series gate ECL, is provided with a countermeasure against α rays against a flip-flop. In the conventional circuit shown in FIG. 24, the mutual relationships among the data input In ₁ , the clock phase input In ₂ , the latch positive side output 64, and the negative side output 63 are exactly the same as in FIG. In summary, when the clock phase input In ₂ is higher than the reference voltage V _BB2 , a current flows through either transistor of the transistor pair 551, 552 depending on the data input In ₁ . On the other hand, In ₂ is the reference voltage V
When it is lower than _BB2 , current flows in one of the transistors of the transistor pair 553, 554, and the data is retained. The feedback back for holding data is fed back from the positive output 64 of the latch to the base of transistor 553.

An error can occur in this circuit due to α-ray incidence only when α-rays enter the collectors of the transistors 552 and 554 for making the positive side output 64, and only when the output is at high level. .

Therefore, as shown in Fig. 15, transistors 566 and 567 are connected in parallel to transistors 552 and 554, respectively, as a countermeasure against α rays, but the collectors are separated and the load resistances are separately set to 564 and 565, respectively. However, it is logically ORed by the wired OR of the Emitta-Fourois transistors 559 and 568.
As a feedback signal. By doing so, the soft error does not occur unless the α rays are simultaneously incident on the transistors 552 (or 554) and 566 (or 567).

In this embodiment, as the series gate ECL circuit, the data holding transistor pair 553, 554 is configured to give the reference voltage V _BB1 to the bases of 554, but the signals of opposite phases to the bases of the transistors 553 and 554. That is, there may be a method of inserting a differential signal. That is, the transistor
The negative output 63 can also be put in the base of 554.
In this case, by performing the duplication as shown in FIG. 15 in exactly the same manner for the output on the negative side, it is possible to prevent the soft error due to the α ray.

Further, in this embodiment, the latch output and the feedback signal are exactly the same, but as described in the embodiment of FIG. 7, it is possible to connect another emitter follower transistor. It is also possible to separate the flip-flop output and the feed back.

Yet another embodiment of the present invention is shown in FIG. The present embodiment is one of the circuit configurations for realizing FIG.
Unlike FIG. 7, it is the case where only NOR logic can be taken due to the relationship of the power supply voltage and the like. Therefore, the flip-flop negative output 704 is inverted by NOR gate 650 to obtain feed back 65. In this embodiment, the soft error due to the α-ray can occur when the α-ray enters the gate 650. Therefore, a circuit as shown in FIG. 17 is used as the gate 650. This circuit corresponds to FIG. 8 and is a duplication of the portion composed of the transistors 801 and 72 and the resistor 804. The soft error is caused by the transistors 801 and 751.
No error will occur unless α-rays are simultaneously incident on the collector of. Therefore, in reality, the α ray soft error becomes very small.

Instead of FIG. 17, the circuit configuration can be similarly changed corresponding to FIGS.

Up to now, although the embodiment in which the bipolar ECL circuit is mainly duplicated at the transistor level has been shown, it is possible to duplicate not only the ECL but also the TTL circuit in the same way. Fig. 18 shows a duplicated TTL basic gate. If a flip-flop is built using this, the increase in the number of elements will be smaller than if the gate is duplicated. In FIG. 18, transistors 824, 827,
The diode 826 and the resistor 829 are duplicated portions.

Also, unlike the conventional NPN transistor, the case of the PNP transistor is essentially the same, and the operation is the same in terms of the circuit except that the noise current due to the α ray flows from the substrate to the collector. However, since the error mode changes from Low level to High level, the duplicated signal is AND
I need to come up with it.

Further, as described at the beginning of the description of the embodiments, the N-channel FET corresponding to the NPN transistor and the P-channel FET corresponding to the PNP transistor exhibit the same circuit operation with respect to α-ray noise. The concept of the embodiment using the bipolar transistor described in the above can be applied as it is.

〔The invention's effect〕

As described above, according to the present invention, a flip-flop circuit that does not impair the normal latch operation, does not significantly increase the number of elements, is resistant to α-rays, and does not cause a soft error is provided. Can be realized.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of the present invention, FIGS. 2 to 18 are diagrams showing an embodiment of the present invention, and FIGS. 19 to 24 are diagrams showing a conventional circuit. Vin ₁ , Vin ₂ ...... Input signal of flip-flop circuit, Vou
t ₁ , Vout ₂ …… Output signal of flip-flop circuit, 1 ……
A latch that includes a feedback loop with multiple elements,
2 ... Input control circuit, 3 ... Output control circuit, S ... Set input, R ... Reset input, Q ... Positive output, ...
Negative output, 21-24 …… NOR gate, 25,26 …… OR gate,
35,36 …… AND gate, 43 …… NAND gate, 44 …… Inverter, 61 …… Flipflop data input, 62 …… Flipflop positive phase clock input, 62A …… Flipflop reverse phase clock input, 64 …… Positive output of flip-flop, 63 …… Negative output of flip-flop,
20,30,40,50,60,70 …… A circuit added to the α-resistant line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaru Oyamauchi 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Ryo Masaki 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Ltd. In the Central Research Laboratory (72) Inventor Mitsuo Usami 1450, Kamimizuhonmachi, Kodaira, Tokyo Hitachi, Ltd. Computer Business Unit Device Development Center (72) Inventor Toru Kobayashi 1450, Kamimizumoto, Kodaira, Tokyo Hitachi, Ltd. (56) Reference JP-A-56-135251 (JP, A) JP-A-54-94851 (JP, A) JP-A-58-15394 (JP, A) JP-A-61- 170118 (JP, A)

Claims (4)

[Claims] 1. A first gate circuit to which at least one external input signal is input, and a second gate circuit which receives an output signal of the first gate circuit and gives a signal used as an output of a flip-flop. At least a third gate circuit, the third gate circuit receiving a feedback signal from the second gate circuit and providing an output signal of the third gate circuit to the second gate circuit. Thus, the third gate circuit and the second gate circuit are connected to the second gate circuit to form a feedback loop, and the first gate circuit is connected to the plurality of bipolar circuits connected to each other. At least one of the plurality of bipolar transistors, the external input signal being applied to at least one control electrode of the plurality of bipolar transistors. In a flip-flop circuit configured to supply the voltage of the collector of a specific bipolar transistor to the second gate circuit as an output signal of the first gate circuit, the second gate circuit is Preventing the level of the feedback signal from the second gate circuit to the third gate circuit from changing when the potential temporarily drops below a high level due to a soft error in the particular bipolar transistor. Flip-flop circuit configured as. 2. The first gate circuit is logically complementary to the voltage of the collector of the specific bipolar transistor from the collector of another specific bipolar transistor among a plurality of bipolar transistors included therein. A circuit configured to supply a related voltage to the second gate circuit, wherein the second gate circuit uses the complementary voltage to prevent a change in level of the feedback signal. The flip-flop circuit according to claim 1, further comprising: 3. The second gate circuit corresponds to a logical sum of a gate circuit for inverting the complementary voltage and a voltage obtained by the inversion and an output from the collector of the specific transistor. 3. The flip-flop circuit according to claim 2, further comprising a circuit that generates a signal to perform as the feedback signal. 4. An emitter-coupled logic circuit in which the plurality of bipolar transistors of the first gate circuit have their respective emitters coupled to each other and the external signal is applied to the base of one of the bipolar transistors. The flip-flop circuit according to any one of claims 1 to 3, which is configured as follows.