JPH02220141A - Trouble detecting circuit - Google Patents

Abstract

PURPOSE:To detect the trouble of a multiplier only by performing the comparison between the estimating signal for the modulo-3 signal of the final result of multiplication and the correcting signal of the modulo-3 signal obtained by applying the addition of antilogarithm to the carry and the sum, i.e., the outputs of the multiplier. CONSTITUTION:When a carry is produced from the highest ran bit, 2 and 1 are added to a produced modulo-3 signal 38 if the final multiplication result 40 has the even and off bit widths respectively. Then a modulo-3 signal is pro duced again according to the result of correction and outputted as a correction circuit output 39 since >=3 produced modulo-3 signals way sometimes be obtained as the result of correction. Thus a coincidence detecting circuit 56 decides the coincidence or discordance between a pair of produced modulo-3 signals 37 and 39. As a result, the trouble of only a multiplier 50 is detected.

Description

[Detailed description of the invention] 1 Naokuni! The present invention relates to a failure detection circuit, and more particularly to a failure detection circuit for an arithmetic circuit that multiplies two signed data with a modulo 3 signal.

Conventionally, in this type of arithmetic circuit, two signed data accompanied by a modulo 3 signal are input, and these two
In order to calculate the multiplication result of two pieces of signed data, a multiplier that outputs a carry and a sum as an intermediate multiplication result, and an adder that adds the carry and sum are provided.

A failure detection circuit for detecting a failure in such an arithmetic circuit has the following configuration. That is, a prediction circuit that predicts a modulo 3 signal of the final multiplication result using signed data, a modulo 3 signal generation circuit that generates a modulo 3 signal from the final multiplication result, and an output of the prediction circuit and an output of the modulo 3 signal generation circuit. and a coincidence detection circuit for detecting coincidence with the arithmetic circuit, and a failure of the entire arithmetic circuit is detected based on the coincidence detection output.

In such conventional failure detection circuits, failures are detected in the entire arithmetic circuit, so when a failure occurs, it is difficult to determine whether it is a failure in a multiplier or an adder that constitutes the arithmetic circuit. The drawback is that it is impossible.

SUMMARY OF THE INVENTION Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to provide a fault detection circuit that can identify a faulty circuit. There is a particular thing.

According to the present invention, there is provided a multiplier which takes two signed data with modulo 3 signals as input and outputs a carry and a sum as intermediate multiplication results, and a multiplier which takes the carry and sum as input. A failure detection circuit for an arithmetic circuit that includes an adder that adds these and outputs a final multiplication result, a modulo 3 signal prediction circuit that predicts a modulo 3 signal of the final multiplication result, and a modulo 3 signal prediction circuit that predicts a modulo 3 signal of the final multiplication result. a code prediction circuit that predicts the code;
a modulo 3 signal generation circuit that generates a signal; a correction circuit that corrects the output of the modulo 3 signal generation circuit according to the predicted code of the code prediction circuit and code elements included in the carry and sum; and the modulo 3 signal prediction circuit. A failure detection circuit is obtained, comprising a coincidence detection circuit for detecting coincidence between the output of the correction circuit and the output of the correction circuit.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In FIG. 1, a multiplier 5 receives signed data 30.31 and outputs a carry 34 and a sum 35 as intermediate multiplication results.
0, a carry 34, and a sum 35 as inputs and an adder 55 which adds them together, constitutes an arithmetic circuit.

In this arithmetic circuit, the modulo 3 signal of the final multiplication result 40 is converted into a modulo 3 signal with signed data 30.31.
Modulo 3 signal prediction circuit 5 predicting from signals 32 and 33
2 and the sign of the final multiplication result 40 as signed data 30.3
a code prediction circuit 51 that predicts from 1; and a modulo 3 signal generation circuit 54 that generates a modulo 3 signal 38, which is the result of adding the carry 34 and sum 35, which are the outputs of the multiplier 50, from the carry 34 and sum 35. , prediction code 36 and carry 3
4 and the sum 35, and a coincidence detection circuit 56 that detects coincidence between the correction circuit output 39 and the predicted modulo 3 signal 37. And failure detection output 41
A failure in only the multiplier 50 is detected and output.

The sign prediction circuit 51 predicts that the signs of the signed data 30.31 are positive if they are the same sign, and negative if they are different signs. However, if either or both of the signed data 30 and 31 are zero, it is predicted to be positive.

The modulo 3 signal prediction circuit 52 uses signed data 30.31
The 9 multiplication that inputs the modulo 3 signal 32 and 33 associated with , multiplies both data, and outputs the predicted modulo 3 signal 37 follows the logic shown in FIG. 2, that is, if the modulo 3 signal 32 is 0, the modulo Regardless of the value of the 3 signal 33, 0 becomes the prediction modulo 3 signal 37. If the modulo 3 signal 32 is 1, the value of the modulo 3 signal 33 becomes the predicted modulo 3 signal 37 as is. If the modulo 3 signal 32 is 2, the predicted modulo 3 signal 37 is 0, 2.1 for (iiO, 1, 2) of the modulo 3 signal 33. Attached data 3
Since this is a modulo 3 signal that also takes into account the sign of 0.31, a modulo 3 signal that takes into account the sign of the final multiplication result is predicted.

The modulo 3 signal generating circuit 54 generates a modulo 3 signal for the remaining bits excluding the most significant bit of the carry 34, thereby generating a modulo 3 signal for the entire sum 35. Adds the two generated modulo 3 signals and produces a result modulo 3
Output to signal 38.

The addition follows the logic shown in FIG. 3, that is, if the simple addition is performed and the result is 0.1.2, 0°1.2 is directly output to the generation modulo 3 signal 38, and if the result is 3.4, it is output as is. 0.
It is output as 1 to the generation modulo 3 signal 38. These operations treat the final multiplication result as an antilog number, and generate a modulo 3 signal of a numerical value that also includes the carry from the most significant bit in the binary addition process of carry 34 and sum 35. do.

In the correction circuit 53, the predicted code 36, carry 34 and sum 3
The generated modulo 3 signal 38 is corrected by the code element included in the code element 5. The content of the correction follows the logic shown in FIG. 4. First, to clarify the difference between the predicted modulo 3 signal 37 and the generated modulo 3 signal, there are two differences. One is that the predicted modulo 3 signal 37 takes the sign into account, but the generated modulo 3 signal 38 does not take the sign into account, and the other is that the generated modulo 3 signal 38 does not take the sign into account.
This includes the carry from the most significant bit in the binary addition process of 4 and sum 35, but the prediction modulo 3 signal 37
This is not included in the

The correction circuit 53 absorbs these two differences.

First, correction is performed using a sign. If the predicted sign 36 is 1, that is, negative, 2 is added to the generated modulo 3 signal 38. however,
This is the case when the final multiplication result has an even bit width.

If the fiM multiplication result has an odd bit width, add 1.

Next, correction is performed by carrying from the most significant bit in the binary addition process of carry 34 and sum 35.

If there is a carry from the most significant bit, the final multiplication result is 4.
If 0 has an even bit width, 2 is added to the generated modulo 3 signal 38, and if it has an odd bit width, 1 is added to the generated modulo 3 signal 38. In addition, whether there is a carry from the most significant bit can be determined based on the relationship between the predicted code and the code elements included in the carry 34 and the sum 35. As a result of a correction of 0 or more, the generated modulo 3 Since the signal may be 3 or more,
A modulo 3 signal is generated again as a result of the correction, and is output as a correction circuit output 39.

Two sets of modulo 3 signals 37.3 generated in this way
9 are matched by the match detection circuit 56, and it becomes possible to detect a failure only in the multiplier 50.

It is clear that a failure in only the adder 55 can be easily detected by comparing the modulo 3 signal 37 and the modulo 3 signal of the adder output 40 (which is generated in a conventional failure detection circuit). It is.

1.5 Emperors 1 According to the present invention, the modulo 3 signal prediction signal of the final multiplication result and the correction signal of the modulo 3 signal of the result of adding the carry and the sum which are the outputs of the multiplier, By comparing the above, it is possible to detect a failure in only the multiplier, and when used in combination with a conventional failure detection circuit, it is also possible to detect a failure in only the adder.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of an actual rope example of the present invention, and Fig. 2 is a circuit block diagram of an actual rope example of the present invention.
FIG. 3 is a diagram showing the relationship between the two modulo 3 signals and their multiplication results, FIG. 3 is a diagram showing the relationship between the addition results, and FIG. 4 is a diagram showing the relationship between correction factors and correction contents in the correction circuit. Explanation of codes of main parts 50... Multiplier 51... Code prediction circuit 52... Modulo 3 signal prediction circuit 53...
... Correction circuit 54 ... Modulo 3 signal generation circuit 55 ...
... Adder 56 ... - Numerical output circuit Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) A multiplier that takes two signed data with modulo 3 signals as input and outputs a carry and a sum as intermediate multiplication results, and a multiplier that takes the carry and sum as input and adds them for final multiplication. A failure detection circuit for an arithmetic circuit including an adder that outputs a result, a modulo 3 signal prediction circuit that predicts a modulo 3 signal of the final multiplication result, and a sign prediction circuit that predicts the sign of the final multiplication result. , a modulo 3 signal generation circuit that generates a modulo 3 signal as a result of adding the carry and the sum, and a modulo 3 signal using the predicted code of the code prediction circuit and the code element included in the carry and the sum. a correction circuit that corrects the signal generation circuit output;
A failure detection circuit comprising: a coincidence detection circuit that detects coincidence between the output of the modulo 3 signal prediction circuit and the output of the correction circuit.