JPH0325543A - Control storage recovering system - Google Patents

Abstract

PURPOSE:To suppress the number of input/output pins of each semiconductor chip from increasing by supplying a count value when an error is detected in another semiconductor chip to the semiconductor chip to perform address management with a universal data bus, and setting a corresponding address as the correction address of control storage by reading out from history storage. CONSTITUTION:An address to make access the control storage 40, the history storage 53 to store the count value of a counter 54 and the error flag of control information at every cycle, and the history storage 55 to store the count value of a counter 56 and the error flag of the control information at every cycle are provided. When the error is detected in the semiconductor chip 42, the count value stored at the same cycle as that of the error flag is supplied from the history storage 55 to the semiconductor chip 41 which performs the address management on the universal data bus, and the corresponding address is read out from the history storage 53, then, it is set as the correction address of the control storage 40. In such a way, it is possible to dispense with a signal line dedicated for the supply of the error flag between plural semiconductor chips, and to prevent the number of input/output pins in each semiconductor chip from increasing.

Description

[Detailed Description of the Invention] [Summary] 1.1 information with an error correction mark added is i. Regarding the $ memory recovery method that corrects the control information in the control memory using a positive sign, there is no need for a dedicated line of sight, and each person's The purpose is to avoid an increase in the number of output bins, and the error correction code is added from tII1tiII memory.
．． The llIll information is read out and supplied individually to a plurality of semiconductor chips to perform respective IQ control, and each semiconductor chip reads the t. In a control memory recovery method that corrects the v1 information in the sll1 memory when an error is detected using an error correction code in the lJ information, a control memory recovery method is provided in each of the plurality of semiconductor chips and mutually synchronizes the &lJ memory. A counter that performs a counting operation for each cycle of access, and a semiconductor chip that manages addresses of the control memory are UGJ'd, and the address that accesses the memory, the count value of the counter in the semiconductor chip, and the A first history memory that stores each error flag that is generated by detecting an error in the IL1 information supplied to the idle chip for each cycle, and other semiconductor chips other than the semiconductor chip that performs address management. A second circuit is installed in the U and stores the count value of the counter in the other semi-interrupted buffer and the error norag generated by detecting an error in the control information supplied to the other semiconductor chip for each cycle. history storage, and when an error is detected in the other semiconductor chip, the count value stored in the same cycle as the error flag is read from the second history storage and the plurality of 1! 7 for supplying the address to the semiconductor chip that performs address management via a general-purpose data bus connecting the conductor chip, and reading an address corresponding to the supplied count value from the first storage memory to correct the control memory; Configure it to be a dress.

[Industrial application field]

The present invention relates to a v1 memory recovery method, in which control information with an error correction code added is stored in the control memory, and when an error occurs, the error correction code is used to store υ161! in the control memory. Concerning the old method of controlling and agitating information.

In recent years, there has been a need to further improve the reliability of sub-equipment equipment, and an error correction code g has been added to the control information stored in the υ+W memory, and the occurrence of a 1-pit L error can be controlled using the U error correction code. Revise control information in memory. iTt is being done. In this way, when you make a 1-pit error, you can straighten your sword. l
This is to prevent multiple pit errors of 2 bits or more from occurring during storage, which could lead to errors.

As a method for configuring ill memory, there are the following formulas: i, I + memory h. In this H type, each of the plurality of semiconductor chips constituting the CPU has a control memory and performs individual ML control. In this case, a single chip that interprets and executes instructions only manages the address of the command record and receives control information from other chips G. In this case, if a 1-bit error occurs in the control information in another chip, that chip transfers the error information to t. It is necessary to send the address of the IJIII memory to the chip that is managing it so that it can correct the control memory.

Although the number of gates on semiconductor chips is increasing, the number of input/output pins for interfacing with the outside has not increased commensurately, and it is necessary to use the minimum number of input/output pins. is necessary.

[Conventional technology]

FIG. 2 shows a block diagram of an example of a conventional method.

In the figure, 10 is a control memory, 11 is a semiconductor chip that performs address management, and 12 is another partially idle chip.

The semiconductor chip 11 latches the starting microaddress of the microprogram Ogram supplied via the input F13 into the address register 14, and this ? Control memory 1 with micro address
Access 0. The v1 information read from the control memory 10 is used for error correction (F C C
) The control information is supplied to each of the circuits 15 and 16, and the control information on which errors of up to 1 bit error have been corrected are supplied to, for example, each of the V4 circuits 17 and 18.

In addition, each of the ECC circuits 15 and 16 transmits a 1-bit error flag to the latch circuit 19 when detecting 1 pit I error.
．． Hit 20 and wrap the syndrome in circuit 21
．． Set to 22. The latch circuit 20's latch circuit 20 is connected to the latch circuit 20 through a dedicated signal I123 from the zip 12 to the button 11.
The error flag is supplied to the OR circuit 24 in the latch circuit 19, and is then sent to the correction circuit 25 and the interrupt generation circuit 2 together with the error flag of the latch circuit 19.
6.

When supplied with the error flag, the interrupt generation circuit 26 *
'F27 notifies the service processor υ (f in the figure) of the occurrence of an interrupt to stop normal processing, and performs correction processing of &+1 memory through the intervention of a microprogram or the like.

If an error occurs in the chip 12 at this time, the interrupt generation circuit 28 transmits the syndrome of the latch circuit W122 to the n-positive circuit 2 via the predefined general-purpose data bus 29.
This correction circuit 25 supplies the latch circuit 21.2 to the latch circuit 21.2.
Corrected due to the syndrome from 2 υ; control information is generated and stored in the address register 30. The a! of the vIIl memory 10 is determined based on the previous 7.0 address, that is, the microphone mouth address where the error occurred. I4 is performed.

Note that the interrupt generation circuits 26 and 28 are the arithmetic circuits 17 and 18.
'fa F
2 From 7.31, notice will be given to Ibisproset υ.

[Problem to be solved by the invention]

In the conventional H type, a dedicated signal line 23 had to be provided between the semiconductor chips 11 and 12, and as the number of chips increased, the number of signal lines for the above structure also increased.
There was a problem in that the number of input and output bins for each (particularly the zip 11) was increased.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a control memory recovery method that does not require a signal line for transfer and does not increase the number of input/output bins of each semiconductor chip.

[Means to solve the problem]

The II11 storage duplication method of the present invention is based on υ! where an error n positive sign is added from the v41I storage. Reads the Illffi information and supplies it to multiple semiconductor chips individually to each i4lJ.
Fill III &! In the recovery method, a counter is provided on each of a plurality of semiconductor chips and performs a counting operation for each cycle of accessing the t#IIl memory in agreement with each other, and a semiconductor chip that performs address retrieval of the control memory. Provided! a first @history memory that stores, for each cycle, an address for accessing the lItl memory, a count value of a counter in the semiconductor chip, and an error flag generated by detecting an error in the lI13111 information supplied to the semiconductor chip; It is provided in a semiconductor chip other than the semiconductor chip that performs management, and the counters in the other semiconductor chips and other 'I! aill supplied to the rest area
A second history memory stores each error flag generated by error detection of tll information every 1+J cycles, and when an error is detected in another semicircular chip, the second history memory
IP! ! The count set stored in the same cycle as the error flag is read from the memory and supplied to the semiconductor chip that performs address management via a general-purpose data bus that connects multiple This is an address for reading from the history memory of 1 and correcting the memory of υl.

[For bamboo]

In the present invention, &IJI! with other ¥ conductor chips! When an error occurs in the I information, the counter l- value at that time controls the address through the general-purpose data bus]! The address of the control memory at the time of error utterance is read out from the first history memory based on the count value. Therefore, there is no need to provide a signal line for supplying error flags between a plurality of F4 off chips, and the number of human output bins for each half off chip does not increase.

(Sudden example) FIG. 1 shows a block diagram of an embodiment of the method of the present invention.

In the same figure, 40 is! ll remember, 41 is address management 1
1 is a semiconductor chip, and 42 is another semiconductor chip.

The semiconductor chip 41 latches the start microaddress of the microphone program supplied through the input terminal 43 in the address register 44, and uses this microaddress to start the ilHD.
Access memory 40.

The υ111l information read from the lIIIti memory 40 is sent to the error correction (FCC) circuits 45 .
For example, the control information supplied to each of
provided to each.

Furthermore, when each of the FCC circuits 45 and 46 detects a 1-bit error, the 1-bit error flag is transferred to the latch circuit 49 .
50 and wrap the sind [I-m] in the wrap circuit 51.
．． Set to 52.

The history memory 53 in the chip 41 includes an address register 44.
7 and 0 addresses, and a count supply for a counter 54 that counts every 1+J cycles of the system clock after being reset at power-on, and a latch circuit 4.
Error flag people from 9 are supplied and history memory 534
This history information is stored sequentially for each cycle. In addition,
The microaddress changes every 1+1 cycles of the system clock. In addition, the WM history 155 in the chip 42 is reset when the power is turned on, and then the count value of the counter 56 is counted every cycle of the system clock.
(same as the count value of the counter 54) and the latch circuit 50
History information of error flags is sequentially stored for each cycle.

Historical memory 53.55 each of at least one step? [It has a capacity to store history information equal to the number of cycles required to execute one instruction, and has a history storage capacity of 53.55
The error nolag stored in each interrupt generation circuit 57.
58 is also supplied.

Each of the interrupt generation circuits 57 and 58 generates an interrupt when an arithmetic exception occurs in each of the arithmetic circuits 47 and 48, and when a T runo lag is supplied, all cycles of the microphone instruction are completed and the next microinstruction is started. Before transitioning to , υ1 inclusive generation is performed, and this interrupt generation is notified to the service program through terminals 61 and 62. If a 1-bit error occurs in the illllKI information in chip 41, υ1 inclusive generation is performed. From decoy history memory 53 I
The microaddresses of the cycles in which the error flag is set are successively output and supplied to the 11 positive circuit 63, and the 1 bit error 1 o'clock syndrome latched in the wrap circuit 51 is supplied to the 5I positive circuit 63. I'i}circuit 6
Corrected by No. 3 Yokono Syndrome fIll til
l information is generated and stored in the instruction memory 40 along with the microaddress.
The control memory 40 is replaced.

If a 1-bit error occurs in the f, II, or III information in the dip 42, an interrupt is generated, and the count code of the cycle in which the error flag is set is read from the history memory of the dip 42, and is read out through the predefined general-purpose data bus 64a. The 1-bit, 1-error, 1-o'clock synd.l], supplied to the positive circuit 63 and latched to the wrap circuit 52, is supplied to the correction circuit 63 through the fixed general-purpose data bus 64b. The 1 correction 11 path 63 generates the W1 positive l+l*ffi information by the above-mentioned syndrome 0-m, and also converts the count supplied from the history memory 55 to the ? of the history memory 53 having the same count value. Read out the ejaculation address and i. ll is supplied to the control memory 40, and the translation of the control memory 40 is performed.

In this way, since the count value and syndrome are supplied from the other ゛f conduction jump 42 to the semiconductor chip 41 that performs address management via the already defined general-purpose data buses 64a and 64b, conventional errors and errors can be avoided. There is no need for the dedicated communication line 23 that was installed to supply the LJ, and an increase in the number of input/output bins of the other semiconductor chips 41, 42 can be prevented.

[Effects of the Invention] As mentioned above, 2IlIlIIl&l! of the present invention. According to the old method, there is no need for a dedicated signal line for supplying error flags between multiple semiconductor chips, there is no increase in the number of output bins for each 'P-deactivated chip, and it is extremely practical for h-use. be,
, is shown.

VI revision applicant Co., Ltd.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the method of the present invention, and FIG. 2 is a block diagram of an example of the conventional method. In the figure, 40 is a control memory, 41.42 is a semiconductor chip, 45.46 Gi error correction O path 53, 55 is a history memory, 54.564 counter, 57.58 is a pruning generator 1 circuit, 634j1 is a positive circuit, 64a ．． 64b is a general-purpose data bus (ECC circuit)

Claims (1)

[Scope of Claims] Control information to which an error correction code has been added is read from a control memory (40), and is individually supplied to a plurality of semiconductor chips (41, 42) to control each semiconductor chip (41, 42).
, 42), in which the control information in the control memory (40) is corrected when an error is detected using an error correction code in the control information; ,
Counters (54, 56) perform a counting operation for each cycle of accessing the control memory (40) in synchronization with each other.
), and is provided in a semiconductor chip (41) that manages addresses of the control memory (40), and includes an address for accessing the control memory (40), a count value of a counter (54) in the semiconductor chip (41), and a first history memory (53) that stores each cycle of error flags generated upon error detection of control information supplied to the semiconductor chip (41);
and the count value of the counter (56) in the other semiconductor chip (42) and the other semiconductor chip (42) provided in the other semiconductor chip (42) than the semiconductor chip (41) that performs address management. ) and a second history memory (55) that stores each error flag generated by detecting an error in the control information supplied to the semiconductor chip (55) for each cycle. A semiconductor chip that reads out a count value stored in the same cycle as the error flag from the second history memory (55) and manages the address using a general-purpose data bus that connects the plurality of semiconductor chips (41, 42). (41), and reads an address corresponding to the supplied count value from the first history memory (53) and uses it as an address for correcting the control memory (40). Recovery method.