JPH03252774A - Wiring design system - Google Patents

Abstract

PURPOSE:To shorten the processing time of wiring design by performing the bundle wiring of element components by using bundle components with shape prepared as the wiring components. CONSTITUTION:A block 4 and a macro cell 5 are arranged in a chip. Next, a straight line 7, and bundle wiring components of L-shape, T-shape, and criss- cross shape, etc., are prepared in advance. In such a case, when the wiring between the macro cells is observed, eight bit parallel signal lines i.e. eight connection exist between the macro cell 5 and a macro cell 6, therefore, the wiring is formed by combining and arranging the components 7, 8, 7a, 8a, and 7b out of prepared bundle wiring components. In such a way, it is possible to efficiently perform automatic wiring processing, and to reduce assistance for the wiring design.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to wiring design technology for semiconductor integrated circuits, circuit boards, and the like.

[Prior Art] In recent years, semiconductor integrated circuits have tended to include macro cells due to demands for higher density, but wire bundles are often used for wiring between macro cells.

Further, bundled wires are often used for connections between each IC on a circuit board.

Conventionally, the wiring design for these wire bundles has been performed individually one by one.

FIG. 4 shows an example of wiring between macro cells according to this prior art.

Since the wiring between macro cells is wired one by one by automatic wiring processing, unconnected wires 51 and detour wires 52 occur due to interference from other general wiring patterns 50. After that, additional wiring work is performed manually, and the wiring length is shortened to shorten the wiring delay.

As described above, when wires are wired one by one, the processing time is long, and unconnected wires or detour wires may occur.

On the other hand, if the bundled line area and the macrocell area are defined in advance, as in the technology described in Jikai Publication No. 63-81569, which shortens the development period by generalizing macrocells such as microprocessors, the bundled wiring can be reduced. For simplicity, it is thought that the occurrence of unconnected wires and detour wires can be suppressed to some extent.

[Problems to be Solved by the Invention] However, according to the technology described in Jikai Publication No. 63-81569, the arrangement of elements is limited to bundled wiring, and there is little flexibility in development and design, and the CPU, etc. There is a problem in that the application of each macrocell is limited to special items that can be general-purposed to some extent.

Therefore, the present invention provides, without limiting the arrangement of elements,
The purpose of this invention is to provide a general wiring design method that can shorten the processing time for wiring design.

[Means for Solving the Problems] In order to achieve the above object, the present invention uses bundled wire components of one or more shapes prepared in advance as wiring components,
A first wiring design method for semiconductor integrated circuits, circuit boards, etc. is provided, which is characterized by performing bundled wiring between element parts.

Further, in order to achieve the above object, the present invention performs bundled wiring between element parts using bundled wire parts of one or more shapes prepared in advance as wiring parts, and then performs bundled wire wiring between element parts. A second wiring design method is provided, which is characterized by performing single-line wiring.

Further, in order to achieve the above object, the present invention includes
A wiring component including a bundled wire component of more than one shape and one or more element components are prepared, and the wiring component type is selected based on the arrangement information of each element and the connection information between each element. A third wiring design method is provided, which is characterized by performing bundled wiring between components.

Further, in order to achieve the above object, the present invention stores wiring component information including bundled wire components of one or more shapes, one or more element component information, arrangement information of each element, and connection information between each element. and means for selecting the wiring component type based on the element component information, arrangement information, and connection information, and performing bundled wiring between each element component. ) provide equipment.

Further, the present invention further provides a storage means for storing wiring component information including bundled wire components of one or more shapes, one or more element component information, arrangement information of each element, and connection information between each element; means for extracting bundled wires based on the element component information, placement information, and connection information; means for selecting the wiring component type from the extracted wire bundles; and means for selecting the wiring component type from the extracted wire bundles; A second CAD device is provided, characterized in that it has a means for performing wire bundle wiring.

Note that the bundled wire parts having one or more shapes are any one or more of the following types: straight wire bundled parts, 5-shaped wire bundled parts, 1-shaped wire bundled parts, and cross-shaped wire bundled parts. It is preferable that it is a wire component, and more preferably that it includes all of these bundled wire components.

[Function] According to the wiring design method according to the present invention, bundled wire parts having one or more shapes such as a straight wire bundled product, a 5-shaped wire bundled component, a 1-shaped wire bundled component, a cross shape, etc. are prepared in advance. Prepared as wiring parts,
This is used to perform bundled wiring between element parts. Furthermore, after the above bundled wiring, the remaining wiring such as each single wire between element parts is performed. Thereby, wiring processing can be made more efficient.

Further, according to the CAD device of the present invention, based on the element component information, arrangement information, and connection information stored in the storage means, a linear bundled product, a 5-shaped wire bundled component, a 1-character bundled wire component, parts,
Wire bundle parts suitable for wire bundle wiring are sequentially selected from wire bundle parts such as a cross shape, and wire bundle wiring between each element component is performed while combining the wire bundle parts. Also, preferably, after that,
The remaining wiring such as each single wire between the element parts is performed based on the element part information, arrangement information, and connection information stored in the storage means. This makes it possible to streamline automatic wiring processing and reduce manual intervention in wiring design.

[Example code] Examples of the present invention will be described below.

The semiconductor chip 1 shown in FIG. 1 includes a crowd buffer cell,
External logic section 2 equipped with bonding pads etc.
A block 4 consists of several hundred gates, and an internal logic section 3 that realizes the logic function intended by the user by arranging multiple macro cells 5 each of which has a single function as a component and wiring between them. has been done.

Hereinafter, the wiring design method according to this embodiment will be explained by taking as an example the case where the wiring of the semiconductor chip 1 shown in FIG. 1 is designed.

First, the block 4 and macrocell 5 shown in FIG. 1 are placed in a chip. At this time, block 4 and macro cell 5
The area other than where is placed will be the wiring area, so estimate and secure this size.

Next, wiring between each block or between each block and an external logic section is performed as follows.

First, bundled wiring parts such as a straight line 7, an L-shape, a T-shape, and a cross-shape are prepared in advance.

In this embodiment, a wire bundle consisting of eight signal wires is prepared as an example. Of course, there are 4, 16, and 3.
Although the number may be 2, 64, etc., in this embodiment, for convenience of explanation, a case of 8 lines will be explained as an example.

Here, looking at the wiring between the macro cells, there are 8-bit parallel data signal lines, that is, eight connections between the macro cells 5 and 6.

Therefore, wiring is realized by combining and arranging this connection with 7.8.7a, 8a, and 7b among the bundled wiring components prepared.

As mentioned above, several patterns are prepared in advance for the number of wires in bundled wire components, and the length of one component is automatically adjusted according to the connection. Allows the direction to be changed by rotation.

Further, in this embodiment, each input/output terminal, that is, the inlet/outlet of the signal line, of the macrocell is arranged on one side at equal intervals or with regularity.

Next, a CAD device that implements the above processing will be described.

FIG. 4 shows the configuration of this CAD device.

In the figure, 43 is a ROM that stores a wiring design processing program executed by the arithmetic processing unit 43, 4 is a memory such as a work RAM, 42 is a data file that stores macro cell information and wiring component information, and 44 is a processing status, chip layout, etc. A display device that displays.

45 is an output storage file that stores chip manufacturing information after wiring design is completed.

The arithmetic processing unit 43 also includes a bundled wire cleaning processing unit 431.
, bundled wire component placement processing section 432, general wiring processing section 433,
It has a connection check processing section 434.

Hereinafter, the procedure of the wiring design process performed by this CAD device will be explained by taking the above-mentioned wiring design (see FIG. 2) as an example.

FIG. 4 shows the wiring design processing procedure in this case.

First, the CAD device 43 uses the bundled wiring cleaning processing section 431.
In this step, we focus on the connection of signal lines between macro cells in the given design information (step 31), and if two or more signal lines have the same arrangement and destination, we extract them as bundled wiring. (Step 32).

Next, the macro cell interval is calculated (step 33), and a straight line passing through the midpoint and parallel to the horizontal or vertical direction is virtually set. Then, a line segment is drawn perpendicularly to the set straight line from one macro cell, and an L-shaped bundled wiring component is selected for the overlapping portion, and a straight wiring component is selected for the remaining portion (step 34).

Next, the selected wire bundle wiring components are combined and arranged while being adjusted by enlargement or reduction (step 35).

Then, the general wiring processing unit 433 performs wiring that has not been extracted as bundled wiring (step 36).
The connection check processing unit 434 performs a connection check (step 37), and if there is no error, the wiring design process ends; if there is an error, the wiring is manually added or corrected (step 37), and the connection check is performed again. of,
This is repeated until there are no more errors, and when there are no more errors, the wiring design process ends.

The wiring information created through the above processing is included in the manufacturing information and stored in the output storage file 45.

Hereinafter, the wiring design processing procedure has been explained using the wiring design shown in Fig. 2 as an example, but the processing procedure algorithm is not limited to this, and can be modified as appropriate depending on the wiring design system. It is desirable to use the following algorithm.

As described above, according to this embodiment, the wiring efficiency is improved by improving the straightness of the wiring in the semiconductor integrated circuit.

In addition, processing time can be shortened, unconnected lines and detour wiring can be reduced, and occurrences of processes such as manual addition of wiring and shortening of detour wiring can be suppressed.

Therefore, the semiconductor integrated circuit design period can be significantly shortened by the above. This is more effective when macro cells are used frequently.

Note that this embodiment describes one embodiment of the present invention by taking the wiring design of a semiconductor integrated circuit as an example, but this is not limited to semiconductor integrated circuits, and can be applied to, for example, the wiring design of a circuit board. The same can be achieved in wiring design, etc. In this case, the macrocell includes an IC chip or the like.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a wiring design method that can shorten the processing time for wiring design without restricting the arrangement of elements.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the arrangement of elements in a semiconductor integrated circuit to be interconnected, FIG. 2 is an explanatory diagram showing an example of bundled wiring according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing an example of the wiring design process. Flowchart 1 showing the procedure, FIG. 4 is a block diagram showing the configuration of the CAD device, and FIG. 5 is an explanatory diagram showing an example of bundled wiring related to superposition wiring design technology. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Frame logic section, 3... Internal logic section 54... Block, 5.6... Macro cell, 7.8.9.10... Wire bundle wiring component, 40・=R
OM, 41...Memory, 42...Data file,
43... Arithmetic processing unit, 44... Display device, 45.
. . . Arrangement storage file, 50 . . . General wiring pattern, 51 . . . Unconnected, 52 . . Detour wiring.

Claims (1)

[Claims] 1. A wiring design method characterized by performing bundled wiring between element parts using bundled wire parts of one or more shapes prepared in advance as wiring parts.