JPH0296278A - Automatic wiring processing system - Google Patents

Abstract

PURPOSE:To realize the uniform wiring of buses for address and data signals, etc., by setting a single signal line with a request for plural uniform wirings and then wiring each signal lines in detail after decision of the wiring routes. CONSTITUTION:In a bus pin production process 3 and a bus signal line production process 4, plural pins used for input/output of the bus signal are turned into a single pin based on the bus wiring specifications 1 together with plural signal lines forming a bus turned into a single signal line. Thus the bus signal connection information 5 is produced from the original connection information 2. In a global wiring process 6, a bus wiring route is decided based on the information 5. The elements A-D form an IC or an LSI, the bus pins P1-P4 perform the input/output of bus signal, and the bus signal lines L1-L2 connect between the pins P1-P4 respectively. These bus pins P1-P4 and bus signal lines L1-L2 consist of plural pins and signal lines.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is an automatic wiring processing method that uses a computer to automatically wire between input and output pins of each element constituting an electronic circuit such as an IC or LSI. It is related to.

[Prior Art] Fig. 4 is a flowchart showing a conventional automatic wiring processing method. 6 is a global wiring process that determines which wiring ((fi) sweat glands and power line) should take what route when viewed from the entire IC and LSI based on the device information and connection information 2; Reference numeral 8 denotes a detail wiring process that determines where each wire physically passes within the route determined in the global wiring process 6, and 9 represents a wiring result obtained by this detail wiring process 8.

Next, the operation will be explained.

In global wiring processing 6, placement information and connection information 2 are input, wiring areas where wiring is possible are determined, and wiring routes, that is, which wiring areas each wiring should pass through are determined. At this time, each wiring becomes the shortest and the IC, LSI
Decide so that the total area is the minimum. How to determine the wiring area differs depending on the wiring method, but basically, determine the maximum number of wirings that each wiring area can include from the perspective of the entire Ic and LSI, and then define each wiring area within that range. Determine which wiring route will be taken.

In detail wiring processing 8, the above global wiring processing 6
According to the information on the wiring area determined in and the wiring determined to pass through the wiring area, the position of each wiring within the wiring area is determined so that each wiring is the shortest and has the smallest wiring area. is performed and output as wiring result 9.

[Problems to be Solved by the Invention] The conventional automatic wiring processing method is performed as described above, but when the wiring consists of multiple signal lines such as address signal lines and data signal lines that need to have uniform wiring lengths, The signal lines that make up the bus may be mixed with signal lines other than the signal line group, each signal line group may take a completely different route, or the signal line groups may unnecessarily intersect. There were problems such as the

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an automatic wiring processing method that can realize uniform wiring of a group of signal lines constituting a bus.

[Means for Solving the Problems] The automatic wiring processing method according to the present invention, prior to global wiring processing, connects a plurality of pins to which bus signals are input/output based on the wiring specifications of a bus consisting of a plurality of signal lines of the same type. Processing is performed to generate bus signal connection information from the original connection information by treating the multiple signal lines that make up the bus as one pin, and by global wiring processing based on this bus signal connection information. The wiring route of a bus signal line with a width equal to the number of lines is determined, and the wiring position within the bus wiring area of each signal line that makes up the bus signal line is determined by detailed wiring processing according to the determined wiring route. It is something.

[Function] The automatic wiring processing method according to the present invention handles multiple pins to which bus signals are input/output as one pin;
The multiple signal lines constituting the bus are treated as one (,:J branch line) with a width equal to the number of signal lines, resulting in global wiring.

They are wired together along the same route. Detail wiring is used to ensure that each signal line does not cross within the bus wiring area, which has a width equal to the number of signal lines.The wiring is routed without unnecessary crossing, and the wiring lengths are almost the same. Become.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a flowchart showing the automatic wiring processing method of the embodiment. 2 is the arrangement information and connection information; 3 is the bus wiring specification for inputting and outputting bus signals based on the above bus wiring specification 1, arrangement information and connection information 2; 4 is a bus pin generation process in which the pins of 4 are generated as one pin (hereinafter referred to as bus pins), and 4 is a bus in which multiple signal lines constituting the bus are similarly generated as a single 4g line (hereinafter referred to as bus signal lines). Signal line generation processing, 5 is bus pin generation processing 3 described above, bus signal connection information described by bus pins and bus signal lines generated by bus signal line generation processing 4, 6 is described as one pin and signal line Global wiring processing that determines the wiring area and route based on the bus signal connection information 5 and the above arrangement information and connection information 2; 7 is the global wiring result obtained by the above global wiring processing 6; 8 is the above global wiring result 7 9 is a wiring result, and 10 is a wiring route designation graphically specified from a graphic terminal during the global wiring process 6.

Next, the operation will be explained.

First, in bus pin generation processing 3 and bus signal line generation processing 4, multiple pins that input and output bus signals are treated as one pin based on bus wiring specifications 1, and multiple signal lines that constitute the bus are treated as one signal. By making it a line, 1 original connection information 2
Bus signal connection information 5 is generated from. In the global wiring process 6, a wiring route as shown in FIG. 2 is determined for the bus based on this information. In Figure 2, A-D
indicates each element constituting an IC or LSI, PI to P4 are bus pins through which bus signals are input/output, and Ll.

L, each bus pin 2. It is a bus signal line connecting between ~24, and each bus pin ■]1~P4 and the bus signal line, L2
Each consists of a plurality of pins and signal lines. For example, the bus pins Pl, Pz, P3 are composed of 16 pins, the bus pin P4 is composed of 8 pins, and the bus signal line Ll (bus pin P,.

Wiring between P2 and P3) is the width of 16 signal lines.

The bus signal lines are determined and routed to have a width equivalent to eight signal lines. This is the bus pin PI e
P2 v p3 consists of 16 pins, and the wiring area of the bus signal line that connects these pins ultimately has 16 pins.
It is necessary to wire the main signal line, and also bus pin P4
consists of 8 pins, and the bus signal line L connected to this
This is because it is necessary to wire eight signal lines in the wiring area No. 2 in the end.

These wirings are routed according to the bus wiring specification 1 or wiring route specification 10 in the global wiring process 6, if the route is specified. If no route is specified, the shortest route is determined in the same way as normal wiring.

On the other hand, in the detail wiring process 8, based on the above global wiring result 7 obtained by the global wiring process 6, as shown in FIG. Wire each signal line uniformly so that it does not cross unnecessarily. Specifically, in FIG. 3, pin a included in one bus pin
, is connected to pin a2 included in the other bus pin, a grid is provided in the bus wiring area according to the wiring pitch, and the wiring position is determined according to this grid so that the other (iY) segment line does not intersect.

In the above embodiments, the internal wiring of ICs and LSIs has been described, but the same effects as in the above embodiments can be obtained for wiring of PCBs, that is, printed circuit boards, etc.

[Effects of the Invention] As described above, according to the present invention, in response to a uniform multiple wiring request, it is handled as one signal line, and after determining the wiring route, the wiring is performed one by one in detail. By adopting this method, it is possible to uniformly route buses such as address signals and data signals, which has the effect of producing products with consistent performance.

[Brief explanation of the drawing]

FIG. 1 is a flowchart 1 showing an automatic wiring processing method according to an embodiment of the present invention, FIG. 2 is a diagram showing the main part of the global wiring h' according to the embodiment, and FIG. 33 is a detailed diagram according to the embodiment. FIG. 4, which is a diagram showing the main part of the wiring result, is a flowchart 1 showing the conventional method. 1 is bus wiring specification, 2 is placement information and connection information, 3 is bus pin generation process, 4 is bus signal line generation process, 5 is bus signal connection information, 6 is global wiring process, 7 is global wiring result, 8 is Detail wiring processing, 9 is wiring result,
10 is a wiring route designation, A-1) is an element, P1 to P4 are bus pins, and Ll. L2 is the bus signal line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Iwa (2 idiots) Figure 2

Claims (1)

[Claims] When automatically wiring between the input and output pins of each element that makes up an electronic circuit using a computer, the wiring area and each wiring route are determined based on the arrangement information of each element and the connection information between the input and output pins. After performing global wiring processing,
In an automatic wiring processing method that obtains wiring results by performing detailed wiring processing to determine the detailed position of each wiring within the wiring area according to the determined wiring route, prior to the global wiring processing described above, Based on the bus wiring specifications consisting of signal lines, multiple pins where bus signals are input/output are treated as one pin, and multiple signal lines that make up the bus are treated as one signal line.Bus signal connection information is determined from the above connection information. Based on this bus signal connection information, the global wiring process determines a bus signal line wiring route with a width equal to the number of signal lines, and the detailed wiring process connects the bus signal line according to the determined wiring route. An automatic wiring processing method characterized in that the wiring position of each constituent signal line within a bus wiring area is determined.