JP3133718B2 - Layout method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly to a layout method for minimizing a layout area of a wiring layer.

[0002]

2. Description of the Related Art The cost of semiconductor integrated circuits has been reduced year by year, and it is necessary to reduce the chip area. One of the factors that determine the chip area is the layout area of the power supply / GND and the wiring layer used for wiring.

In a conventional layout method, a power supply and a GND wiring are first placed on a block in FIG.
2, and a wiring area for use in the same layer as the power supply / GND wiring in the block is provided between the power supply wiring and the GND wiring. The spacing of this area was unified and fixed for all blocks. Next, wiring outside the blocks arranged as shown in FIG. 13 was arranged.

[0004]

However, the above conventional layout method has the following problems. First, some blocks do not use the wiring area provided in the block, and the unused areas are all free areas (see free area 1 in FIG. 13).

[0005] As a second problem, the area of the wiring region arranged outside the block is determined when the number of wirings is the largest, and when the number of wirings is small, the area shown in FIG.
A free area has been created as in the free area 2 of FIG.

An object of the present invention is to solve the above problems,
Fill unused wiring areas in blocks,
An object of the present invention is to provide a layout method that does not generate an empty area by equalizing the number of wirings in a wiring area arranged outside a block.

[0007]

The object of the present invention is to provide a step A of inputting data relating to an arbitrary number of various blocks to be arranged in a layout area to a data processing device and storing the data in a storage device. Step B for classifying the blocks into groups to which they belong and storing them in the storage device for each group, Step C for arbitrarily arranging each block in each group, and arbitrarily arranging each group and assigning the arrangement pattern for each arrangement pattern Storing D in a storage device;
Step E of arranging the ND wiring, Step F of arranging another wiring outside the power supply / GND wiring, and calculating the layout area of the arrangement pattern in which the power supply / GND wiring and the wiring outside the wiring are arranged. Step G is repeated a specified number of times while changing the arrangement of each group, and further, the layout areas of the resulting arrangement patterns are compared with each other to determine the minimum area arrangement. The above problem can be solved by a layout method including a step H for finding a pattern and a step I for outputting data of an arrangement pattern with the smallest area found.

According to the present invention, a plurality of blocks to be laid out in a certain layout area (a set of elements which must be arranged close to each other in a circuit) are grouped according to a certain criterion, and the arrangement pattern of each group is tried. A method is provided for finding and outputting an arrangement pattern that minimizes the layout area among them while changing the layout pattern. As a result, the chip size can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described. (First Embodiment) The layout method in which the classification in the step B is performed according to the size and arrangement of the internal wiring area of each block.

The internal wiring area of each block includes a power supply wiring and a GND arranged in advance in the block.
This is an area other than the wiring. If the boundary line inside the power supply / GND wiring is, for example, 5 μm from the center of the block and 10 μm from the center of the block, they are classified into different groups.
The placement of each block in the same group can have a small overall impact, so be careful about how each group is placed as a whole without having to worry about the placement of the blocks in the group. Can pour. Also, when the internal wiring region is not at the center of the block (for example, at the top or bottom), it is classified according to the corresponding classification concept.

(Second Embodiment) The above-described step C is performed only for blocks where a power supply wiring and a GND wiring are previously arranged at a predetermined distance from the center of each block.
After the step, a step J for correcting the arrangement of the power supply / GND wiring in the group is inserted, and the step E
And the layout method ignoring reference to the power supply / GND wiring in step F and step G.

The first embodiment includes the case where the widths of the power supply wiring and the GND wiring area arranged in advance in the block are both zero. On the other hand, the present embodiment deals with a case where these areas are arranged symmetrically from the center of the block and the width of the area always takes a finite value.

In this case, the internal wiring area defined by the power supply / GND wiring is prepared in each block in advance, but if this is used as it is, the internal wiring area will not be used up when the amount of wiring passing through the block is small. It is possible that an empty area will be created in the file. Therefore, a correction for narrowing the internal wiring area is performed as step J while checking the vacancy of the internal wiring area in each block.

Since the power supply / GND wiring is already prepared in each block, the power supply / GND is provided outside the block.
Step E of arranging the D wiring is unnecessary and is deleted. The power supply in step F and step G
References to GND wiring are ignored.

(Third Embodiment) The correction of the power supply and the GND wiring in the step J is performed until the vacant area does not exist in the internal wiring area of each block.
The above-mentioned layout method, wherein the GND wiring is moved toward the center of the block.

The present embodiment specifically describes the correction method in the second embodiment. That is, the power supply / GND wiring is moved toward the center of each block until there is no free area in the internal wiring area of each block.

[0017]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a conceptual diagram for explaining the flow of processing in a layout method according to this embodiment, and FIG.
3 is a flowchart showing the flow of FIG. 1 as a processing step, FIGS. 3 and 4 are blocks handled by the present embodiment, FIG. 5 is a conceptual diagram showing a group layout pattern, and FIG. Power supply G arranged outside
FIG. 8 is a diagram showing a state in which another wiring layer is further disposed outside the ND wiring. The names of the respective steps in the flowchart of FIG. 2 are different from those of the first aspect.

Referring to FIG. 1, a data processing apparatus 2 operated under program control, intermediate data 3 storing data output by data processing apparatus 2 and data processing operated under program control are shown in FIG. It includes output data 5 for storing data output by the device 4 and the data processing device 4.

The input data 1 stores blocks to be arranged in a layout pattern to be designed. The blocks stored here are created in advance so as to satisfy any of the conditions described later.

The data processor 2 has a first condition 21, a second condition 22, and a third condition 23. Condition 21 is that the same layer as the power supply / GND wiring is not used for the wiring. Condition 22 uses the same layer as the power supply / GND within 5 microns from the center of the block. Condition 23 uses the same layer as the power supply / GND within 10 microns from the center of the block (see FIG. 3).

Intermediate data 3 is group 31, group 3
2. Group 33. Group 31 has condition 21
Are stored in the group 32, and the blocks that satisfy the condition 22 are stored in the group 32.
Stores a block that satisfies the condition 32.

The data processor 4 has an arrangement determination 41 which determines how to arrange the groups 31 to 33 to minimize the layout area. The optimum layout pattern determined by the data processing device 4 is stored in the output data 5.

Next, the operation of the present embodiment will be described in detail with reference to FIGS. The input data 1 stores 10 blocks (see FIG. 4) to be arranged in the layout area to be designed now. Next, the data processing device 2
Is input data 1 (step A1 in FIG. 2). The group is classified according to the conditions. Blocks in which the same wiring layer as the power supply / GND is not used according to the condition 21 are stored in the group 31 (step A2). Next, according to the condition 22, the wiring area used in the block is less than 5 microns from the center of the block.
2 (step A3). Finally, a block whose wiring area is within 10 microns from the block center is stored in the group 33 according to the condition 33 (step A4).

Next, blocks are arbitrarily arranged in each group (step A5) (see FIG. 5).

The completed three groups are input to the data processing device 4. First, the three groups are arbitrarily arranged (see FIG. 6) (step A6), the power supply / GND wiring is arranged (see FIG. 7) (step A7), and the wiring outside the power supply / GND wiring is arranged (FIG. 8). (See step A)
9). Next, the area of the layout pattern in which the power supply / GND wiring and the wiring outside the power supply / GND wiring are arranged is calculated (step A9), and the areas are compared (step A1).
0) Consider whether the area of the layout pattern is minimum. If the area is the smallest, the layout pattern and the area are stored (step A11); otherwise, the process proceeds to the next processing. The above processes from 41 to 46 are performed in 6
(Step A12) The pattern with the smallest area is finally stored in the output data 5 (Step A13).

In the first embodiment, the number of blocks input to the block 1 is limited to ten, but the number of blocks may be arbitrary. Although the blocks are classified according to three conditions, the number of conditions is not limited. The wiring area in the block is also set to 0, 5, and 10 microns from the center of the block, but the numerical value may be arbitrarily determined. Further, the wiring area in the block is not limited to the center of the block, but may be the upper or lower part of the block.

(Second Embodiment) Next, another embodiment of the present invention will be described with reference to the drawings. 9 is a flowchart of this embodiment, FIG. 10 is input data, FIG. 11 is an explanatory diagram of correction in this embodiment, FIG. 12 is an explanatory diagram of a power supply / GND wiring and a wiring area in a block in a conventional block, and FIG. FIG. 9 is a conceptual diagram illustrating a free area in a conventional layout method. Note that the names of the steps in the flowchart of FIG. 9 are different from those in claim 1 or the like.

Referring to FIG. 9, step B of this embodiment is described.
The input data input in step S1 differs from the data input in step A1 in FIG. Step A5 in FIG.
Before the power supply and GND wiring correction (step B
5) The difference is that step A7 is eliminated.

In the block input in step B1, a power source is set in advance at a position 10 microns from the center of the block.
The GND wiring is arranged (see FIG. 10). The same processing as in FIG. 2 is performed from step B1 to step B4, and then the power supply / GND wiring is corrected within the group. Power supply / GN of blocks stored in groups 31 and 32
Since there is an empty area between the D wirings, the power supply / GND wiring is moved toward the center of the block so that the empty area disappears (step B5) (see FIG. 11).

Thereafter, steps B6 and B7 perform the same processing as steps A5 and A6 in FIG. Since the power supply / GND wiring has already been arranged, the processing corresponding to step A7 in FIG. 2 is not performed, and steps B8 to B13 are the same as steps A8 to A13 in FIG.

[0032]

As described above, the first effect of the present invention is that there is no free area between the power supply and the GND wiring. The reason is that by grouping the blocks, it is possible to collectively arrange blocks in which the wiring area of the same layer as the power supply / GND used in the block is close, and to arrange the power supply / GND wiring so that no empty area is formed. This is because they can be arranged.

A second effect of the present invention is that the wiring outside the power supply / GND wiring can be efficiently arranged. The reason for this is that, in a block, where blocks that use the same layer of wiring as the power supply / GND are small and are collectively arranged, an area that can be used for wiring outside the power supply / GND wiring is not included in the block. This is because the area of use of the wiring in the same layer is wider than where large blocks are gathered and arranged. By these first and second effects, the layout area can be reduced, and the chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a flow of a process according to a first embodiment.

FIG. 2 is a flowchart expressing the flow of FIG. 1 as processing steps.

FIG. 3 is a conceptual diagram illustrating blocks in the present embodiment.

FIG. 4 is a conceptual diagram illustrating input data in the present embodiment.

FIG. 5 is a conceptual diagram illustrating a group in the present embodiment.

FIG. 6 is a conceptual diagram showing an arrangement pattern of a group.

FIG. 7 is a conceptual diagram showing a power supply / GND wiring arranged outside an arrangement pattern.

FIG. 8 is a conceptual diagram showing a state where another wiring layer is further disposed outside the wiring layer.

FIG. 9 is a flowchart illustrating a flow of a process according to the second embodiment.

FIG. 10 is a conceptual diagram illustrating input data in the present embodiment.

FIG. 11 is an explanatory diagram of correction in the present embodiment.

FIG. 12 is an explanatory diagram of a power supply / GND wiring and a wiring area in a block in a conventional block.

FIG. 13 is a diagram illustrating a free area in a conventional layout method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input data 2 ... Data processing apparatus 21 ... 1st condition 22 ... 2nd condition 23 ... 3rd condition 3 ... Intermediate data 31 32 33 ... Group 4 ... Data processing apparatus 41 ... Arrangement determination 5 ... Output data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (4)

(57) [Claims] 1. A step of inputting data relating to an arbitrary number of various blocks to be arranged in a layout area to a data processing device and storing the data in a storage device, and classifying the blocks into groups to which the blocks belong according to a predetermined classification condition. Step B of storing each group in the storage device for each group, Step C of arbitrarily arranging each block in each group, and Step D of arranging each group arbitrarily and storing the layout pattern in the storage device for each pattern A step E of arranging a power supply and a GND wiring with respect to the arrangement pattern; a step F of arranging another wiring outside the power supply / GND wiring; and the arrangement of the power supply / GND wiring and the wiring outside thereof. And calculating a layout area of the arranged layout pattern, and changing the layout of each group. From Step D to S G recurring specified number of times, further, step H to find the resulting arrangement pattern of comparison with smallest area mutually the layout area of each arrangement pattern
And a step I of outputting the data of the found layout pattern having the smallest area. 2. The layout method according to claim 1, wherein the classification in the step B is performed according to the size and arrangement of the internal wiring area of each block. 3. After step C, the arrangement of the power supply / GND wiring within the group is corrected for only the blocks in which the power supply wiring and the GND wiring are arranged at a predetermined distance from the center of each block. Step J is performed, and Step E is deleted, and the power supply / GND in Step F and Step G is inserted.
3. The layout method according to claim 1, wherein a reference to wiring is ignored. 4. The correction relating to the power supply / GND wiring in the step J is to move the power supply / GND wiring toward the center of the block until there is no free space in the internal wiring area of each block. The layout method according to claim 3.