JPH0325242U - - Google Patents
Info
- Publication number
- JPH0325242U JPH0325242U JP8604689U JP8604689U JPH0325242U JP H0325242 U JPH0325242 U JP H0325242U JP 8604689 U JP8604689 U JP 8604689U JP 8604689 U JP8604689 U JP 8604689U JP H0325242 U JPH0325242 U JP H0325242U
- Authority
- JP
- Japan
- Prior art keywords
- metal base
- convex part
- package
- semiconductor element
- convex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 238000005219 brazing Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の半導体素子収納用パツケージ
の一実施例を示す断面図、第２図は従来の半導体
素子収納用パツケージの断面図である。 １……金属基体、１ａ……凸部、２……絶縁枠
体。
の一実施例を示す断面図、第２図は従来の半導体
素子収納用パツケージの断面図である。 １……金属基体、１ａ……凸部、２……絶縁枠
体。
Claims (1)
- 中央部に半導体素子が載置される凸部を有する
金属基体上に、前記凸部を囲繞するようにして絶
縁枠体をロウ付けして成る半導体素子収納用パツ
ケージにおいて、前記金属基体に設けた凸部の側
面を下方に広がる傾斜状と成したことを特徴とす
る半導体素子収納用パツケージ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8604689U JPH0810197Y2 (ja) | 1989-07-21 | 1989-07-21 | 半導体素子収納用パッケージ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8604689U JPH0810197Y2 (ja) | 1989-07-21 | 1989-07-21 | 半導体素子収納用パッケージ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0325242U true JPH0325242U (ja) | 1991-03-15 |
| JPH0810197Y2 JPH0810197Y2 (ja) | 1996-03-27 |
Family
ID=31635462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8604689U Expired - Lifetime JPH0810197Y2 (ja) | 1989-07-21 | 1989-07-21 | 半導体素子収納用パッケージ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810197Y2 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4512140B2 (ja) * | 2005-12-14 | 2010-07-28 | 学校法人 中村産業学園 | Ｌｅｄ道路交通信号灯 |
-
1989
- 1989-07-21 JP JP8604689U patent/JPH0810197Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4512140B2 (ja) * | 2005-12-14 | 2010-07-28 | 学校法人 中村産業学園 | Ｌｅｄ道路交通信号灯 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810197Y2 (ja) | 1996-03-27 |