JPH03250867A - Detection circuit for frame pulse - Google Patents

Abstract

PURPOSE:To always detect a frame pulse surely without giving effect on a video signal regardless of an APL (average brightness level) of the video signal by providing a bypass filter circuit before a waveform shaping circuit. CONSTITUTION:An analog input signal is fed to an A/D converter 15 via a coupling capacitor 4 and an output signal DS of the A/D converter 15 is fed to a waveform shaping circuit 25 via a digital high pass filter circuit 24. Then the frame pulse is detected from the output signal of the waveform shaping circuit 25. Thus, the frame pulse is always and surely detected without giving effect on a video signal regardless of an APL (average brightness level) of the video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame pulse detection circuit suitable for use in a synchronization separation circuit of a MUSE decoder, for example.

[Summary of the Invention] The present invention provides an analog input signal to an analog/digital converter via a sampling capacitor in a frame pulse detection circuit that periodically changes by a predetermined cycle in positive polarity synchronization with a video signal. The output signal of this analog/digital converter is supplied to a waveform shaping circuit via a digital high-pass filter circuit, and the frame pulse is detected from the output signal of this waveform shaping circuit, thereby determining the APL ( The frame pulse can always be reliably detected regardless of the average brightness level and without affecting the video signal.

[Prior Art] In order to transmit a so-called high-definition signal in a broadcasting system with a limited band such as Eri Broadcasting, MUSE (Multiple Sub - N
yquist-Sampling Encodin
g) A method has been developed.

The transmission signal format of the MUSE method is 2 frames per frame, and the information for 1 frame is 11 as shown in Figure 6.
It is composed of 25 lines (line numbers 1 to 1125). With a sampling frequency of 16.2MHz, one line has 480 points (sample numbers 1 to 4).
8o), and the line sample numbers of line numbers 1 and 2 are between 13 and 316.
T S (vertical 1 intervalte
positive synchronization frame pulses for frame synchronization are assigned to sample numbers 317 to 480 of these line numbers 1 and 2, and horizontal synchronization is assigned to sample numbers 1 to 12 of each line. (
HD) signal is assigned. In addition, as a general rule, each line except line numbers 1 and 2 has sample numbers 13 to 2.
The color signal C or control signal is assigned to the position 106, and the luminance signal Y is assigned to the sample numbers 107 to 480 (7). Furthermore, when the color signal C and the luminance signal Y are expressed with an 8-bit dynamic range,
The level is at the median value (12B/2
56) is assigned a clamp level signal for DC clamp.

FIGS. 7A and 7B show the frame pulse waveforms of line numbers 1 and 2, respectively. In FIGS. 17A and 17B, if one cycle of a frequency of 16.2 MHz is ICK,
17. The value of each frame pulse is inverted every 4CK.
It consists of 5 pairs of square waves, and the zero level of this square wave is “0”.
'' and high level "1" are set to the black level and white level (100% level) of the luminance signal, respectively.
The frame pulse of line number 1 and the frame pulse of line number 2 have a phase difference of 180° and have an extremely low correlation in the vertical direction.On the other hand, normal video signals have a high correlation in the vertical direction, so the correlation in the vertical direction By detecting , the frame pulse can be detected.

Then, the HD period of line number 3 starts 8CK after the end of the frame pulse of line number 2, t0, and thereafter, the HD period of the next line number starts every horizontal period, so the detection of that frame pulse is impossible. If possible, synchronization separation can be performed by generating a key timing pulse using the frame pulse as a reference, extracting the HD signal of each line using this key timing pulse, and finding the phase error. Furthermore, as shown in FIGS. 8A and 8B, the HD signal waveform of the MUSE method is set so that the rising and falling edges are inverted every line, and the reference point is set so that the level of sample number 6 is 128/ 256 position. A clock pulse CP for resampling is generated by multiplying the frequency between these reference points by a PLL circuit, and a phase error consisting of the difference between 172, the sum of the values of sample numbers 8 and 4, and the value of sample number 6 is generated. The PLL circuit is controlled to minimize this.

FIG. 9 shows an input section of a conventional MUSE type decoder. In this FIG. 9, (1) is an input terminal, and an FM demodulation circuit (not shown) and an 8M
Baseband MUS from Hz low-pass filter circuit
E signal is supplied. (2) shows the peak clamp circuit as a whole, (4) shows the coupling capacitor, and (12) shows the switch circuit, whose MUSE signal is connected to the resistor (3) and coupling capacitor (4) in the peak clamp circuit (2). ) to the movable contacts of the switch circuit (12). In the peak clamp circuit (2),
The movable contact of the switch circuit (12) is grounded via the capacitor (5), and the movable contact is connected to the diode (
The anode of the diode (6) is commonly connected to the cathode of the diode (6) and the anode of the diode (7).
The cathode of the diode (7) is connected to the DC voltage source (11) through the resistor (10), and the anode of the diode (6) is connected to the ground through the diode (7). is connected to the cathode of the resistor (9) through a resistor (9).

One fixed contact (12a) of the switch circuit (12) is connected to one fixed contact (13a) of the switch circuit (13), and the other fixed contact (12b) of the switch circuit (12) is connected to the other fixed contact (12b) of the switch circuit (12).
) is connected to the switch circuit (
13) is connected to the other fixed contact (13b).

The DC clamp circuit (14) is connected to line numbers 563 and 1.
1 with a clamp level transmitted on the 125 line.
It is used to clamp the DC level of the input signal once per line during the HD period. Switch circuit (13
) The signal that appears on the movable contact of the analog/digital (A
/D) converter (15) into a digital signal DS, and this digital signal DS is sent to a de-emphasis circuit (
16) and a reverse transmission gamma (r-') correction circuit (17).

(18) shows the sync separation circuit as a whole, in this sync separation circuit (18), (19) is a digital comparator that converts the input signal into a binary signal around a predetermined slice level, and (20) is a frame This is a pulse detection circuit, and a signal at a level of 50% of the digital signal DS and the luminance signal output from the A/D converter (15) is supplied to the non-inverting input port and the inverting input port of the digital comparator (19), respectively. , the output signal of this comparator (19) is supplied to a frame pulse detection circuit (20).

This frame pulse detection circuit (20) detects the degree of correlation between adjacent lines, and determines that frame pulses of lines numbered 1 and 2 have been detected when the correlation is smaller than a predetermined value. (For example, Japanese Patent Publication No. 6
1-261973). The frame pulse detection circuit (20) outputs a frame pulse detection signal FPD indicating detection of a frame pulse and a key timing pulse for extracting an HD signal based on the frame pulse.

(21) shows an HD signal extraction circuit for extracting the HD signal from the digital signal DS using the key timing pulse, and (22) shows a phase error detection circuit for detecting the phase error of the extracted HD signal. From the signal sampling circuit (21), the horizontal synchronizing pulse HDP and this horizontal synchronizing pulse HDP are output.
The clock pulse CP for sampling is output by multiplying the frequency of CP so as to minimize the phase error. (23) indicates a counting circuit that counts the horizontal synchronizing pulse HDP, and this counting circuit (23) is reset by the frame pulse detection signal FPD, and when the lines are line numbers 563 and 1125, the DC clamp circuit (19)
A clamp timing pulse is supplied to maintain the clamp level.

To explain the operation of the example in FIG. 9, when frame synchronization is not achieved, such as when turning on tWA or switching channels, the movable contact of the switch circuit (12) is moved to the fixed point (12a).
) side, the movable contact of the switch circuit (13) is the fixed contact (
13a) side, and the frame pulse detection circuit (2
0), frame pulses are detected. In this case, since the peak clamp circuit (2) is provided,
Even if the frame pulse shown in FIG. 7 fluctuates upward or downward, the signal level is returned to the center by conduction of the diode (7) or (6), respectively.

After the frame pulse is detected and frame synchronization is achieved, the DC clamp circuit (14) operates at the correct timing, so the movable contact of the switch circuit (12) is moved to the fixed contact (12b) side, and the switch circuit ( By switching the movable contact 13) to the fixed contact (13b) side, the DC level is clamped in the HD period of FIG. 6 for each line. In this way, the DC clamp circuit (1
4) is operating, there is no direct current fluctuation, so the peak clamp circuit (2) is used in a through state.

[Problem to be solved by the invention]

However, because the MUSE signal is emphasized on the encoder side, overshoot O5 and undershoot Us occur in the frame pulse, as shown in FIG. 7A. Therefore, these overshoes)
A resistor (3) and a capacitor (5) are installed in the peak clamp circuit (2) to suppress O3 and undershoot US.
Since an integrating circuit is provided, the A of the video signal is
When PL (average 11 ft level) is close to the black level or white level, the frame pulse as the digital signal DS no longer crosses the 50% level signal of the luminance signal as shown in FIG. There was an inconvenience that detection could not be performed.

In addition, as shown in FIG. 7A and B, line numbers 1 and 2
The white level WL is displayed at the front of the frame pulse of each line.
and black level BL signals are assigned, so when the APL of the video signal is close to the black level or the white level, the in frame pulse will vary particularly greatly.

Also, the line connecting the input terminal (1) and the A/D converter (15) can be considered as a main line analog signal line through which the original video signal is transmitted; Peak clamp circuit (2) on the signal line
It is generally not desirable to add a time constant circuit like this.

In view of the above, the present invention provides a detection circuit for a frame pulse that is positively synchronized with a video signal and periodically changes by a predetermined cycle, and that detects a frame pulse that does not affect the video signal regardless of the APL of the video signal. The object of the present invention is to always be able to reliably detect the frame pulse without having to give it.

[Means to solve the problem]

As shown in FIG. 1, the present invention is a detection circuit for a frame pulse that periodically changes by a predetermined cycle in positive polarity synchronization with a video signal. The output signal DS of this A/D converter (15) is supplied to a waveform shaping circuit (25) via a digital high-pass filter circuit (24). The frame pulse is detected from the output signal of (25).

[Effect]

According to the present invention, since a peak clamp circuit for frame pulses is not added at the analog signal stage, there is no influence on the video signal.

Furthermore, since a high-pass filter circuit (24) is provided before the waveform shaping circuit (25), the AP of the video signal is
Even if L varies, the frame pulse can be reliably detected.

〔Example〕

Hereinafter, one embodiment of the frame pulse detection circuit according to the present invention will be described with reference to FIGS. 1 to 5. In this example, the present invention is applied to the input section of a MUSE type decoder, and parts in FIG. 1 corresponding to those in FIG. 9 are given the same reference numerals, and detailed explanation thereof will be omitted.

Figure 1 shows the input section of the MUSE type decoder of this example. In Figure 1, the analog MUSE signal supplied to the input terminal (1) is connected to the coupling capacitor (4).
is supplied to the movable contacts of the switch circuit (12), and the fixed contacts of one and the other of the switch circuit (12) are supplied directly and via the DC clamp circuit (14) to the one and the other of the switch circuit (13). Connected to the other fixed contact, the signal appearing at the movable contact of this switch circuit (13) is converted to an A/D converter (15) with a sampling frequency of 16.2Hz.
) into an 8-bit digital signal DS, for example,
This digital signal DS is transferred to a de-emphasis circuit (16)
The signal is then supplied to a main line system circuit (not shown) via a reverse transmission gamma (r-') correction circuit (17). Since DC clamping is performed approximately once per line (one horizontal period), the time constant provided by the coupling capacitor (4) must be sufficiently longer than one horizontal period (29,63 μ5ec).

In the synchronous separation circuit (18), (24) is a high-pass filter (HPF) circuit consisting of a digital filter;
5) indicates a digital comparator, and a high-frequency digital signal HPDS obtained by filtering the digital signal DS with a high-pass filter circuit (24) and a reference signal (2) having a value of O. are supplied to the non-inverting input port and the inverting input port of the comparator (25), respectively, and the binary signal output from the comparator (25) is supplied to the frame pulse detection circuit (20). The other configuration of this synchronous separation circuit (18) is the same as the example in FIG. 9.

FIG. 2 shows a specific configuration example of the high-pass filter circuit (24) in the example in FIG. ) ~ (26K) , (27^) ~ (27
J) are delay circuits each having a delay time of 2D, (28A) to (
28K) are adders, and multipliers (29A) to (29L) each multiply the input signal by a coefficient of 22. In this case, delay circuits (26A) to (26K), (
27K) to (27A) are connected in the second order, and the digital signal DS is supplied to the first delay circuit (26A) via the input port (24a), and the delay circuits (26A) to (26K) are connected in the following order.
The input signals to the delay circuits (278) to (27K) are added to the output signals from the delay circuits (278) to (27K) using adders (28A) to (28K), respectively, and the output signals of these adders (28A) to (28K) are The signal is supplied to multipliers (29A) to (29K), respectively, and the output signal of the delay circuit (26K) is supplied to the multiplier (29L). Then, a multi-input adder (30) calculates the sum signal of the output signals of these multipliers (29A) to (29L),
This sum signal is supplied to the comparator (25) in FIG. 1 via the output port (24b). This sum signal becomes the high frequency digital signal HPDs.

In the example in Figure 2, the coefficient KO- multiplied by each multiplier (29A) to (29L) is given a value of 22 as shown in Table 1.The frequency characteristics are as shown in Figure 3, where the cutoff frequency is approximately 0. ．．
It becomes about 5MHz.

When the high-pass filter circuit (25) of the example in FIG. 2 is supplied with a frame pulse whose front signal level is black as shown in FIG. 4A, the frame pulse portion in the output signal is the fourth As shown in Figure B, the DC signal ■ has a value of 0. It was confirmed that the signal oscillates up and down with the center at . Furthermore, when a frame pulse whose front signal level is a white level is supplied to the high bass filter circuit (25) as shown in FIG. 5A, the frame pulse portion of the output signal is as shown in FIG. 5B. A DC signal ■ with a value of 0 as shown in . It was confirmed that the signal oscillates up and down with the center at . In this example, a DC signal ■ whose value is 0 is input to the inverting input port of the digital comparator (25).

is supplied as a reference signal, the frame pulse output from the high-pass filter circuit (24) can always be reliably binarized. Therefore, according to this example, regardless of the APL of the video signal, and whether the level immediately before the frame pulse is the white level WL or the black level BL, as in line number 1 or 2 (see Figure 7). Even if there is a frame pulse, there is an advantage that the frame pulse [i circuit (20) can always reliably detect the frame pulse.

To explain the overall operation of the example in Figure 1, when the power is turned on or the channel is switched, the movable contacts of the switch circuit (12) and the movable contacts of the switch circuit (13) are connected directly through one fixed contact of each. Connecting. After the frame pulse is detected by the high-pass filter circuit (24), the comparator (25), and the frame pulse detection circuit (20) and frame synchronization is achieved, the switch circuit (12) is used to clamp the DC level. ) and the movable contact of the switch circuit (13) are connected via the other fixed contact and the DC clamp circuit (14). In this case, since frame synchronization has already been achieved and the positions of each horizontal synchronization (HD) signals can be accurately identified, the DC level can be stably clamped by the DC clamp circuit (14).

In this case, in this example, the input terminal (1) and the A/D converter (1)
Since the peak clamp circuit (2) used in the example of FIG. 9 is not added to the main analog signal line between the main line and the main analog signal line (5), there is an advantage that the video signal can be reproduced more faithfully.

Furthermore, in this example, since the peak clamp circuit (2) is not added, overshoot O8 and undershoot US (see FIG. 7A) accompanying the frame pulse cannot be removed; however, for example, as shown in FIG. As shown in B, even though the frame pulse is accompanied by overshoot O3 and undershoot tJs, the output signal is a DC signal (2) with a value of 0. Since the pulse still swings up and down around the center, the frame pulse can be accurately detected even with such overshoot O3 and undershoot US attached.

It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that various configurations may be adopted without departing from the gist of the present invention, such as using a band-pass filter circuit as the high-pass filter circuit.

〔Effect of the invention〕

According to the present invention, there is an advantage that frame pulses can always be detected reliably regardless of the APL of the video signal and without affecting the video signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the input section of a MUSE type decoder according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the high-pass filter (HPF) circuit in the example shown in FIG. 1, and FIG. is a diagram showing the frequency characteristics of the example in Figure 2, Figures 4 and 5 are diagrams each showing examples of input and output signals of the high-pass filter circuit in the example in Figure 2, and Figure 6 is a diagram showing the transmission of the MUSE method. Diagrams showing the information of one frame of the signal, Figures 7 and 8 are respectively MUSE
A signal waveform diagram showing frame pulse waveforms and horizontal synchronization (HD) signal waveforms of the conventional MUSE method, FIG. 9 is a configuration diagram showing the input section of a conventional MUSE method decoder, and FIG. 1O is a signal waveform diagram showing conventional signal waveforms. It is. (4) is a coupling capacitor, (14) is a DC clamp circuit, (15) is an A/D converter, (24) is a high-pass filter (HPF) circuit, and (25) is a digital comparator. Agent Hidemori Matsukuma V. HPF f path rz frame pulse ( ) Fig. 4 HPF hill ffl t, r: 7 rempal 2 (2) @8
Figure-11-Saleful number

Claims (1)

[Claims] In a detection circuit for a frame pulse that periodically changes by a predetermined cycle in positive polarity synchronization with a video signal, an analog input signal is supplied to an analog/digital converter via a coupling capacitor, The frame pulse is characterized in that the output signal of the analog/digital converter is supplied to a waveform shaping circuit via a digital high-pass filter circuit, and the frame pulse is detected from the output signal of the waveform shaping circuit. detection circuit.