JPH0323775A - Frame synchronizing signal detection circuit and input signal discrimination switching device using same - Google Patents

Abstract

PURPOSE:To surely detect a frame synchronizing signal by providing 1st-3rd binarizing means binarizing a MUSE signal, 1st-3rd correlation detectors connecting to the binarizing means, and obtaining OR using noncorrelation logic of the correlation detectors as positive logic. CONSTITUTION:When a frame synchronizing signal is placed in a range from 50% to 100% (from V1 to V2) of an A/D window, a 1st binarizing means 2 taking a C1 as a threshold level to output a binary pattern of the frame synchronizing signal. The 1st-3rd correlation detectors 5, 6, 7 obtain respectively the correlation between lines and in-lines. Then the 1st correlation detector 5 connecting to the 1st binarizing means 2 detects the period of a frame synchronizing signal as noncorrelation, and outputs of the correlation detectors 5, 6, 7 are ORed by an OR circuit 8 to obtain the result of noncorrelation in the frame synchronizing signal period, thereby detecting the synchronizing signal. Similarly, when the frame synchronizing signal is from 25% to 75%, or from 0% to 50%, the frame synchronizing signal is detected surely. Thus, the frame synchronizing signal is stably detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame synchronization signal detection circuit that detects a frame synchronization signal of a positive polarity synchronization format, such as the MUSE system, in which the synchronization signal exists within the range of the video signal level. Regarding. [Prior technology] In 1988, NHK Technical Research developed a method for compressing and transmitting broadband high-definition (high-definition television) signals.
MUSE (Multiple Sub-Ny
quistSagtpling Encoding) method is known.

In this MUSE method, audio and signal processing control information (control signals) are multiplexed during the vertical retrace period, and in order to accurately extract this information, frame synchronization detection is required in the receiver of this MUSE method. is necessary. MUSE
The frame synchronization signal of this method is a positive polarity synchronization signal that is multiplexed within the video signal level range. The signal format consists of two lines of signals as shown in Figure 7, and the signal pattern is such that neither the correlation between the frame synchronization signals between the two lines nor the correlation within the line is the same as that of the video signal. .

As a method for detecting this frame synchronization signal, as described in Japanese Patent Laid-Open No. 61-248674, the analog MUSE signal to be transmitted is converted into an analog-to-digital converter (
A known method is to use the most significant bit (MSB) of A/D conversion to determine inter-line and intra-line correlations, thereby distinguishing and detecting frame synchronization signals and video signals.

[Problem to be solved by the invention]

In the above conventional example, when the frame synchronization signal is not detected and synchronization has not been established, such as immediately after the start of reception, when the entire screen is white or black,
For the following reasons, there was a problem that the frame synchronization signal could not be detected and the time until synchronization was established was delayed. In the MUSE receiver, digital processing is used to demodulate the band-compressed MUSE signal to the original wideband high-definition signal.
Analogue digital conversion of USE signal (A/D conversion)
do.

In the A/D converter, the conversion voltage range is Vo to V2 (
Hereinafter, this will be referred to as the A/D window, and the potential corresponding to the voltage VO or its quantized value will be the 0% level of the A/D window, and the potential corresponding to the potential V2 or its quantized value will be the A/D window's 0% level. Expressed as 100% level of the window. ), and for example, when converting to an 8-bit digital value, the voltage vO is (o
ooooooo) , voltage v2 (11111111)
When linearly quantized, the medium-heat voltage V 1 (=2) of Vl-VO is (10000000
), and when the input signal voltage V is in the range v2≧V≧v1, the MSB of the digital value to be quantized is always 1, V
When l>V≧VO, the MSB of the digital value to be quantized is always O. From this, detecting a frame synchronization signal using the MSB corresponds to using a signal obtained by binarizing the input signal using the 50% level of the A/D window as the threshold.

On the other hand, in order to make effective use of the dynamic range of the A/D converter, clamping is normally performed before the A/D converter. In the case of the MUSE method, 50% of the amplitude of the luminance signal
% level is used as a reference level for clamping, and one line (clamp level line) is multiplexed during the vertical retrace period, and clamping is performed so that this level becomes the voltage in (1) above. Therefore, when the clamp level line is clamped to a potential of <Vl (the center of the A/D window) as shown in FIG. 8(a), the frame synchronization signal is % to 75%, and the binarized pattern of the frame synchronization signal is obtained in the MSB. In addition, even if another signal line is clamped instead of the clamp level line under conditions where synchronization has not been established, such as immediately after the start of reception, if the signal level is near the reference level, the MSB will be set to normal. You can obtain the pattern of the frame synchronization signal in the same way as . However, under such conditions, when a video signal that makes the entire screen black or white is input over several fields, if the video signal line is clamped, the black level of the video signal becomes v1 as shown in FIG. 8(b), for example. , and the frame synchronization signal is located between 50% and 100% of the A/D window. Therefore, no frame synchronization signal pattern is obtained in the MSB, and during this period, it becomes impossible to detect a synchronization signal, resulting in a delay in the time until synchronization is established.

An object of the present invention is to provide a frame synchronization signal detection circuit that can reliably detect a frame synchronization signal even under conditions where synchronization has not been established, such as immediately after the start of reception. [Means for solving the problem] The above purpose is to set the threshold C1 to be a value in the range of 50% to 100% of the A/D window, the threshold C2 to be set to a value of 50%, and The first step is to binarize the MUSE signal using a threshold C3 determined by a value in the range of % to 50%.
, a third binarization means, first to third correlation detectors connected to the first to third binarization means, and a logical OR with the non-correlation logic of the correlation detector being a positive logic. This is achieved by finding . [Operation] When the frame synchronization signal is located in the range of 50% to 100% (Vl to V2) of the A/D window as described above, the first binarization using C1 as the threshold value is performed. Means outputs a binary pattern of frame synchronization signals. 1st to 3rd
The correlation detectors determine inter-line and intra-line correlations, respectively. Therefore, the first correlation detector connected to the first binarization means can detect the period of the frame synchronization signal as uncorrelated. Therefore, by calculating the logical sum of the outputs of each correlation detector, a non-correlation detection result for the frame synchronization signal period can be obtained, and a synchronization signal can be detected. Similarly, when the frame synchronization signal is between 25% and 75%, the second binarization means with C2 as the threshold and the second correlation detector connected thereto also detect the frame. When the synchronization signal is between 0% and 50%, non-correlation of the frame synchronization signal period is detected from the third binarization means using the previous Wc3 as a threshold and the third correlation detector connected thereto. The result is obtained. Therefore, even if synchronization is not established immediately after reception starts and clamping is performed incorrectly, the frame synchronization signal can be reliably detected. [Example] An example of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention, l is an input terminal of the MUSE signal, 2, 3.4 is a first
, second and third comparators, 5, 6 and 7 are the first, second and third comparators.
8 is the first OR circuit, 9 is the integrator, l
O is the fourth comparator, and 11 is the output terminal. Figure 2 shows
This is a diagram showing the signal waveforms of each part of the circuit configuration diagram shown in FIG. 1. As mentioned above, immediately after the start of reception, the entire screen is in a black level state, and the frame synchronization signal is output from the A/D when the clamping is incorrect. This shows the operation when the window is located in the range of 50% to 100% of the window. Note that the frame synchronization signal waveform of the MUSE signal in the figure is shown in a simplified manner. Input terminal 1 is the input terminal for the MUSE signal, and now, in the state shown in FIG. 2 (α>), the MUSE signal is
Power is given to one side of each of the second and third comparators 2 and 3.4. The first comparator 2 has a threshold value C1 given to its other input, and compares whether the level of the input MUSE signal is larger or smaller than the threshold value C1. Outputs O. As a result, the output of the comparator contains the MU binarized at the Cl level.
SE signal is obtained. Similarly, the second comparator 3 is set to 2 by the threshold value C2, and the third comparator 4 is set to 2 by the threshold value C3.
Perform valorization. This threshold value C1 is 50% of the A/D window.
The threshold C2 takes a value in the range of 100%, the threshold C3 takes a value in the range from 0% to 50%, for example, as shown in Figure 2 (α). Set 01 to a value of 75% and set C3 to a level of 25%. Therefore, the output of the first comparator 2 provides a binarized pattern of the frame synchronization signal as shown in FIG. 2(b). Furthermore, since the signal level of the second comparator 3 is always in a range larger than the threshold value C2, the output of the second comparator 3 is constantly outputted as 1 as shown in FIG. 2 (Q). The output of device 4 also always outputs 1 as shown in Figure 2(d). first to third correlation detectors 5,
6.7 each detects the autocorrelation of the input binary signal, and the detection circuit for detecting the frame synchronization signal of the MUSE signal is configured to detect the autocorrelation of the input binary signal. An IH delay line delays the binarized signal by LH (H indicates one horizontal scanning period), a 4CK delay line delays the binary signal by 4CK (CK indicates a transmission clock), and 1H.
a first exclusive OR circuit which receives the input/output signals of the delay line; The LH
Conditions where the logics do not match at distant points and the logics do not match at points 4ck apart are output as ``no correlation J (=1). Therefore, the output of the first correlation detector 5, which inputs the output of the first comparator 2, has a large time width only in the latter half of the second line, as shown in FIG. 2(e). A detection result of ``None'' is obtained.In addition, the second comparator 3
Since there is no change in the input signal, the output of the second correlation detector 6 which receives the output of The output of the third correlation detector 7 which receives the output of the comparator 4 as input is shown in FIG.
)become that way.

The first OR circuit 8 receives the outputs of the first to third correlation detectors 5, 6.7 as input, and calculates the OR with the "no correlation" logic as positive logic. As shown in FIG. 2(h), a signal from which the frame synchronization signal period can be determined can be obtained.

The integrator 9 receives the output of the first OR circuit 8 as an input, and performs integration to detect whether or not a period of "no correlation" has occurred continuously for a certain period or more. this is,
For example, a k-bit counter is used, the output of the first OR circuit 8 is connected to its reset terminal, and the period of ``with correlation'' is reset, and the counting is performed with the period of ``r'' without correlation. By doing so, it is possible to obtain an integration result for the count value (k-bit output of the counter). Therefore, the integrator 9 shows a large value only in the latter half of the second line, as shown in Figure 2 (i) (here, the counting results are displayed in analog form), and the value shown in Figure 2 (i) is large. The output of the integrator 9 is applied to one input of the fourth comparator 10, and the output of the fourth comparator LO(1) is applied to the other input of the fourth comparator 10. is given a threshold value S. This fourth comparator 10 outputs 1 when a value larger than the threshold value S is generated by the integrator 9, and outputs O when the value is smaller. The “no correlation” detection result that occurs in the second half of the second line is approximately 140c.
By selecting the threshold value S to a value such as 128, it is possible to eliminate detection results of "slight r no correlation" occurring in other lines, and the fourth comparator 10 As the output, a pulse with a period of 1 frame sliced by the threshold value S is obtained as shown in FIG. 2(j). Therefore, the detection pulse of the frame synchronization signal can be obtained from the output terminal 11 connected to the output of this fourth comparator IO. Also, due to a clamp error, the MUSE signal may be 0% of the A/D window.
If the position is within 50% of the range, the third comparator 4
Therefore, it is obvious that when the comparator is in the normal position, a binary pattern can be extracted from the second comparator 3, and a detection pulse can be obtained at the output terminal 11 in the same way. According to this embodiment, it is possible to reliably detect a frame synchronization signal even when synchronization has not been established and a clamp error occurs, such as immediately after the start of reception. Furthermore, since a comparator is used as the binarization means to give a degree of freedom to the threshold value, it is also possible to adaptively change the threshold value, for example, by following changes in the surrounding environment.

Furthermore, the detection circuit of this embodiment depends on whether at least the first to third comparators are configured in an analog manner or in a digital manner. Analog MU before A/D conversion
The present invention is applicable to both the SE signal and the MUSE signal that has been converted into a digital power set after A/D conversion. Such a frame synchronization signal detection circuit can also be used to discriminate signals between the current NTSC system and MUSE system, for example, by integrating the frame synchronization detection pulse and determining periodicity. For example, NTS
A shared receiver that can receive both C-system broadcasting and MUSE-system high-definition broadcasting is conceivable, but
When attempting to share the /D converter and the digital No. 48 processing circuit, it is necessary to switch the system clock, etc., making it difficult to digitally construct a frame synchronization detection circuit and automatically discriminate signals. Therefore, in such a case, a detection circuit that directly binarizes the analog signal before A/D conversion and detects the MUSE frame synchronization signal can be effectively used. An example of this is shown in FIG.

In FIG. 9, an analog video signal input from an input terminal l7 is passed through a clamp circuit 31 to an A/D converter 2.
0, is led to a frame synchronization signal detection circuit 18 constructed from the embodiment shown in FIG. The clamp circuit 31 switches the reference level of the clamp between the NTSC signal (pedestal or sync tip clamp) and the MUSE signal (neutral level clamp) under the control of the determiner 19.
Ensure that the signal is within the normal range. The A/D converted digital video signal is sent to the MUSE synchronization processing circuit 2.
1. It is applied to the NTSC synchronization processing circuit 22, the MUSE signal processing circuit 27, and the NTSC signal processing circuit 'd428. M
The system clock fM output from the USE synchronization processing circuit 2l and the system clock fM output from the NTSC synchronization processing circuit 22. is a synchronization signal MSYNC (HD, VD or multiple synchronization signal) given to the input of the switch circuit 23 and output from the MUSE synchronization processing circuit 2l, and a synchronization signal (
HD, VD, or multiple synchronous signals) are applied to the input of the switch circuit 24. MUSE signal processing circuit 26 and common signal processing circuit 27 (for example, frame memory,
signal MS (R, G, B or Y, R-Y, B-Y) processed by the filter) and the NTS C signal processing circuit 2
8 and the signal NS processed by the common signal processing circuit 27
(R, G, B or Y, R-Y, B-Y) is given to the input of the switch circuit 29. The output of the switch circuit 23 supplies a system clock to the digital section.
The output of the switch circuit 24 is connected to a synchronization signal output terminal 25, and the output of the switch circuit 29 is connected to a video signal output terminal. In addition, the switch circuits 23, 24, 29 are
It is controlled by the output of judge l9. The determiner 19 can be composed of, for example, a retriggerable one-shot circuit, and the time constant of the one-shot circuit is selected to be at least one frame period and within two frame periods of the MUSE signal. Assume that According to this, when the frame synchronization signal detection circuit 18 detects frame synchronization of the MUSE signal and generates a detection pulse, the determination period 19 is triggered every frame, and its output cannot show a steady value. can. (For example, the set time constant period becomes 1 when the trigger occurs, and becomes 0 when the trigger no longer occurs.) Therefore, according to the frame synchronization signal detection circuit of the present invention, the clamp is Regardless of whether it is in the MUSE or NTSC state, if a MUSE signal is input, it can be detected reliably, and there is no need for a dedicated A/D converter for signal discrimination, which reduces costs. It is also advantageous. Next, another embodiment of the present invention will be explained using FIGS. 3 and 4. In Figure 3, 12 is an A/D converted MUS
The n-bit word line l3 representing the E signal is a positive logic AND circuit. 14 is a negative logic AND circuit, and the rest is the same as in the previous embodiment. FIG. 2 is a diagram explaining the binarization means of this embodiment. In this embodiment, the threshold value C
1 is the 75% quantization value of the A/D window, and threshold C2 is 5.
The quantization value is set to 0%, and the threshold value C3 is set to the quantization value of 25%.

The A/D converted n-bit MUSE signal is represented by n words lX12, and bits representing the MSB and its lower digit (hereinafter referred to as MSB-1).

) is supplied to the input of the positive logic AND circuit 13 and the input of the negative logic AND circuit 14. Further, the output of the positive logic AND circuit Ia13 is input to the input of the first correlation detector 5, and the MSB is input to the input of the second correlation detector 6.
The output of the negative logic AND circuit l4 is connected to the input of the third correlation detector, and the subsequent configuration is the same as in the previous embodiment. The positive logic AND circuit 13 calculates the positive logic AND of the MSB and MSB-1. Therefore, for example, when quantizing with 8 bits, the quantization value is 255 (1
1111111) 7)% et al. 192 (11 million
) Since the MSB and MSB-1 bits are always 1 in the range of
55-192) is 1, less than that (191-0)
Outputs O when . Therefore, this positive logic AND circuit 13 can provide the first correlation detector 5 with a signal obtained by binarizing the MUSE signal using the 75% value of the A/D window as a threshold value.

The MSB has a quantization value of 128 (10000000) to 255 (11111) as shown in the MSB column in Figure 4.
111) is 1%, and the range from 127 (01111111) to o (oooooooo) is O, so it is exactly A
This corresponds to binarizing the MUSE signal using 50% of the /D window as the threshold. Therefore, a binary signal with a threshold value of 50% can be achieved by directly applying the MSB to the second correlation detector 6.

The negative logic AND circuit 14 calculates the negative logic AND of MSB and MSB-1. Therefore, the quantization value changes from 63 (00111111) to o (oooooo
oO) within the range of MSB and MS. Since the bit with B-1 is always O, as shown in the AND column in Figure 4, when the input signal level is below 25% of the A/D window (63 to 0 in this case). O, outputs 1 when it is above that level. Therefore, this negative logic AND circuit 14 is an A/D
A signal obtained by binarizing the MUSE signal using a value of 25% of the window as a threshold value can be provided to the third correlation detector 7.

Therefore, when the frame synchronization signal is located in the range shown in the α column of the input signal example in FIG. 4 due to a malfunction of the clamp, the first correlation detector 5 When the position is as shown in column b of the input signal example in the same figure, the second correlation detector 6 detects
If located as shown in the column, the third correlation detector 7
A signal including logic capable of determining a frame synchronization signal can be obtained from the above. The outputs of these correlation detectors 5, 6.7 are subjected to the same processing as in the previous embodiment in the first OR circuit 8, integrator 9, and fourth comparator IO, so that the output From terminal H, a detection pulse of a frame synchronization signal can be obtained.

Therefore, according to this embodiment, the object of the present invention is achieved, and the threshold value for binarization is set to 75% and 50% of the A/D window.
, by setting it at 25%. The binarization means can be simplified and the circuit scale can be reduced.

Next, still another embodiment of the present invention will be described with reference to FIGS. 5 and 6. In FIG. 5, 15 is an exclusive OR circuit, 16 is a second OR circuit, and the others are the same as in the previous embodiment. FIG. 6 is an explanatory diagram of the binarization means of this embodiment. M. of the word line 12 of the digital MUSE signal quantized to n bits. The bit lines of SB and MSB-1 are connected to the input terminal of exclusive OR circuit l5. Also, the first
The correlation detector 5 and the second correlation detector 6 have the same configuration as in the previous embodiment. The input of the first correlation detector 5 is supplied with the output of the exclusive OR circuit, and the input of the second correlation detector 6 is supplied with the bit line of the MSB.

The second OR circuit 16 inputs the output of the first correlation detector 5 and the output of the second correlation detector 6, and similarly to the first OR circuit 8, it has a "no correlation" logic. The output is connected to the input of the first integrator 9. The structure after this integrator 9 is the same as that of the previous embodiment. The former exclusive OR circuit 15 is MS
This is to obtain the exclusive OR of B and MSB-1.

Therefore, in the case of 8-bit quantization, 192 (110
00000) to 255 (11111111) and 63 (00111111) to Q (000000
The bit values of MSB and MSB-1 match in the range of 00), and the values do not match in the other range (64 to 191), so the level of the input signal is changed as shown in the EX-OR column of Figure 6. is more than 75% of the A/D window (192-255) and 2
1 if below 5% (63-0), 7 from 25%
Outputs O when the range is up to 5% (64 to 191). Therefore, when the frame synchronization signal is located as shown in the Q column of the input signal example in FIG. 6 or as shown in the C column of the input signal example in the same figure, the exclusive OR circuit l5 A binarized pattern of the frame synchronization signal can be obtained as the output. In this case, the polarity of the binarized pattern to be output will be reversed depending on whether it is located as in the α column or as in the C column of the input signal example in FIG. Correlation detection is to find logical mismatch between lines within a line, so even if the polarity of the output signal is reversed, the detection process and detection results are not affected.

Therefore, when the frame synchronization signal is located as shown in the α column and C column of the input signal example in FIG. It will be done. Also, b41 in the input signal example in FIG.
1, a signal from which the frame synchronization signal can be determined can be obtained from the second correlation detector 6 to which the first MSB is connected, as in the previous embodiment.

Therefore, in this embodiment as well, the frame synchronization signal can be reliably detected even if the clamping is erroneous when synchronization is not established and the human input signal is not within the normal range with respect to the A/D window. Also. Since binarization using 75% of A/D as a threshold value and binarization using 25% of A/D as a threshold value can be performed at once, the purpose of the present invention can be achieved with two correlation detectors. It is possible to reduce the circuit scale.

Note that the present invention is not limited to the MUSE signal, but can be applied to any video signal whose synchronization signal is a binary pattern that has no correlation with the video signal on a predetermined line, and the correlation detector can be configured accordingly. By changing the above, the invention can be effectively applied without detracting from the gist of the invention.

〔Effect of the invention〕

According to the present invention, even if a signal is clamped to an incorrect level in a transient state such as immediately after the start of reception, a frame synchronization signal can be detected stably, and the time required for establishing synchronization of a receiver can be reduced. .

[Brief explanation of the drawing]

Claims (1)

[Claims] 1. A frame synchronization signal detection circuit which receives a television signal, detects a positive polarity synchronization format frame synchronization signal from the input television signal, and outputs the result. When the voltage range (hereinafter referred to as window) for converting a television signal from analog to digital is 100%, the input television signal is at least 2 times the threshold value determined by a value in the range of 0% to 50% of the window. a first binarization means for converting into a value, a second binarization means for binarizing the input television signal using a value of 50% of the window as a threshold; A third binarizing means binarizes the previously input television signal with a threshold value determined by a value in the range from 100% to 100%, and the output signal of the first binarizing means is inputted. Detects the correlation between the detected signals and outputs the results. The output signals of the first correlation detector and the second binarization means are input, and the correlation between the input signals is detected and the result is output. The output signals of the second correlation detector and the third binarization means are input,
Detects the correlation of input signals and outputs the results. A third correlation detector is input with the output signal of the first correlation detector, the output signal of the second correlation detector, and the output signal of the third correlation detector, and 1. A frame synchronization signal detection circuit comprising detection means for detecting that any of the correlation detectors detects no correlation and outputting a signal. 2. The threshold value of the first binarization means is 25% of the window.
and the threshold value of the second binarization means is 50% of the window.
The threshold value of the third binarization means is 75% of the window.
The frame synchronization signal detection circuit according to claim 1, characterized in that: 3. A frame synchronization signal detection circuit for detecting a frame synchronization signal in the positive polarity synchronization format, which detects at least the input M
A/A converting the USE signal into an n-bit digital signal
a D converter, an exclusive OR circuit to which the MSB bit signal and the MSB-1 bit signal of the digital signal are input, and a first correlation to which the output signal of the exclusive OR circuit is input. a second correlation detector to which the MSB signal is input; an output signal of the first detector and an output signal of the second correlation detector are input; 1. A frame synchronization signal detection circuit comprising: detection means for detecting that at least one of the first correlation detector and the second correlation detector detects that there is no correlation, and outputting the result. 4. An input terminal into which a first television signal or a second television signal with a different synchronization format is input, and a system clock is supplied, and the television signal input to the input terminal is A/D converted and output. an A/D converter; a first signal processing circuit that processes a first television signal converted into a digital signal output from the A/D converter;
A second signal processing circuit that processes a second television signal converted into a digital signal output from the /D converter and output signals of the first and second signal processing circuits are input,
a switch circuit that selects and outputs one of the input signals; and a switch circuit that selects and outputs one of the input signals; and a switch circuit that selects and outputs one of the input signals; A frame synchronization signal detection circuit according to claim 1, which receives a television signal, detects a frame synchronization signal in a positive polarity synchronization format, and outputs the result, and integrates and outputs an output signal of the frame synchronization signal detection circuit. an integrator, a comparator that determines whether the output signal of the integrator exceeds a predetermined value and outputs the result, and whether a detection pulse of a frame synchronization signal is generated in the output signal of the comparator. , and a determiner that determines whether the output signal is , or not, the switch circuit is controlled by an output signal of the determiner, and a system clock supplied to the A/D converter is switched. An input signal discrimination switching device using a frame synchronization signal detection circuit.