JPH04355569A - Synchronizing signal processing unit - Google Patents

Abstract

PURPOSE:To process a binary synchronizing signal and a ternary synchronizing signal properly respectively. CONSTITUTION:A 1/4H pulse generating circuit 6 receiving a single pole binary synchronizing signal or a bipolar ternary synchronizing signal generates a pulse consecutive at least in excess of a pulse width more than a half of that of the ternary synchronizing signal and a NAND gate circuit 7 ANDs the generated pulse with the original synchronizing signal to discriminate the presence of an AND output for a vertical blanking period thereby deciding whether the synchronizing signal is the binary or the ternary synchronizing signal. In the case of the ternary synchronizing signal, a 3/4H pulse generating circuit 9 deletes only the AND output relating to the equalizing pulse for the vertical blanking period from the AND output to convert the synchronizing signal into the binary synchronizing signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal processing device for discriminating a three-value synchronization signal and converting the waveform into a two-value synchronization signal.

0002

[Prior Art] A high-definition synchronization signal not only serves as a scanning reference for screen scanning, but also as a phase reference for three channels of parallel transmission of each component signal of a luminance signal and a chrominance signal. Particular precision is required for extraction. For this reason, in consideration of the ease of synchronization detection and phase management, high-definition television uses a three-level synchronization signal consisting of a bipolar three-level pulse waveform with positive and negative symmetry. Even if the received waveform is distorted from the original waveform due to the influence of the characteristics, it is said that by setting the slice level to the pedestal level, the reproduction synchronization phase can be kept the same as the ideal transmission path. Figures 6 (A) to (D) are waveform diagrams of high-definition synchronization signals. As can be seen from Figure 6 (B), the phase reference of the horizontal synchronization signal is the part where the pulse of negative polarity rises to the pulse of positive polarity. It is given as a zero crossing point that intersects with the pedestal level. In addition, in the vertical blanking period, which is set as a period five times the horizontal scanning period H, an equalization pulse is inserted in the middle of the horizontal synchronization pulse, and in odd fields, the zero-crossing point of the first equalization pulse is also In even fields, the zero-crossing points of the horizontal sync pulses following the first equalization pulse each provide a phase reference for the vertical sync signal.

0003

[Problem to be Solved by the Invention] A deflection circuit in a high-definition receiver captures the phase of the part where the polarity is reversed from a negative polarity pulse to a positive polarity pulse with respect to a ternary synchronization signal separated from a video signal, and uses this as a phase reference. Although it is necessary to generate a binary synchronization signal, there are cases where the current standard television signal is played back on a high-definition receiver by doubling the number of scanning lines, so the synchronization signal processing device in the high-definition receiver is It is necessary to appropriately process both the high-definition three-value synchronization signal and the current television standard system binary synchronization signal. However, conventional synchronization signal processing devices of this kind are too insistent on compatibility with the current television standard system, for example, they simply extract only the negative polarity pulse from the ternary synchronization signal, and use the falling part to perform the reference synchronization. The synchronization phase is extremely inaccurate, and this shift in the synchronization phase may have a negative effect on the deflection system, or the phase of the clamp pulse that is generated using the synchronization signal as a phase reference may shift. There were also problems with video clamping, such as noticeable mistakes. There is also a method that uses the trailing edge of the negative polarity pulse separated from the ternary synchronization signal as the phase reference, but for example, if the received waveform is distorted from the original waveform during the transmission process, playback synchronization using the slice level can be used as the phase reference. Since phase errors are unavoidable and the synchronization phase is disturbed during the vertical blanking period when equalization pulses are inserted, for example, in high-definition receivers that perform calculations for digital convergence even during the vertical blanking period, convergence correction is necessary. As a result of the calculation being disrupted, there was a problem in that convergence shifts were likely to occur at the top of the screen.

0004

[Means for Solving the Problems] The present invention has solved the above-mentioned problems, and a unipolar binary synchronization signal or a bipolar three-value synchronization signal is supplied, and the three-value synchronization is performed by a leading edge trigger. a pulse generation circuit that generates a pulse that lasts for at least half the pulse width of the signal; an AND gate that ANDs the output pulse of the pulse generation circuit with the original synchronization signal; The presence or absence of the AND output of the product gate is determined, and the synchronization signal is 3.
The first feature is that it includes a determining means for specifying whether it is a value or a binary value.

The present invention also provides a pulse generation circuit that generates a pulse having a pulse width exceeding at least half of the three-level synchronization signal from the leading edge of the three-level synchronization signal; An AND gate that takes an AND with the value synchronization signal, and from the AND output of this AND gate, only the AND output related to the equalization pulse in the vertical blanking period is deleted, and the zero-crossing point of the three-value synchronization signal is set to the phase. A second feature of the present invention is that it includes a masking means for obtaining a series of binary synchronization signals at intervals of one horizontal scanning period as a reference.

Furthermore, the present invention provides an amplitude separation circuit which is supplied with a unipolar binary synchronization signal or a bipolar three-value synchronization signal and separates the amplitude into positive and negative polarities at a pedestal level; a pulse generation circuit that inverts the polarity of the preceding pulse of the amplitude-separated preceding pulse and the following pulse, and generates a pulse that lasts at least over half the pulse width of the ternary synchronization signal by a leading edge trigger; The present invention further includes determining means for performing a logical product of the output of the pulse generation circuit and the subsequent pulse, and determining whether the synchronizing signal is 3-valued or 2-valued depending on the presence or absence of the logical product output. This is characterized by the following three characteristics.

[0007]

[Operation] This invention generates a pulse that lasts at least half the pulse width of the ternary sync signal from a unipolar binary sync signal or a bipolar ternary sync signal by a leading edge trigger, and then It is determined whether the synchronization signal is three-valued or binary by calculating the AND with the original synchronization signal and determining the presence or absence of the AND output during the vertical blanking period. Further, as for the three-value synchronization signal, the waveform is converted into a two-value synchronization signal by erasing only the AND output related to the equalization pulse in the vertical blanking period from the AND output.

Furthermore, the amplitude of a unipolar binary sync signal or a ternary sync signal of positive and negative polarities is separated into positive and negative polarities using a pedestal level, and of the amplitude-separated preceding pulse and subsequent pulse, the preceding pulse is After reversing the polarity of
The leading edge trigger generates a pulse that lasts at least half the pulse width of the ternary sync signal, and by ANDing this pulse with the subsequent pulse, the sync signal becomes 3 depending on the presence or absence of the AND output. Specify whether it is a value or a binary value.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 5. FIG. 1 is a circuit diagram showing an embodiment of the synchronous signal processing device of the present invention, and FIGS. 2 and 3 are
FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1 when processing a three-value synchronization signal and a two-value synchronization signal, respectively.

The synchronization signal processing device 1 shown in FIG. 1 operates by a synchronization waveform discrimination circuit 2 for discriminating waveforms between a binary synchronization signal and a three-value synchronization signal, and a three-value discrimination output from this synchronization waveform discrimination circuit 2. It consists of a synchronous waveform conversion circuit 3 that converts a value synchronous signal into a binary synchronous signal. The synchronization waveform discrimination circuit 3 generates a pulse that lasts from the leading edge of the binary or three-value synchronization signal over at least half of the pulse width of the three-value synchronization signal, and distinguishes between the generated pulse and the logic of the original synchronization signal. The product is used to discriminate between binary and ternary values. In addition, the synchronous waveform conversion circuit 3 is
Since the leading edge of the AND output indicating the above discrimination result provides the zero-crossing point of the ternary synchronization signal, by generating a pulse with an appropriate pulse width from this zero-crossing point, the ternary -2
Performs value conversion.

[0011] A high-definition or current television standard video signal is first separated in a synchronization separation circuit 4 into which only the synchronization signal portion is separated. The separated synchronization signal is amplified by the subsequent buffer amplifier 5 into a pulse having an amplitude value of 5Vp-p. Next, in the 1/4H pulse generation circuit 6,
A pulse with a pulse width of 1/4 of the high-definition horizontal scanning period H, that is, 1/2 of the pulse width of the ternary synchronization signal
Generate pulses well in excess of . The pulse generated by the 1/4H pulse generation circuit 6 is supplied to the NAND gate circuit 7 and subjected to an AND operation with the output of the buffer amplifier 5. As a result, if it is a three-value synchronization signal, as shown in FIG.
A value pulse is obtained. However, in the case of a binary synchronization signal,
As shown in FIG. 3(D), since the NAND gate circuit 7 generates a pulse that rises at the trailing edge of the original synchronization signal, it is naturally necessary to eliminate this pulse. Therefore, the output of the NAND gate circuit 7 is activated only when the above-mentioned synchronization waveform discrimination circuit 2 discriminates a three-level synchronization signal, in other words, the output of the buffer amplifier 5 can be extracted as is for a two-level synchronization signal. The final stage changeover switch 8 is configured to be switched in accordance with the result of synchronous waveform discrimination.

By the way, since the equalization pulse inserted at 1/2H cycle within the vertical blanking period remains in the binary pulse obtained from the three-level synchronization signal by the NAND gate circuit 7, the embodiment Now, the leading edge of the output of the NAND gate circuit 7 triggers the 3/4H pulse generation circuit 9, which is a masking means, and the pulse continues for 3/4 times the horizontal scanning period H, as shown in FIG. 2(E). A 3/4H pulse is generated. However, the 3/4H pulse generation circuit 9 has a structure in which no retrigger is applied during the pulse generation period, and therefore the equalization pulse is masked to the 3/4H pulse and erased. The positive polarity pulse that falls every 1H period is finally converted by the pulse width adjustment circuit 10 into a pulse shown in FIG. It is output to the outside via 8.

Note that the output of the NAND gate circuit 7 during the vertical blanking period is greatly different between the binary sync signal and the ternary sync signal, and the ternary sync signal outputs a pulse even during the vertical blanking period. In contrast, the binary synchronization signal has a difference in that no pulse is output except immediately after the start of the vertical blanking period. For this reason, the synchronous waveform discrimination circuit 2 shown in the embodiment checks the presence or absence of the output pulse of the NAND gate circuit 7 when one horizontal scanning period has elapsed from the start point of the vertical blanking period, and discriminates the waveform. There is.

That is, the output of the buffer amplifier 5 is supplied to a vertical synchronization separation circuit 11, where the vertical synchronization signal is separated. Next, the separated vertical synchronization signal is sent to the 1H delay circuit 1.
After being delayed by one horizontal scanning period in step 2, the 2H pulse generation circuit 13 generates a pulse lasting two horizontal scanning periods as shown in FIG. 2(G). generated 2H
The pulse is transmitted from the output of the NAND gate circuit 7 to the inverter 14.
It is supplied to the NAND gate circuit 15 together with the output whose polarity has been inverted at , where it is subjected to an AND operation to discriminate between binary and ternary values. In other words, for the binary synchronization signal, FIG.
As shown in (G), the discrimination output is always at a high level, whereas for the ternary synchronization signal, as shown in Fig. 2 (H), there are four negative polarity pulses during the 2H period. can get. Therefore, the discrimination output obtained from the NAND gate circuit 15 is sent to the one-shot circuit 16 for one vertical scanning period V.
By converting the pulse into a pulse that lasts for 20 seconds and supplying it to the changeover switch 8 as a changeover control signal, appropriate waveform conversion is performed according to the determination result.

[0015] In this way, the synchronization signal processing device 1 has the following features:
A binary synchronization signal and a three-value synchronization signal can be distinguished by using the difference in waveform of the equalization pulse inserted within the vertical blanking period. Therefore, when a high-definition receiver is supplied with a video signal that complies with the current television standard system, it may be necessary to perform a waveform conversion process on the binary synchronization signal from three-level synchronization to binary synchronization, which is meaningless and harmful. Signal processing can be avoided. On the other hand, when high-definition signals are supplied to current television receivers, by converting the 3-level synchronization signal to a binary sync signal, disturbances in the deflection system and video clamping can be avoided. Failures etc. can be avoided. Also, 3
Regarding the value synchronization signal, the waveform can be converted into a binary synchronization signal by erasing only the AND output related to the equalization pulse in the vertical blanking period from the AND output of the NAND gate circuit 7. 2
By sharing a part of the synchronous waveform conversion circuit 3 with the synchronous waveform conversion circuit 3, the overall circuit configuration can be simplified.

[0016] It is also possible to use a synchronization waveform discriminating circuit 22 different from the one described above, such as the synchronization signal processing device 21 shown in FIG. The synchronous waveform discrimination circuit 22 shown in the same figure is
First, the video signal is amplitude-separated into a positive pulse and a negative pulse using the pedestal as a reference in an amplitude separation circuit 25 consisting of a positive pulse comparator 23 and a negative pulse comparator 24. At this time, as a matter of course, positive polarity pulses are not separated from the binary synchronization signal consisting only of negative polarity pulses, and only positive polarity pulses and negative polarity pulses are separated from the ternary synchronization signal. However, for positive polarity pulses, both the binary and ternary synchronization signals also separate the video signal in addition to the synchronization signal. Then, the negative pulse separated by the negative pulse comparator 24 is passed through the one-shot circuit 26 for a time T1 (=
1.185 μs) and also time T2 (=3.17
After converting the one-shot pulse into a one-shot pulse having a pulse width T of less than 9 μs, it is subjected to a match determination with the output of the positive pulse comparator 23.

That is, here, the time interval from the end point of the video signal to the zero cross point is used as the time T1, while the time interval from the start point of the negative polarity pulse to the start point of the video signal is used as the time T2. One shot circuit 26
The output of the NAND gate circuit 27, which takes the logical product of the output of
This is obtained as a pulse train as shown in (E). Therefore, the output of the NAND gate circuit 27 is waveform-shaped by a one-shot circuit 28, and the output of the one-shot circuit 28 is used to switch the changeover switch 8.

As described above, according to the synchronization signal processing device 21, since only negative polarity pulses are obtained during amplitude separation for the binary synchronization signal, an AND output cannot be obtained from the NAND gate circuit 27; As for the 3-level sync signal, since the AND output can always be obtained from the NAND gate circuit 27, the difference in the waveform of the equalization pulse inserted within the vertical blanking period can be used to generate the 2-level sync signal and the 3-level sync signal. Unlike the method that determines 2 in all periods,
Waveforms of value synchronization signals and three-value synchronization signals can be easily distinguished.

[0019]

Effects of the Invention As explained above, the present invention can generate a signal from a unipolar binary sync signal or a bipolar ternary sync signal.
Generating a pulse that lasts for at least half the pulse width of the tri-level sync signal by the leading edge trigger, and then performing an AND with the original sync signal to determine the presence or absence of an AND output during the vertical blanking period. Since the configuration is configured to specify whether the synchronization signal is 3-valued or binary,
It is possible to distinguish between a binary synchronization signal and a three-value synchronization signal by using the difference in the waveform of the equalization pulse inserted within the vertical blanking period. It is possible to avoid meaningless and harmful signal processing such as applying waveform conversion processing from three-level synchronization to binary synchronization to the binary synchronization signal when supplying a video signal that is When a high-definition signal is supplied to the receiver, converting the 3-level synchronization signal to a binary sync signal has excellent effects such as avoiding disturbances in the deflection system and failures in video clamping. .

[0020] Furthermore, the present invention has a configuration in which the waveform of the three-value synchronization signal is converted into a two-value synchronization signal by erasing only the AND output related to the equalization pulse in the vertical blanking period from the AND output. Therefore, it is possible to obtain two-level synchronization signals that are continuous at one horizontal scanning period interval using the zero-crossing point of the three-level synchronization signal as a phase reference, and a part of the circuit can be shared with the circuit used for the above-mentioned synchronization waveform discrimination.
Effects such as being able to easily configure a synchronization signal processing device that performs ternary-to-binary conversion according to the synchronization waveform discrimination result are achieved.

Furthermore, the present invention separates the amplitude of a unipolar binary sync signal or a ternary sync signal of positive and negative polarities into positive and negative polarities using a pedestal level, and separates the amplitude of the preceding pulse and the following pulse into which the amplitude is separated. , after inverting the polarity of the preceding pulse, generating a pulse that lasts at least over half the pulse width of the ternary synchronization signal by the leading edge trigger, and logically ANDing this pulse with the subsequent pulse. Since the configuration is configured to specify whether the sync signal is 3-level or 2-level depending on the presence or absence of the product output, only negative polarity pulses can be obtained during amplitude separation for the 2-level sync signal. While a product output cannot be obtained, a logical product output can always be obtained for a 3-level synchronization signal.Therefore, binary synchronization can be performed using the difference in waveform of the equalization pulse inserted within the vertical blanking period. Unlike the method of distinguishing between a signal and a three-value synchronization signal, this method has advantages such as being able to easily distinguish between the waveforms of a binary synchronization signal and a three-value synchronization signal in all periods.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a synchronization signal processing device of the present invention.

FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1 when processing a ternary synchronization signal.

FIG. 3 is a signal waveform diagram of each part of the circuit shown in FIG. 1 when processing a binary synchronization signal.

FIG. 4 is a circuit configuration diagram showing another embodiment of the synchronization signal processing device of the present invention.

FIG. 5 is a signal waveform diagram of each part of the circuit shown in FIG. 4 when processing a ternary synchronization signal.

FIG. 6 is a waveform diagram of a high-definition synchronization signal.

[Explanation of symbols]

1, 21 Synchronous signal processing device 2, 22 Synchronous waveform discrimination circuit 3 Synchronous waveform conversion circuit 6 Pulse generation circuit (1/4H pulse generation circuit) 7
AND gate (NAND gate circuit) 9 Masking means (3/4H pulse generation circuit) 25 Amplitude separation circuit

Claims (3)

[Claims] 1. A pulse that is supplied with a unipolar binary sync signal or a bipolar ternary sync signal, and whose leading edge trigger generates a pulse that lasts for at least half the pulse width of the ternary sync signal. A generation circuit, an AND gate that takes an AND of the output pulse of the pulse generation circuit and the original synchronization signal, and determines whether or not there is an AND output of the AND gate in the vertical blanking period, and determines whether the synchronization signal is 3. A synchronous signal processing device characterized by comprising determining means for specifying whether the signal is a value or a binary value. 2. A pulse generation circuit that generates a pulse having a pulse width exceeding at least half of the three-level synchronization signal from the leading edge of the three-level synchronization signal, and an output pulse of the pulse generation circuit and the original three-level synchronization signal. an AND gate that takes the AND of
From the AND output of this AND gate, only the AND output related to the equalization pulse in the vertical blanking period is deleted, and a binary synchronization signal that continues at one horizontal scanning period interval is generated using the zero-crossing point of the three-level synchronization signal as a phase reference. 1. A synchronous signal processing device comprising masking means for obtaining a signal. 3. An amplitude separation circuit which is supplied with a unipolar binary synchronization signal or a bipolar three-value synchronization signal and separates the amplitude into positive and negative polarities based on the pedestal level, and a preceding signal whose amplitude is separated by the amplitude separation circuit. A pulse generation circuit that inverts the polarity of the preceding pulse among the pulse and the subsequent pulse and generates a pulse that lasts at least over half the pulse width of the three-level synchronization signal by a leading edge trigger, and an output of this pulse generation circuit. and the subsequent pulse, and determining means for determining whether the synchronization signal is three-valued or binary depending on the presence or absence of the logical product output. Device.