JPH03250224A - Error detection condition generating circuit - Google Patents

Abstract

PURPOSE:To dynamically change the detecting condition of error by setting the error detecting condition to an error detecting condition memory capable of rewriting at any time and applying a condition selection instructing signal to the memory as an address signal. CONSTITUTION:The condition selection writing data of (m)X(n) bits is written to an error selecting condition memory 1 while designating the address. The (n) bit of this condition selection writing data is corresponding to the (n) bit of a condition input signal, '0' is written into a bit to be defined as the error detecting condition and '1' is written to the other bit. When the condition input signal is inputted and the address signal of (i) bits is applied, the address is applied through a memory address selection circuit 5 to the error detection memory 1 and reading is instructed. Then, the error detecting condition data of (m + n) bits is applied to condition selection circuits 21-2m together with the condition input signal. Thus, the detecting condition of the error can be dynamically changed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error detection condition generation circuit, and particularly to an error detection condition generation circuit that sets a plurality of error detection conditions in an information processing device.

[Conventional technology]

Conventionally, this rice error detection condition generation circuit has adopted a method in which detection conditions are set and fixed in advance, or a method in which t or suppression of detection can be set.

[Problem to be solved by the invention]

The above-mentioned error detection condition generation circuit requires a large amount of modification man-hours when specifications are changed after the design is completed, and the error detection ability is reduced when error detection is suppressed for error detection conditions that are not set. It has the disadvantage that it decreases.

[Means to solve the problem]

The error detection condition generation circuit of the present invention includes an n-bit condition input signal, an error detection condition memory having an n×m bit width and an address specified by i bits, and when writing to this error detection condition memory. a memory address selection circuit that selects a write address and selects an error selection condition selection signal during reading; a write data bus that writes error detection condition data to the error detection condition memory; The logical sum of the j×n+1st bit to (j+1)×nth bit (j=0 to m−1) of the read pressure data of the memory and the 1st to nth bits of the condition input signal is bit-corresponding. an error detection condition determination circuit that takes the logical product of m condition selection circuits to be taken and the n-bit output signal of each condition selection circuit, and further calculates the logical sum of the m outputs obtained by these logical products. It is constituted by having the following.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes an error detection condition memory 1 which has an address specified by an i bit and can read and write each word of n×m bits, and an error comparison condition memory 1. m condition selection circuits 21. which take the logical sum of the output of the output signal and n bits of an input signal (hereinafter referred to as a condition input signal) for detecting the presence or absence of an error. ~． 2m, an error detection condition determination circuit 3 consisting of m AND circuits and one OR circuit, an error flag register 4 that holds the output of the error detection condition circuit 3, and an error detection condition memory l.
The memory address selection circuit 5 selects writing or reading by giving an address to the memory address.

With the above configuration, m×n bits of condition selection write data are written into the error selection condition memory 1 by specifying an address. The n bits of this condition selection write data correspond to the n bits of the condition input signal, and "0" is written to the bits that are desired to be used as error detection conditions, and "1 par" is written to the other bits. Since this set can be made up to m, it is possible to set the error detection condition at m Iff years with one address specification.When a 0 condition input signal is input and an i-bit address signal is given as a condition selection instruction signal, An address is given to the error detection memory 1 via the memory address selection circuit 5, and reading is instructed, m×
8 condition selection circuits 21.n-bit error detection condition data are applied to condition selection circuits 21.about.2m together with condition input signals; ~2m, the output of error detection condition memory 1 is “
The logic of the bit position “1” with the condition input signal is always “1”.
" is excluded from the error detection conditions. On the other hand, the bit position where the readout of the error detection condition memory 1 is "0" becomes the error detection condition.

Condition selection circuit 21. ~． AND-OR logic is performed in the output error detection/determination circuit 3 from 2m and inputted to the error flag register 4.

〔Effect of the invention〕

As explained above, the error detection condition generation circuit of the present invention sets error detection conditions in an error detection condition memory that can be rewritten at any time, and provides a condition selection instruction signal as an address signal to the memory, thereby detecting errors. Since the conditions can be changed dynamically, the error detection conditions can be set as needed without requiring any special man-hours.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...Error detection condition memory, 3...
Error detection determination circuit, 4...Error flag register, 5...Memory address selection circuit, 21.
~, 2m... Condition selection circuit.

Claims (1)

[Claims] An n-bit condition input signal, an error detection condition memory having an n×m bit width and an address specified by i bits, and a write address is selected when writing to this error detection condition memory, and an error is selected when reading. a memory address selection circuit for selecting a condition selection signal; a write data bus for writing error detection condition data into the error detection condition memory; From (j+
1) m condition selection circuits that take the logical sum of the 1st bit to the nth bit of the condition input signal (j = 0 to m-1) and the 1st bit to the nth bit of the condition input signal, and select each condition. 1. An error detection condition generation circuit comprising: an error detection condition determination circuit which takes an AND of n-bit output signals of the circuit and further takes an OR of m outputs obtained by these ANDs.