JPH03241751A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To contrive to suppress a contact resistance between a low-resistance region and ohmic electrode and a sheet resistance between a gate and source by forming the low-resistance region only on the source side in close vicinity in a self-alignment manner to a gate electrode. CONSTITUTION:An anisotropic etching is applied to resist films 14, 17 to remove a sublayer resist 14 on the source side and an ion implantation is conducted on the drain side in a state, where the resist film 14 is left, to form a low- resistance region 18 only on the source side. After that, the anisotropic etching is again applied to the resist film 14 to complete a dummy gate, then the pattern of the dummy gate is reversed by an insulating film, and subsequently a Schottky electrode 20 is formed at the place of the removed dummy gate; source ohmic electrodes 21, 22, on a source low-resistance region 18; and drain ohmic electrodes 21, 22, on a drain side activated layer separately from a gate electrode, respectively. Thus, it is possible to contrive to reduce a source resistance.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to field effect transistors, particularly microwave integrated circuits (MICs) and monolithic microwave integrated circuits (MICs).
The present invention relates to a method of manufacturing a field effect transistor suitable for high-frequency operation, which constitutes an MIC or the like.

[Conventional technology]

Generally, GaAs MMICs and MICs intended for high-frequency operation such as in the microwave band have resistors and active elements such as field effect transistors (MESFET).
It is formed by combining passive elements such as capacitors and inductors.

The operating frequency of the field effect transistor used here is 2 GHz or higher, and the transistor itself is required to be high-speed. Therefore, various efforts have been made to improve fl (current cutoff frequency), which is an indicator of high speed performance. Specifically, in order to improve the transconductance g and reduce the gate capacitance,
In order to make the gate shorter than μm and reduce the source resistance,
By performing ion implantation using the T-shaped dummy gate as a mask, source/drain low resistance regions are formed in a self-aligned manner with respect to the gate electrode.

[Problem to be solved by the invention]

However, if we use a dummy gate to form low resistance regions of the source and drain located symmetrically on both sides of the gate electrode, the low resistance regions on the source side will be self-aligned with the gate electrode. Although this is desirable in terms of reducing the source resistance, at the same time the low resistance region on the drain side is also formed close to the gate electrode, resulting in poor IV saturation characteristics and poor drain conductance. In particular, since the gate-drain breakdown voltage becomes low, it becomes difficult to use it for power applications (high output applications). As mentioned above, in high frequency applications such as microwave bands, it is necessary to shorten the gate length. For power applications that require a withstand voltage of 20 V or more, if the low resistance regions on the source and drain sides are placed close to the gate electrode with a short gate length in a self-aligned manner, a leak path will immediately occur and normal operation will not be possible. cannot be expected.

[Means to solve the problem]

In the method for manufacturing a field effect transistor of the present invention, after forming a lower resist film for a dummy gate and a mask pattern for the dummy gate on an active layer of a semiconductor substrate,
An upper resist film is formed to cover only the drain side from the gate formation region. Next, these resist films are anisotropically etched to remove the lower resist on the source side, and ions are implanted with the resist film left on the drain side to form a low resistance region only on the source side. .

After that, the resist film is anisotropically etched again to complete the dummy gate, and then the pattern of the dummy gate is reversed with an insulating film, and then a shot hole is placed on the dummy gate trace.
A source ohmic electrode is formed on the electrode and the source low resistance region, and a drain ohmic electrode is formed on the drain side active layer at a distance from the gate electrode.

[Effect]

On the source side, a low resistance region is formed in close proximity to the gate electrode in a self-aligned manner, so contact resistance with the ohmic electrode and sheet resistance between the gate and source are suppressed as much as possible. On the other hand, by not forming a low resistance region on the drain side and forming its electrode apart from the gate electrode, the gate-drain breakdown voltage is improved and the drain conductance is improved.

Note that the drain electrode is formed directly on the active layer since there is no low resistance region. As mentioned above, it is essential to reduce the resistance as much as possible on the source side in order to improve the characteristics.
The resistance on the drain side has relatively little effect on the characteristics,
For example, by performing alloying treatment, a practically sufficient ohmic contact can be obtained.

Further, when forming a dummy gate, after forming a mask pattern, the lower resist film is etched using this as a mask, so the dimension of the lower resist film in the gate length direction becomes smaller than the dimension of the mask pattern in the same direction due to undercut.

A gate electrode is formed in a portion where this lower resist film is removed. Therefore, the limit of optical exposure when forming a mask pattern by photolithography (for example, 0.6μ
A gate length shorter than m) is obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 1 is a process sectional view showing an embodiment of the present invention.

Please note that this is a schematic representation and the scale etc. are not accurate.

First, Si ions are implanted into a semi-insulating GaAs substrate 11 using a resist pattern (not shown) formed by ordinary photolithography as a mask. The implantation conditions are, for example, 5×10 12 /cJ and 30 keV, and thereby the active layer (operating layer) 12 is formed. At this time, in order to prevent the short channel effect, Be ions may be deeply implanted using the same resist pattern 13 in addition to Si.

After removing the resist pattern, Si is deposited by P-CVD method.
An N film 13 is formed (FIG. 1(a)).

This SiN film 13 will become a protective film when annealing is later performed to activate the implanted ions, and its thickness is 100 mm.
OA level is sufficient.

A resist is applied on this SiN film 13 to form a lower resist film 14 for forming a dummy gate. The thickness is approximately 1 μm. Subsequently, a mask material, in this case a SiO2 film 15, is deposited on top of it by sputtering, and a resist pattern 16 covering the gate formation region and having openings on both sides is formed on it by ordinary photolithography. Figure (b)).

Next, using the resist pattern 16 as a mask, the S t O2 film 15 is patterned by reactive ion etching (RIE) using a gas such as cF4+H2 (see FIG.
C)).

Next, an upper resist film 17 is formed to cover only the drain side from the gate formation region (FIG. 1(d)). The thickness is approximately 1 μm at the thinner portion.

Here, each resist film is subjected to RIE using 02 gas. This etching is performed on the upper resist film 17 on the drain side.
, and from the exposed surface of the lower resist film 14 on the source side.

Although the SiO2 film 15 acts as a mask for the etching under the film 5, the undercut also removes the lower resist film directly under it in the vicinity of the end face. S on the source side
When all of the lower resist film 14 except under the iO2 film 15 has been removed, Si ions are deeply implanted under the condition of 4×1013/c-1100keV to form the source low resistance region 18.
(Fig. 1(e)). At this time, the drain side is protected by a resist film.

The remaining resist film is subjected to RIE again using 02 gas. On the source side, 15 SiO2 films 5 lower resist films 1
Only 4 undercuts progress. After the upper resist film 17 is removed on the drain side, the lower resist film 14 outside the lower SiO2 film 15 is removed, and the S
Undercutting of the lower resist film 14 under the IO2 film 15 progresses. As a result of the protection provided by the upper resist film 17, the start of undercut on the source side is delayed compared to the drain side, and as a result, the end face of the lower resist film 14 recedes with respect to the end face of the SiO2 film 15 on the drain side. Although it is larger on the source side, the amount of undercut saturates with the etching time as shown in FIG. 2, so there is no fear that the dummy gate will collapse due to too much undercut.

By setting the undercut amount to an appropriate value depending on the etching time, the dimension in the gate length direction of the lower resist film 14 can be adjusted to 5iO7 formed by photolithography.
It can be set to a desired value smaller than the dimension of the membrane 15 in the same direction. After that, an insulating film is formed on the entire surface by sputtering, in this case SiO
2 films are deposited (FIG. 1(f)).

After removing the lower resist film 14 and the lower layer 5 of the SiO2 film 15 thereon by lift-off using a resist remover, annealing is performed to activate the implanted ions.

Thereafter, using conventional photolithography and lift-off methods, a Schottky gate electrode 20 and a source low resistance region 18 are formed on the active layer 12 exposed in the dummy gate trace.
On top of the source ohmic electrode 21 and gate electrode 20
A drain ohmic electrode 2 is placed on the active layer on the opposite side of the source ohmic electrode 21 and separated from the gate electrode 20.
2 (FIG. 1(g)). Gate electrode 2
For example, aluminum (AI) and titanium (Ti
)/platinum (pt)/gold (Au). Also sauce
The drain ohmic electrodes 21 and 22 are made of, for example, a two-layer film of gold/germanium (AuGe)/nickel (Ni).
0 Formed by diffusing germanium into the GaAs substrate 11 by heat treatment after vapor deposition.

[Structure of the invention]

As described above, the present invention reduces source resistance by forming a source low resistance region in a self-aligned manner on the gate electrode.
In addition to improving the transconductance gm and current cutoff frequency f, the use of a T-shaped dummy gate allows the gate length to be made shorter than the limit of optical exposure without providing a low resistance region on the drain side. Forming it away from the electrode has the effect of obtaining a high drain-gate breakdown voltage. Therefore, it is suitable for high frequency, such as microwave band, and high output amplifiers.

Layer resist film, 15.19...SiO2 film, 17...
- Upper resist film, 18...source low resistance region, 20
...Schottky gate electrode, 21.22...source/drain ohmic electrode.

Claims (1)

[Claims] a step of forming an active layer on the surface of a semiconductor substrate, a step of sequentially forming a lower resist film and a mask material layer that can be mutually selectively etched with the resist film thereon, and a step of forming an active layer on the surface of the semiconductor substrate; A process of forming a mask pattern by removing both sides of the gate formation area, leaving the gate formation area; a process of forming an upper resist film that covers only the drain side from the gate formation area; and anisotropic etching of these resist films. a step of removing the lower resist layer of the source formation region by applying ion implantation, a step of performing ion implantation using the mask pattern and the remaining resist film as a mask to form a source low resistance region, and a step of performing anisotropic etching on the resist film. After removing the upper resist film and the lower resist film except under the mask pattern, and forming an insulating film on the entire surface,
A process of removing the remaining lower resist film, forming a Schottky gate electrode on the active layer exposed in the removed portion of the lower resist film in the gate formation region, and forming a source ohmic electrode on the source low resistance region and a source ohmic electrode on the drain side. forming drain ohmic electrodes on the active layer at distances from the gate electrode.