JPH03241750A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to suppress a sheet resistance by forming a low-resistance region in close vicinity to a gate electrode in a self-alignment manner. CONSTITUTION:After a remover used exclusively for OMR is employed to remove a sublayer resist film 14 and SiO2 films 15, 19 on the resist film by a lift-off, annealing is conducted for the purpose of activating implanted ions. After that, normal photolithography and lift-off method are used to form a Schottky gate electrode 20 on an activated layer 12 exposed at the place of a removed dummy gate, a source ohmic electrode 21 on a source low-resistance region 18 and a drain ohmic electrode 22 on the activated layer on the drain side separately from the gate electrode 20, respectively. Thus, it is possible to contrive to reduce a source resistance.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to field effect transistors, particularly microwave integrated circuits (MICs) and monolithic microwave multiplier circuits (M
The present invention relates to a field-effect transistor suitable for high-frequency operation constituting an MIO, etc., and a method for manufacturing the same.

[Conventional technology]

Generally, GaAs MMICs and MICs intended for high-frequency operation such as in the microwave band have resistors and active elements such as field effect transistors (MESFET).
It is formed by combining passive elements such as capacitors and inductors.

The operating frequency of the field effect transistor used here is 2 GHz or higher, and the transistor itself is required to be high-speed. Therefore, various efforts have been made to improve fr (current cutoff frequency), which is an indicator of high speed performance. Specifically, the transconductance g
0.5μ to improve gate capacitance and reduce gate capacitance
In order to make the gate shorter than m and reduce the source resistance, T
By performing ion implantation using the letter-shaped dummy gate as a mask, source/drain low resistance regions are formed in a self-aligned manner with respect to the gate electrode.

[Problem to be solved by the invention]

However, if we use a dummy gate to form low resistance regions of the source and drain located symmetrically on both sides of the gate electrode, the low resistance regions on the source side will be self-aligned with the gate electrode. Although this is desirable in terms of reducing source resistance, at the same time, the low resistance region on the drain side is also formed close to the gate electrode, resulting in poor IV saturation characteristics and poor drain conductance. In particular, since the gate-drain breakdown voltage becomes low, it is difficult to use it as a power (high output) FET. As mentioned above, in high frequency applications such as microwave bands, it is necessary to shorten the cable length. Among power FETs that require a withstand voltage of 20V or more, if the low resistance regions on the source and drain sides are placed close to the gate electrode with a short gate length in a self-aligned manner, a leak bus will immediately occur and normal operation will not be possible. cannot be expected.

[Means to solve the problem]

The field effect transistor of the present invention includes a Schottky gate electrode on an active layer of a semiconductor substrate, a source low resistance region adjacent to the Schottky gate electrode, and a source ohmic electrode disposed above the Schottky gate electrode, with the gate electrode sandwiched between the source ohmic electrode and the source ohmic electrode. A drain ohmic electrode is placed on the active layer on the opposite side.

In addition, in order to obtain such a field effect transistor, the manufacturing method of the present invention involves forming an active layer on the surface of a semiconductor substrate, shaping a lower resist film and a mask pattern, and forming a dummy gate by anisotropic etching. Then, only the drain side from the gate formation region is covered with an upper resist film that can be selectively removed with respect to the lower resist film, and ion implantation is performed in this state to form a low resistance region only on the source side. Next, the upper resist film is removed, and after the pattern of the dummy gate is reversed with an inorganic material film, a Schottky gate electrode and source/drain ohmic electrodes are formed.

[Effect]

On the source side, a low resistance region is formed in close proximity to the gate electrode in a self-aligned manner, so contact resistance with the ohmic electrode and sheet resistance between the gate and source are suppressed as much as possible. On the other hand, by not forming a low resistance region on the drain side and arranging its electrode apart from the gate electrode, the gate-drain breakdown voltage is improved and the drain conductance is improved.

Note that the drain electrode is formed directly on the active layer since there is no low resistance region. As mentioned above, it is essential to reduce the resistance as much as possible on the source side in order to improve the characteristics.
The resistance on the drain side has relatively little effect on the characteristics,
For example, by performing alloying treatment, a practically sufficient ohmic contact can be obtained.

Further, when forming a dummy gate, after forming a mask pattern, the lower resist film is etched using this as a mask, so the dimension of the lower resist film in the gate length direction becomes smaller than the dimension of the mask pattern in the same direction due to undercut.

A gate electrode is formed in a portion where this lower resist film is removed. Therefore, the limit of optical exposure when forming a mask pattern by photolithography (for example, 0.6μ
A gate length shorter than m) is obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1 of the accompanying drawings.

FIG. 1 is a process sectional view showing an embodiment of the present invention.

Please note that this is a schematic representation and the scale etc. are not accurate.

First, S1 ions are implanted into a semi-insulating GaAs substrate 11 using a resist pattern (not shown) formed by ordinary photolithography as a mask. The injection conditions are, for example, 5 x 10'/c + T1230kev
As a result, an active layer (operating layer) 12 is formed.

At this time, in order to prevent the short channel effect, Sl
Besides, Be ions may be deeply implanted using the same resist batten 13. After removing the resist button, P
- Form the SiN film 13 by CVD method (Fig. 1(a)
)). This SiN film 13 will serve as a protective film when annealing is later performed to activate the implanted ions, and its thickness may be about 100 OA.

A resist is applied on this SiN film 13 to form a lower resist film 14 for forming a dummy gate. This resist is made of rubber-based O which is insoluble in acetone.
MR (trade name) is used, and the thickness is about 1 μm. Subsequently, a mask material, here S, is applied on top of it by sputtering.
An iO2 film 15 is deposited, and a resist batten 18 covering the gate formation region and having openings on both sides is formed thereon by ordinary photolithography (see FIG. 1).
C)).

Next, using the resist batten 16 as a mask, the SiO2 film 15 is etched by reactive ion etching (RIE) using CF4CH2 gas, and then the SiO2 film 15 is etched.
Using the O film 15 as a mask, the lower resist film 1 located outside the S 102 film 15 is removed by RIE using 02 gas.
Remove 4. At this time, the lower resist film 14 located outside the lower layer 5 of the SiO2 film 15 is removed. At this time, 5I
Since an undercut also occurs in the lower resist film 14 under the O3 film 15, a T-shaped dummy gate is formed (first
Figure (C)).

Thereafter, an upper resist film 17 is formed to cover only the drain side from the gate formation region. Upper resist film 17
must be able to be selectively removed with respect to the lower resist film 14. Here, AZ4 soluble in acetone
300 (trade name) was used. Also, the thickness is 1 in the thin part.
It is about μm.

In this state, SL ions are deeply implanted under the conditions of 4×10 ”/ad and 100 keV to form a source low resistance region 20 (FIG. 1(d)).

After removing the upper resist film 17 with acetone, an insulating film, here an SiO2 film 19, is formed on the entire surface by sputtering.
(Fig. 1(C)).

After removing the lower resist film 14 and the lower portion 5 of the SiO2 film 15 thereon by lift-off using a special OMR remover, annealing is performed to activate the implanted ions (FIG. 1(f)).

Thereafter, using conventional photolithography and lift-off methods, a Schottky gate electrode 20 and a source low resistance region 18 are formed on the active layer 12 exposed in the dummy gate trace.
A source ohmic electrode 21 is formed on the active layer, and a drain ohmic electrode 22 is formed on the active layer on the drain side at a distance from the gate electrode 20 (FIG. 1(g)). The gate electrode 20 is made of, for example, aluminum (Al) or titanium (Ti)/platinum (Pt)/gold (Au).

The source/drain ohmic electrodes 21 and 22 are formed, for example, by depositing a two-layer film of gold/germanium (AuGe)/nickel (Ni) and then diffusing germanium into the GaAs substrate 11 by heat treatment.

[Structure of the invention]

As described above, the present invention reduces source resistance by forming a source low resistance region close to the gate electrode (in a self-aligned manner), improves transconductance g and current cutoff frequency f, and improves T Even if the gate length is made shorter than the limit of optical exposure by using a character-shaped dummy gate, high drain-gate breakdown voltage can still be achieved by not providing a low resistance region on the drain side and by forming the drain electrode away from the gate electrode. It has the effect of providing Therefore, it is suitable for high frequency, such as microwave band, and high output amplifiers.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention. 11...GaAs substrate, 12...active layer, 14...
・Lower resist film, 15.19...SiO2 film, 17
... Upper resist film, 18... Source low resistance region,
20... Schottky gate electrode, 21.22...
Source/drain ohmic electrode.

Claims (1)

[Claims] 1. A Schottky gate electrode is disposed on an active layer of a semiconductor substrate, and a source low resistance region and a source ohmic electrode are disposed on the active layer region adjacent to the Schottky gate electrode, and the gate electrode is disposed in the active layer region. A field effect transistor in which a drain ohmic electrode is placed on the active layer on the opposite side of the source ohmic electrode, separated from the gate electrode. 2. A step of forming an active layer on the surface of the semiconductor substrate, a step of sequentially forming a lower resist film and a mask material layer that can be mutually selectively etched with this resist film, and a step of forming an active layer on the surface of the semiconductor substrate; On the other hand, there are two steps: a step of forming a mask pattern by removing both sides of the gate formation region, leaving the gate formation region; a step of performing anisotropic etching on the lower resist film to remove the lower resist film other than under the mask pattern; A step of covering only the drain side from the gate formation region with an upper resist film that can be selectively removed from the resist film, and a step of performing ion implantation using these mask patterns and the resist film as a mask to form a source low resistance region. ,
A process of removing the upper resist film, a process of removing the remaining lower resist film after forming an insulating film on the entire surface, and a process of removing the Schottky gate on the active layer exposed in the removed part of the lower resist film in the gate formation area. Along with forming the electrode,
A method for manufacturing a field effect transistor, comprising forming a source ohmic electrode on a source low resistance region and forming a drain ohmic electrode on a drain side active layer at a distance from a gate electrode.