JP3121272B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor using a compound semiconductor and a method for manufacturing the same.
In particular, the present invention relates to a field-effect transistor for a high-speed compound semiconductor IC used for a communication device, a computer, and the like, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to operate a field effect transistor (hereinafter, referred to as "FET") using a compound semiconductor such as GaAs at a high operating frequency, it is necessary to shorten a gate length. In producing an FET having a short gate length, photolithography using UV light is not suitable for forming a gate having a gate length of 0.5 μm or less because its resolution is 0.4 to 0.5 μm. Therefore, photolithography (hereinafter, referred to as “EB lithography”) using an electron beam capable of obtaining higher resolution can be generally used.

[0003] However, EB lithography has problems that the apparatus cost is high and the throughput is low.

For this reason, a method of manufacturing an FET in which a gate is formed using a side wall is disclosed in, for example,
No. 136263, JP-A-61-82482,
JP-A-62-45184, or JP-A-Hei 1-2
No. 51668.

Hereinafter, a method of manufacturing a FET in which a gate is formed using a sidewall in such a conventional technique will be described with reference to FIGS. 8 (a) to 8 (h).

[0006] First, referring to FIG.
A photoresist (not shown) is formed on the substrate. And
By performing selective ion implantation using a photolithography process, an n region 13 is formed near the surface of the substrate 11. n
A part of the region 13 functions as a channel region of a formed FET. Thereafter, an insulating film 14 such as SiN is deposited by CVD or the like so as to cover the substrate 11 including the n region 13.

Next, an etching mask (not shown) made of a resist having a predetermined pattern is formed on the insulator film 14 by using a photolithography process.
Then, using the etching mask, the insulator film 1 is formed.
4 is subjected to anisotropic dry etching such as RIE,
An insulator pattern 15 made of an insulator film as shown in FIG. 8B is formed.

[0008] Next, as shown in FIG.
Then, a film 16 of a material that can form a gate electrode such as WSi (hereinafter, simply referred to as “gate electrode film 16”) is deposited so as to cover the insulator pattern 15.

Next, as shown in FIG. 8D, anisotropic dry etching such as RIE is performed on the gate electrode film 16 without using an etching mask to form an insulator pattern 15.
Then, the gate insulating film 16 other than the side wall is removed. As a result, a side wall 17 made of the gate electrode film 16 is formed on the side wall of the insulator pattern 15.

Next, as shown in FIG. 8E, the insulator pattern 15 is selectively removed to form a sidewall gate 18 made of a gate electrode film 16.

Next, as shown in FIG. 8F, a photoresist 19 having a predetermined pattern is formed on the substrate 11 by a photolithography process. Then, selective ion implantation is performed using the photoresist 19 and the sidewall gate 18 as a mask. Thereby, n ⁺ region 22 having a larger implantation amount and implantation depth than n region 13
To form At this time, by making the sidewall gate 18 function as a mask for ion implantation, the positional relationship between the n region 13 and the n ⁺ region 22 is determined in a self-aligned manner.

Next, after removing the photoresist 19, an insulating film 23 such as SiO ₂ as shown in FIG. 8G is deposited so as to cover the substrate 11 including the sidewall gate 18. Then, the insulating film 23 is replaced with the protective film 23.
While performing the annealing process. Thereby, the ion implantation region is activated to form an active region of the FET.

Next, as shown in FIG. 8H, a source electrode 24 is formed on the n ⁺ region (source / drain region) 22.
And a drain electrode 25 are formed. Thereafter, by forming necessary wirings and the like, the FET is completed.

According to the above manufacturing method, photolithography is not used in the step of forming the side wall gate 18 functioning as a gate electrode, and the gate length is
Is controlled by the thickness of the gate electrode film 16 deposited as a constituent material of the sidewall gate 18 thereon.
Therefore, the resolution of the photolithography process is not related to the setting of the gate length.

[0015]

However, the above-described conventional method of manufacturing an FET in which a gate is formed using a sidewall has the following problems.

First, the FET manufactured by the above method is:
Since it has a one-finger type gate electrode having only one electrode finger, an FET having a multi-finger type or dual gate type gate electrode structure is not manufactured. FE for one finger structure
In order to increase the drain current of T, the width of one electrode finger of the gate electrode must be increased. Therefore, when integrated, the chip size increases.

Second, a step of forming a side wall 17 made of the gate electrode film 16 on the side wall of the insulator pattern 15 by anisotropic dry etching (see FIG. 8D).
In this case, the n region 13 exposed after the gate electrode film 16 is removed by etching may be damaged by dry etching. When the damaged portion constitutes the drain region of the FET to be formed, the breakdown voltage between the gate and the drain may be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide (1) a field effect transistor using a multi-finger type or dual gate type sidewall gate;
(2) To provide a field effect transistor using a sidewall gate having a high gate-drain withstand voltage by reducing etching damage to a drain region of an FET, and (3) an electric field having the above-described features. To provide a method for manufacturing an effect transistor.

[0019]

According to the present invention, there is provided a field effect transformer.
A method of manufacturing a transistor includes a first method of forming an insulator film on a substrate.
And dry etching the insulator film to form a square
A second step of forming an edge pattern, and the insulator pattern;
Forming a gate electrode film on the substrate including the substrate
Etching the gate electrode film anisotropically
Side wall of the gate electrode film on the side wall of the body pattern
And forming a fourth step of forming the insulator pattern.
Both of which are partially removed to form sidewall gates
5) wherein the first step comprises the steps of:
Is a field-effect transistor formed on the substrate.
An active region is formed over the impurity diffusion region to be formed.
The sidewall formed in the fourth step is
One side overlaps the impurity diffusion region and the other three sides
Is located outside the impurity diffusion region, and the fourth step
Select the three sides located outside the impurity diffusion region
Further comprising the step of:
Objective is achieved.

[0020]

[0021]

Preferably, a plurality of ohmic electrodes are formed.
In the sixth step, the sidewall gate is removed
In the first and second positions, respectively
The method further includes a sixth step of forming an ohmic electrode.
You.

Preferably, in the second step, the absolute
The edge pattern is a drain type in the impurity diffusion region.
Formed so as to cover the region to be formed,
A sixth step of forming an ohmic electrode of
The first such as sandwiching the sidewall gate from both sides
Source and drain electrodes at the second and third positions, respectively.
And the drain electrode is formed of the impurity diffusion region.
Formed on the area covered by the insulator pattern
And a sixth step.

Preferably, in the fifth step, the disconnection is performed.
The insulator pattern is selectively removed by removing a part of the edge pattern.
An opening is formed in the nozzle, and the ion
A sixth step of implanting ions and forming a plurality of ohmic electrodes.
A seventh step of forming the side wall gate
In the first and second positions so that the
A first type ohmic electrode and a second type ohmic electrode.
Forming an ohmic electrode, and forming an ohmic electrode of the first type.
Forming a seventh electrode in the opening,
Include.

Preferably, in the second step, the absolute
The edge pattern is a drain type in the impurity diffusion region.
The fifth step is formed so as to cover a region to be a component.
In this step, a part of the insulator pattern is selectively removed to
An opening is formed in the insulator pattern, and the opening is further formed.
A sixth step of implanting ions through
A seventh step of forming a back electrode;
First and second such that the fall gate is sandwiched from both sides
Forming a source electrode and a drain electrode at each position,
And the drain electrode is formed in the opening.
And b.

According to another aspect of the invention, a field effect transformer is provided.
The transistor is placed on the substrate containing the impurity diffusion
Formed in a closed pattern along the four sides of the area
Gate wiring, at least a part of the gate wiring
Is a gate wiring, which functions as a gate electrode, and the impurity
The closed pattern of the gate wiring on the diffusion region
The first ohmic electrode formed at a position corresponding to the inside of the
A pole and the gate wiring on the impurity diffusion region.
The second formed at a position located outside the closed pattern
And the impurity diffusion region is T-shaped.
And the second ohmic electrode is
No. 2 located on both sides of the closed pattern of the
Connecting the first and second positions and the first and second positions.
At a third position located in a direction orthogonal to the
That achieves the above objectives.
You.

According to another aspect of the invention, a field effect transformer is provided.
The transistor is placed on the substrate containing the impurity diffusion
Formed in a closed pattern along the four sides of the area
Gate wiring, at least a part of the gate wiring
Is a gate wiring, which functions as a gate electrode, and the impurity
The closed pattern of the gate wiring on the diffusion region
The first ohmic electrode formed at a position corresponding to the inside of the
A pole and the gate wiring on the impurity diffusion region.
The second formed at a position located outside the closed pattern
Ohmic electrode, and the impurity diffusion region has a cross shape.
And the second ohmic electrode is
No. 2 located on both sides of the closed pattern of the
Connecting the first and second positions and the first and second positions.
Third and fourth positions located in a direction perpendicular to the direction of movement
Each of which has the above purpose.
Is achieved.

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

The operation will be described below.

In the method of manufacturing a field-effect transistor according to the present invention, a sidewall made of a gate electrode film is formed around a rectangular insulator pattern made of an insulator film formed on a substrate. Therefore, by removing the insulator pattern, a side wall gate formed of the gate electrode film and having a pattern along the periphery of the rectangular region is formed. This sidewall gate is a gate wiring,
Further, at least a part thereof functions as a gate electrode.

Furthermore, by selectively removing portions of the sidewalls formed along the two opposite sides of the insulator pattern, the two gate electrode films having the same gate length and gate width can be obtained. A dual gate type sidewall gate is formed.

In the impurity diffusion region where the active region of the field effect transistor is to be formed on the substrate,
In particular, when an insulator pattern is formed so as to cover a region where a drain is to be formed, a drain formation region can be protected from damage due to etching in a step of forming a sidewall made of a gate electrode film by anisotropic etching. .

If an opening is formed by selectively removing a part of the insulator pattern, the insulator pattern can be left so as to be in contact with the inside of the sidewall gate. Thereby, the strength of the sidewall gate with respect to a force in a direction parallel to the surface of the substrate and the adhesion between the substrate and the sidewall gate can be increased.

In the field effect transistor of the present invention, a structure in which two opposing fine gate electrodes having the same length are connected can be formed. Thus, a field effect transistor having a multi-finger type fine gate electrode having two to four electrode fingers is formed. Specifically, a gate wiring at least part of which functions as a gate electrode is formed so as to form a pattern along at least three sides of the rectangular region. Then, a first ohmic electrode (preferably a drain electrode) is formed at a position corresponding to the inside of the gate wiring pattern, and a plurality of second ohmic electrodes (preferably at a position corresponding to the outside of the gate wiring pattern). Is a source electrode). Accordingly, depending on the position and the number of the second ohmic electrodes to be formed, a two-finger type having two to four electrode fingers, a three-finger type,
Alternatively, a four-finger type FET having a fine gate electrode is formed.

By providing an insulator so as to be in contact with the inside of the pattern of the gate wiring (gate electrode), the strength of the sidewall gate with respect to the force in the direction parallel to the surface of the substrate and the strength between the substrate and the sidewall gate can be improved. Adhesion can be increased.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIGS. 1 (a) to 1 (l)
FIGS. 4A and 4B are a cross-sectional view and a plan view illustrating each step of the method for manufacturing the FET 100 according to the first embodiment of the present invention. FIGS. Specifically, in each drawing other than FIGS. 1A and 1C, a cross-sectional view is shown on the left side of the drawing and a plan view is shown on the right side. On the other hand, FIGS. 1A and 1C show only cross-sectional views.

First, as shown in FIG. 1A, an accelerating voltage of about 180 keV and a dose of about 2.times. Are applied to a semi-insulating GaAs substrate 11 using a suitably patterned photoresist (not shown) as a mask. Mg at 0 × 10 ¹² cm ^-2
Ions are implanted to form p regions 12. Thereafter, an acceleration voltage of about 20 keV and a dose of about 2.0 × 10 ¹³ cm ⁻²
Implants Si ions into the p region 12 and n
A region 13 is formed. A part of the n region 13 functions as a channel region of the FET 100 to be formed. Next, an SiN film 14 having a thickness of about 400 nm is formed as an insulator film so as to cover the surface of the substrate 11 including the channel region 13.
Is deposited.

Next, as shown in FIG. 1B, after a resist pattern (not shown) having an appropriate shape is formed on the SiN film 14, the resist pattern is used as an etching mask to form a dry pattern using RIE. Etching and S
The iN film 14 is etched to form a square SiN pattern 1
5 is formed.

Next, as shown in FIG. 1C, a thickness of about 200 n to function as the gate electrode film 16 so as to cover the surface of the substrate 11 including the SiN pattern 15.
A mSi film 16 is deposited.

Next, as shown in FIG. 1D, the WSi film 16 is dry-etched by RIE without using an etching mask to remove the WSi film 16 at locations other than the side wall of the SiN pattern 15. . Thereby, Si
A sidewall 17 made of WSi is formed on the sidewall of the N pattern 15. At this time, the sidewall 17
Are formed along the four sides of the SiN pattern 15 so as to surround the periphery thereof.

Next, as shown in FIG. 1E, the SiN pattern 15 is removed using hydrofluoric acid. by this,
A sidewall gate 18 (hereinafter, also referred to as a “square pattern sidewall gate”) arranged to surround the periphery of a certain rectangular region is formed.

Next, as shown in FIG.
A photoresist 19 having an appropriate pattern is formed thereon, and using this as a mask, Si ions are implanted at an acceleration voltage of about 30 keV and a dose of about 3.0 × 10 ¹² cm ⁻² ,
An n ′ region 20 is formed.

Next, after removing the resist 19, FIG.
As shown in (g), an SiO ₂ film (through film) 21 is formed on the surfaces of the substrate 11 and the n ′ region 20. Furthermore, S
After a new resist 19 'having an appropriate pattern is formed on the iO ₂ film (through film) 21, the through film ₂ is formed using the sidewall gate 18 and the resist 19' as a mask.
1, the acceleration voltage is about 150 keV, and the dose is about 5.0.
Si ions are implanted at × 10 ¹³ cm ⁻² to form an n ⁺ region 22.

Next, after removing the resist 19 ′ and the SiO ₂ film (through film) 21, as shown in FIG. 1H, an SiO ₂ film (protective film) having a thickness of about 100 nm is formed on the surface of the substrate 11. 23 is deposited. After that, a temperature of about 8
Annealing is performed at 00 ° C. for about 15 minutes to activate the ion implantation region.

Next, as shown in FIG. 1I, an opening is provided in the SiO ₂ film 23 at a predetermined position on the n ⁺ region 22, and an AuGe layer / Ni layer / Au layer is formed there. Ohmic electrodes (source / drain electrodes) 24 and 25 having a structure are formed. In the configuration of FIG. 1 (i), preferably,
N ⁺ region 2 surrounded by sidewall gate 18
2 functions as a drain electrode 25, and the n ⁺ of the portion outside the sidewall gate 18 is formed.
The electrode 24 formed on the region 22 functions as the source electrode 24. Alternatively, the positional relationship between the drain electrode and the source electrode may be reversed.

Next, as shown in FIG. 1J, an SiO ₂ film (first interlayer film) 26 covering the sidewall gate 18 and the electrodes 24 and 25 is deposited. Further, the SiO ₂ film 2
After a resist (not shown) is formed on the surface of No. 6, baking is performed at a temperature of about 180 ° C. for about 5 minutes to flatten the surface of the formed resist. Next, dry etching using RIE is performed to form the sidewall gate 1.
The resist and the SiO ₂ film (first interlayer film) 26 are etched back until the surface of No. 8 is exposed.

Next, openings are formed in the first interlayer film 26 at locations corresponding to the electrodes 24 and 25, respectively. Then, as shown in FIG.
A two-layer structure of a Ti layer and an Au metal layer having a thickness of about 300 nm and about 300 nm is formed in a predetermined pattern by evaporation and lift-off.
It is formed on the interlayer film 26. Here, the electrodes 24 and 25
The above-described two-layer structure formed at a position corresponding to each of the electrodes contacts the electrodes 24 and 25 through the opening, and
It functions as the layer wiring 28. Further, the above-described two-layer structure corresponding to a portion on the sidewall gate 18 functions as the gate low-resistance metal layer 27.

Next, as shown in FIG. 1L, a SiN film (second interlayer film) 29 covering the gate low resistance metal layer 27 and the first layer wiring 28 is deposited. Thereafter, the SiN film 2 corresponding to the upper part of the first layer wiring 28 is dry-etched.
In 9, an opening for providing an inter-wiring contact is formed. Finally, a second layer wiring 30 made of a Ti / Au metal layer
And 31 are formed by plating so as to be in contact with the first layer wiring 28 through the opening. Thus, the FET 100 according to the present embodiment is completed.

In the FET 100, the gate low-resistance metal layer 27 at the same level as the first layer wiring functions as a lead wiring from the sidewall gate (gate electrode) 18. On the other hand, the second layer wirings 30 and 31 function as lead wirings from the source / drain electrodes 24 and 25. The low-resistance metal layer 27 corresponding to the wiring extending from the gate and the second-layer wirings 30 and 31 which are wirings extending from the source and drain electrodes 24 and 25 are formed at different levels via an interlayer insulating film. ing.

In the embodiment described above, FIG.
As shown in (d), a sidewall gate 18 is formed around a rectangular SiN pattern 15 formed so as to cross the n region 13. Then, as shown in FIG. 1I, an ohmic electrode (preferably, a drain electrode) 2 is formed in a portion surrounded by the sidewall gate 18.
5 are provided, and other ohmic electrodes (preferably source electrodes) 24 are provided outside the sidewall gate 18 and at positions sandwiching the electrode 25 from both sides. Thus, the FET 100 having the multi-finger type gate electrode can be easily manufactured using the sidewall gate.

Further, according to the conventional technique, the gate length is set to 0.
If a fine gate electrode having a size of 5 μm or less is formed, the gate electrode may be peeled off in a subsequent process. However, in the method of the present embodiment described above,
Since the sidewall gate 18 is provided so as to form a square closed pattern, the gate length is 0.5
Even with a fine gate of μm or less, the strength of the sidewall gate 18 against a force parallel to the surface of the substrate 11 is increased. As a result, the adhesion between the substrate 11 and the sidewall gate 18 is improved.

The sidewall gates need not always be formed in a closed pattern. The above-mentioned increase in strength can be brought about if it is formed along the periphery of the rectangular region so as to surround at least three sides thereof.

Further, by making the portion of the n ⁺ region 22 surrounded by the sidewall gate 18 function as a drain region, in the step of forming the sidewall gate 18 by dry etching shown in FIG. A portion to be a drain region can be protected from plasma damage. As a result, the breakdown voltage between the gate and the drain can be kept high.

(Second Embodiment) FIGS. 2A to 2L
FIGS. 7A and 7B are a cross-sectional view and a plan view illustrating each step of a method for manufacturing the FET 200 according to the second embodiment of the present invention. FIGS. Specifically, FIGS. 2 (b), (d), (e),
In each of (i), (k) and (l), a cross-sectional view is shown on the left side of the figure and a plan view is shown on the right side. On the other hand, in each of the other drawings, only a cross-sectional view is shown. In these figures, the same components as those in the configuration of the first embodiment shown in FIGS. 1A to 1L are denoted by the same reference numerals.

In this embodiment, first, in the step shown in FIG. 2A, the p region 1 is formed in the substrate 11 under the same ion implantation conditions as those shown in FIG. 1A in the first embodiment.
2 and n regions 13 are formed. However, at this time, by adjusting the shape of the resist pattern, the n region 13 and the p region 1 are adjusted.
2 is formed in a T-shape. Thereafter, the formed n region 1
As in the first embodiment, an SiN film 14 is formed so as to cover the surface of the substrate 11 including 3.

In the steps shown in FIGS. 2 (c) to 2 (l), the first
By performing the same steps as those described with reference to FIGS. 1C to 1L in the embodiment, the FET 200 is completed. A detailed description of the overlapping steps will be omitted here.

In the embodiment described above, FIG.
As shown in (d), a sidewall gate 18 is formed around the rectangular SiN pattern 15. Then, as shown in FIG.
An ohmic electrode (preferably a drain electrode) 25 is provided in a portion surrounded by 8, and another ohmic electrode (preferably a source electrode) is provided outside the sidewall gate 18 and at a position corresponding to each tip of the T-shape. 24 are provided. Thus, the FET 200 having the multi-finger type gate electrode can be easily manufactured using the sidewall gate.

The structure of the FET 200 formed in this embodiment is the same as that of the FET 100 according to the first embodiment described above.
And the same effect can be exerted. Further, in the present embodiment, the n region 13 and the p region 1
By arranging the two in a T-shape, three of the four sides of the sidewall gate 18 formed in a square shape are actually used as gate electrodes. Thus, as in the FET 100 of the first embodiment, the sidewall gate 18
The gate width can be substantially increased as compared with the case where only two opposing sides of the four sides are actually used as gate electrodes. As a result, there is an advantage that a larger drain current can be obtained.

(Third Embodiment) FIGS. 3 (a) to 3 (l)
FIGS. 9A and 9B are a cross-sectional view and a plan view illustrating each step of a method for manufacturing the FET 300 according to the third embodiment of the present invention. FIGS. Specifically, FIGS. 3 (b), (d), (e),
In each of (i), (k) and (l), a cross-sectional view is shown on the left side of the figure and a plan view is shown on the right side. On the other hand, in each of the other drawings, only a cross-sectional view is shown. In these figures, the same components as those in the configuration of the first embodiment shown in FIGS. 1A to 1L are denoted by the same reference numerals.

In this embodiment, first, in the step shown in FIG. 3A, the p region 1 is formed in the substrate 11 under the same ion implantation conditions as the step shown in FIG. 1A in the first embodiment.
2 and n regions 13 are formed. However, at this time, by adjusting the shape of the resist pattern, the n region 13 and the p region 1 are adjusted.
2 is formed in a cross shape. Thereafter, the formed n region 1
As in the first embodiment, an SiN film 14 is formed so as to cover the surface of the substrate 11 including 3.

In the steps shown in FIGS. 3C to 3L, the first
By performing the same steps as those described with reference to FIGS. 1C to 1L in the embodiment, the FET 300 is completed. A detailed description of the overlapping steps will be omitted here.

In the embodiment described above, FIG.
As shown in (d), a sidewall gate 18 is formed around the rectangular SiN pattern 15. Then, as shown in FIG.
An ohmic electrode (preferably a drain electrode) 25 is provided in a portion surrounded by 8, and another ohmic electrode (preferably a source electrode) 24 is provided outside the sidewall gate 18 and at a position corresponding to each tip of the cross. Is provided. Thus, the FET 300 having the multi-finger type gate electrode can be easily manufactured using the sidewall gate.

The structure of the FET 300 formed in this embodiment is the same as that of the FET 100 according to the first embodiment described above.
And the same effect can be exerted. Further, in the present embodiment, the n region 13 and the p region 1
By arranging 2 in a cross shape, all four sides of the sidewall gate 18 formed in a square shape are actually used as gate electrodes. Thus, as in the FET 100 of the first embodiment, the four side gates 18
The gate width can be substantially increased as compared with the case where only two opposing sides of the sides are actually used as gate electrodes. As a result, there is an advantage that a larger drain current can be obtained.

(Fourth Embodiment) FIGS. 4A to 4N
FIGS. 9A and 9B are a cross-sectional view and a plan view illustrating each step of a method for manufacturing an FET 400 according to a fourth embodiment of the present invention. FIGS. Specifically, FIGS. 4A and 4C show only cross-sectional views, and FIGS. 4E and 4F show only plan views. In each of the other figures, a cross-sectional view is shown on the left side of the figure, and a plan view is shown on the right side. In these figures, FIG.
The same components as those in the configuration of the first embodiment shown in (a) to (l) are denoted by the same reference numerals.

First, as the steps shown in FIGS. 4A to 4D, the same steps as those described with reference to FIGS. 1A to 1D in the first embodiment are performed.

Next, as shown in FIG.
3 is formed. However, here, the resist mask 19 is formed so as not to cover the two sides 17a and 17b of the side wall 17 which are located outside the n region 13 and face each other.

Next, as shown in FIG. 4F, two opposite sides 17a and 17b of the side wall 17 are selectively removed by dry etching using a resist mask 19, and the resist mask 19 is further removed. Thus, a sidewall gate 18 is formed. Here, the side wall gates 18 in the present embodiment are two parallel gates.
It has a dual gate type structure composed of two gate electrodes.

Thereafter, in the steps shown in FIGS. 4G to 4N, the same steps as those described with reference to FIGS. 1E to 1L in the first embodiment are performed. And FET40
Complete 0. A detailed description of the overlapping steps will be omitted here.

In the present embodiment, the opposing two sides 17a and 17b located outside the n region 13 in the side wall 17 are selectively removed. As a result, a sidewall gate 18 having a dual-gate type structure including two gate electrodes having the same gate length and gate width and being parallel to each other is formed. Then, FIG. 4 (k)
As shown in FIG. 7, ohmic electrodes 24 and 25 functioning as source / drain electrodes are formed so as to sandwich the formed dual-type sidewall gate 18 from both sides. Thereby, the dual gate type FET 400 including two sidewall gates is easily manufactured.

(Fifth Embodiment) FIGS. 5A to 5N
FIGS. 21A and 21B are a cross-sectional view and a plan view illustrating each step of a method for manufacturing the FET 500 according to the fifth embodiment of the present invention. FIGS. Specifically, FIGS. 5A and 5C show only cross-sectional views, and FIGS. 5E and 5F show only plan views. In each of the other figures, a cross-sectional view is shown on the left side of the figure, and a plan view is shown on the right side. In these figures, FIG.
The same components as those in the configuration of the fourth embodiment shown in (a) to (n) are denoted by the same reference numerals.

In this embodiment, first, in the step shown in FIG. 5A, the p region 1 is formed in the substrate 11 under the same ion implantation conditions as those shown in FIG. 1A in the first embodiment.
2 and n regions 13 are formed. Thereafter, the formed n
As in the first embodiment, an SiN film 14 is formed so as to cover the surface of the substrate 11 including the region 13.

Next, as shown in FIG. 5B, after a resist pattern (not shown) having an appropriate shape is formed on the SiN film 14, dry etching using RIE is performed using the resist pattern as an etching mask. Go to Si
The N film 14 is etched to form a square SiN pattern 15.
To form At this time, in the present embodiment, SiN
The pattern 15 is formed so as to be located on one side of the n region 13.

Next, as shown in FIG. 5C, a thickness of about 200 n to function as the gate electrode film 16 so as to cover the surface of the substrate 11 including the SiN pattern 15.
A mSi film 16 is deposited.

Next, as shown in FIG. 5D, the WSi film 16 is dry-etched by RIE without using an etching mask to remove the WSi film 16 at locations other than the side wall of the SiN pattern 15. . This gives S
A sidewall 17 made of WSi is formed on the sidewall of the iN pattern 15. At this time, the sidewall 17
Are formed along the four sides of the rectangular SiN pattern 15 so as to surround the periphery thereof.

Next, as shown in FIG.
3 is formed. However, here, the resist mask 19 is formed so as not to cover the three sides 17a, 17b, and 17c outside the n-region 13 in the sidewall 17.

Next, as shown in FIG. 5F, by dry etching using the resist mask 19, three sides 17a, 17b and 17c of the side wall 17 which are not covered by the resist mask 19 are selected. Removed. Thereafter, in the steps shown in FIGS. 5 (g) to 5 (n),
By performing the same steps as those described with reference to FIGS. 1E to 1L in the first embodiment, the FET 500 is completed. A detailed description of the overlapping steps will be omitted here. In the present embodiment, as shown in FIG. 5K, the source electrode 24 and the drain electrode 25 are formed so as to sandwich the formed sidewall gate 18 from both sides.

In this embodiment, in the n ⁺ region 22, Si
If the portion covered with the N pattern 15 is made to function as a drain region, a portion to be a drain region is protected from plasma damage in the step of forming the sidewall gate 18 by dry etching shown in FIG. can do. As a result, the breakdown voltage between the gate and the drain can be kept high.

(Sixth Embodiment) FIGS. 6A to 6K
FIGS. 21A and 21B are a cross-sectional view and a plan view illustrating each step of a method for manufacturing the FET 600 according to the sixth embodiment of the present invention. FIGS. Specifically, FIGS. 6A and 6C show only cross-sectional views, and in each of the other drawings, a cross-sectional view is shown on the left side of the figure.
A plan view is shown on the right side. In these drawings, the same components as those of the embodiments described above include:
The same reference numbers are given.

First, as the steps shown in FIGS. 6A to 6D, the same steps as those described with reference to FIGS. 1A to 1D in the first embodiment are performed.

Next, as shown in FIG. 6E, wet etching is performed using a resist (not shown) having a predetermined pattern as an etching mask, and the side wall 1 is etched.
An opening 32 is formed by selectively removing a part of the SiN pattern 15 surrounded by 7. After that, the n ′ region 20 is formed under the same ion implantation conditions as in the step shown in FIG. 1F in the first embodiment. Then, FIG.
In the steps shown in (f) to (k), the same steps as those described with reference to FIGS. 1 (g) to 1 (l) in the first embodiment are performed to complete the FET 600. In addition,
A detailed description of the overlapping steps will be omitted here. In this embodiment, as shown in FIG. 1H, an ohmic electrode (preferably, a drain electrode) 25 is provided in a portion surrounded by the sidewall gate 18, and the electrode 25 is provided outside the sidewall gate 18 and on both sides. Each other ohmic electrode (preferably, a source electrode) 24 is provided at a position sandwiched between them.

The structure of the FET 600 formed in this embodiment is the same as that of the FET 100 according to the first embodiment described above.
And the same effect can be exerted. Further, in the present embodiment, S is in contact with the inside of the side wall gate 18 formed along the periphery of the rectangular region.
Since the iN pattern 15 exists, the strength of the sidewall gate 18 against a force parallel to the surface of the substrate 11 can be further increased. As a result, the adhesion between the substrate 11 and the sidewall gate 18 is further improved.

(Seventh Embodiment) FIGS. 7A to 7N
FIGS. 21A and 21B are a cross-sectional view and a plan view illustrating each step of a method for manufacturing the FET 700 according to the seventh embodiment of the present invention. FIGS. Specifically, FIGS. 7A and 7C show only cross-sectional views, and in each of the other drawings, a cross-sectional view is shown on the left side of the drawing.
A plan view is shown on the right side. In these drawings, the same components as those of the embodiments described above include:
The same reference numbers are given.

First, as the steps shown in FIGS. 7A to 7F, the same steps as those described with reference to FIGS. 5A to 5F in the fifth embodiment are performed.

Next, as shown in FIG. 7G, wet etching is performed using a resist (not shown) having a predetermined pattern as an etching mask, and
An opening 32 is formed by selectively removing a part of the SiN pattern 15 surrounded by 7. Then, FIG.
In the steps shown in (h) to (n), the same steps as those described with reference to FIGS. 5 (h) to (n) in the fifth embodiment are performed to complete the FET 700. A detailed description of the overlapping steps will be omitted here. In the present embodiment, as shown in FIG. 7K, ohmic electrodes 24 and 25 functioning as source / drain electrodes are formed so as to sandwich the formed sidewall gate 18 from both sides.

The structure of the FET 700 formed in this embodiment is the same as that of the FET 500 according to the fifth embodiment described above.
And the same effect can be exerted. Further, in the present embodiment, the side wall gate 1
8 has an SiN pattern 15 in contact with one side thereof.
The strength of the sidewall gate 18 against a force parallel to the surface of the substrate 11 can be further increased. As a result, the adhesion between the substrate 11 and the sidewall gate 18 is further improved.

[0100]

As described above, in the method of manufacturing a field-effect transistor according to the present invention, a sidewall made of a gate electrode film is formed around a rectangular insulator pattern made of an insulator film formed on a substrate. It is formed. Therefore, by removing the insulator pattern, a side wall gate formed of the gate electrode film and having a pattern along the periphery of the rectangular region is formed. The sidewall gate is a gate wiring, and at least a part thereof functions as a gate wiring. Here, since the sidewall gate is formed along the periphery of the rectangular region, a field-effect transistor having high adhesion to the substrate is manufactured even with a fine gate having a gate length of about 0.5 μm or less. be able to. The above effect can be exerted if the sidewall gate (gate wiring) is formed along at least three sides around the rectangular region.

Furthermore, by selectively removing portions of the sidewalls formed along the two opposing sides of the insulator pattern, the two gate electrode films having the same gate length and gate width can be obtained. A dual gate type sidewall gate is formed.

Also, of the impurity diffusion regions where the active region of the field effect transistor is to be formed on the substrate,
In particular, when an insulator pattern is formed so as to cover a region where a drain is to be formed, a drain formation region can be protected from damage due to etching in a step of forming a sidewall made of a gate electrode film by anisotropic etching. . As a result, a field effect transistor having a sufficiently high withstand voltage level between the gate and the drain can be easily manufactured.

If an opening is formed by selectively removing a part of the insulator pattern, the pattern made of the insulator is left so as to be in contact with the inside of the sidewall gate of the pattern along the periphery of the rectangular region. be able to. Thereby, even if the sidewall gate has a minute gate length (for example, about 0.5 μm or less), the strength of the sidewall gate against a force in a direction parallel to the surface of the substrate,
The adhesion between the substrate and the sidewall gate can be increased.

In the field effect transistor of the present invention, a structure in which two opposing fine gate electrodes having the same length are connected can be formed. Thus, a field effect transistor having a multi-finger type fine gate electrode having two to four electrode fingers is formed. Specifically, a gate wiring at least part of which functions as a gate electrode is formed so as to form a pattern along at least three sides of the rectangular region. Then, a first ohmic electrode (preferably a drain electrode) is formed at a position corresponding to the inside of the gate wiring pattern, and a plurality of second ohmic electrodes (preferably at a position corresponding to the outside of the gate wiring pattern). Is a gate electrode). Accordingly, depending on the position and the number of the second ohmic electrodes to be formed, a two-finger type having two to four electrode fingers, a three-finger type,
Alternatively, a four-finger type FET having a fine gate electrode is formed. At this time, since the gate wiring (gate electrode) is formed so as to form a pattern along the periphery of the rectangular region, even a fine sidewall gate having a short gate length can be formed in a direction parallel to the surface of the substrate. The strength of the sidewall gate with respect to the force and the adhesion between the substrate and the sidewall gate can be increased.

[Brief description of the drawings]

FIGS. 1A to 1L are diagrams for explaining a manufacturing process of a field-effect transistor according to a first embodiment of the present invention.

FIGS. 2A to 2L are diagrams for explaining a manufacturing process of a field-effect transistor according to a second embodiment of the present invention.

FIGS. 3A to 3L are diagrams for explaining a manufacturing process of a field-effect transistor according to a third embodiment of the present invention.

FIGS. 4A to 4N are views for explaining a manufacturing process of a field-effect transistor according to a fourth embodiment of the present invention.

FIGS. 5A to 5N are views for explaining a manufacturing process of a field-effect transistor according to a fifth embodiment of the present invention.

FIGS. 6A to 6K are diagrams for explaining a manufacturing process of a field-effect transistor according to a sixth embodiment of the present invention.

FIGS. 7A to 7N are views for explaining a manufacturing process of a field-effect transistor according to a seventh embodiment of the present invention.

FIGS. 8A to 8H are views for explaining a manufacturing process of a field-effect transistor according to the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Substrate 12 p region 13 n region 14 Insulator film 15 Insulator pattern 16 Gate electrode film 17 Side wall 18 Side wall gate 19, 19 ′ Resist mask 20 n ′ region 21 Through film 22 n ⁺ region 23 Protective film 24, 25 Ohmic electrode (source / drain electrode) 26 First interlayer film 27 Gate low resistance metal layer 28 First layer wire 29 Second interlayer film 30, 31 Second layer wire (source / drain lead wire) 32 Opening

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-161774 (JP, A) JP-A-3-196532 (JP, A) JP-A-60-46074 (JP, A) JP-A-59-1984 34666 (JP, A) JP-A-61-82482 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 29/778 H01L 29/80-29/812

Claims (7)

(57) [Claims] A first step of forming an insulator film on a substrate; a second step of dry-etching the insulator film to form a square insulator pattern; A third step of forming a gate electrode film on the substrate; and a fourth step of anisotropically etching the gate electrode film to form a sidewall of the gate electrode film on a side wall portion of the insulator pattern. And a fifth step of removing at least a part of the insulator pattern to form a sidewall gate. In the first step, the insulator film is formed on the substrate. Forming the active region of the field effect transistor on the impurity diffusion region to be formed, the sidewall formed in the fourth step has one side overlapping the impurity diffusion region, The side of the impurity diffusion region The method for manufacturing a field effect transistor, wherein the fourth step is located outside, and the fourth step further includes a step of selectively removing the three sides located outside the impurity diffusion region. 2. A sixth step of forming a plurality of ohmic electrodes, further comprising the step of forming ohmic electrodes at first and second positions sandwiching the sidewall gate from both sides. Claim 1
3. The method for manufacturing a field-effect transistor according to item 1. 3. In the second step, the insulator pattern is formed so as to cover a region of the impurity diffusion region that is to be a drain formation portion, and further a sixth step of forming a plurality of ohmic electrodes. And
A source electrode and a drain electrode are respectively formed at first and second positions sandwiching the sidewall gate from both sides, and the drain electrode is a region of the impurity diffusion region covered with the insulator pattern. The method for manufacturing a field-effect transistor according to claim 1 , further comprising a sixth step formed on the substrate. The method according to claim 4, wherein the fifth step, the opening in the insulator pattern portion is selectively removed to the insulating pattern is formed, further, the sixth to perform ion implantation through the opening And a seventh step of forming a plurality of ohmic electrodes,
A first type ohmic electrode and a second type ohmic electrode are respectively formed at first and second positions sandwiching the sidewall gate from both sides, and the first type ohmic electrode is formed at the opening. The method of manufacturing a field-effect transistor according to claim 1 , comprising: a seventh step formed in the portion. 5. The method according to claim 5, wherein in the second step, the insulator pattern is formed so as to cover a region of the impurity diffusion region that is to be a drain formation location. An opening is formed in the insulator pattern by selectively removing the portion, a sixth step of performing ion implantation through the opening, and a seventh step of forming a plurality of ohmic electrodes,
A seventh step of forming a source electrode and a drain electrode respectively at first and second positions sandwiching the sidewall gate from both sides, and the drain electrode is formed in the opening; The method for manufacturing a field effect transistor according to claim 1 , wherein the method includes: 6. A gate wiring formed on a substrate including an impurity diffusion region so as to form a closed pattern along four sides of a rectangular region, wherein at least a part of the gate wiring functions as a gate electrode. A first ohmic electrode formed on the impurity diffusion region at a position corresponding to the inside of the closed pattern of the gate wiring, and a first ohmic electrode on the impurity diffusion region, A second ohmic electrode formed outside the closed pattern of the gate wiring, wherein the impurity diffusion region is formed in a T shape, and the second ohmic electrode is First and second positions located on both sides of the gate wiring with the closed pattern therebetween, and third positions located in a direction orthogonal to a direction connecting the first and second positions, respectively. And Field effect transistor. 7. A gate wiring formed on a substrate including an impurity diffusion region so as to form a closed pattern along four sides of a rectangular region, wherein at least a part of the gate wiring functions as a gate electrode. A first ohmic electrode formed on the impurity diffusion region at a position corresponding to the inside of the closed pattern of the gate wiring, and a first ohmic electrode on the impurity diffusion region, A second ohmic electrode formed outside the closed pattern of the gate line, wherein the impurity diffusion region is formed in a cross shape, and the second ohmic electrode is At first and second positions located on both sides of the wiring with the closed pattern interposed therebetween, and at third and fourth positions located in a direction orthogonal to the direction connecting the first and second positions, respectively. Formation Are field-effect transistors.