JPH0323482U - - Google Patents
Info
- Publication number
- JPH0323482U JPH0323482U JP1989082595U JP8259589U JPH0323482U JP H0323482 U JPH0323482 U JP H0323482U JP 1989082595 U JP1989082595 U JP 1989082595U JP 8259589 U JP8259589 U JP 8259589U JP H0323482 U JPH0323482 U JP H0323482U
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- common electrode
- joined
- stacked
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Credit Cards Or The Like (AREA)
Description
第１図は本考案の一実施例におけるＩＣメモリ
カードの一部を切欠いた斜視図、第２図はその部
分断面図、第３図は同じく電気回路のブロツク図
、第４図は同じく積層状態を示す斜視図、第５図
は従来のＩＣメモリカードにおける部分断面図で
ある。
２……プリント配線板、６……メモリＬＳＩチ
ツプ、１０……電極（共通）、１２……導体リー
ド、１２ａ……導体リードの一端部、１２ｂ……
導体リードの他端部、１３……電極（非共通）、
１５……導体リード、１５ａ……導体リードの一
端部、１５ｂ，１５ｃ，１５ｄ……導体リードの
他端部、１６，１７，１８，１９，２２，２３…
…導体配線、Ｌ，Ｓ……導体配線の配列間隔。
Fig. 1 is a partially cutaway perspective view of an IC memory card according to an embodiment of the present invention, Fig. 2 is a partial sectional view thereof, Fig. 3 is a block diagram of an electric circuit, and Fig. 4 is a laminated state. FIG. 5 is a partial cross-sectional view of a conventional IC memory card. 2... Printed wiring board, 6... Memory LSI chip, 10... Electrode (common), 12... Conductor lead, 12a... One end of the conductor lead, 12b...
The other end of the conductor lead, 13...electrode (uncommon),
15...Conductor lead, 15a...One end of the conductor lead, 15b, 15c, 15d...Other end of the conductor lead, 16, 17, 18, 19, 22, 23...
...Conductor wiring, L, S... Arrangement interval of conductor wiring.
Claims (1)
積層され、前記各メモリＬＳＩチツプの電極には
導体リードの一端部が接合され、前記メモリＬＳ
Ｉチツプの共通電極に接合された前記導体リード
の他端部は、重ね合わされて前記プリント配線板
の導体配線に接合され、前記メモリＬＳＩチツプ
の非共通電極に接合された前記導体リードの他端
部は、積層階数分に分岐させ、どの階数に積層さ
れるかによつて必要とする１本のみを残し、他の
分岐させた各導体リードの他端部は電気的に非導
通状態にして、各階数ごとに対応するそれぞれ異
なつた前記導体配線に接合された構成であつて、
前記共通電極及び非共通電極に接続している前記
導体配線はそれぞれ均等な間隔で配列され、前記
非共通電極に接続している前記導体配線の配列間
隔を、前記共通電極に接続している前記導体配線
の配列間隔より大きくしたことを特徴とするＩＣ
メモリカード。 A plurality of memory LSI chips are stacked on a printed wiring board, and one end of a conductor lead is connected to an electrode of each memory LSI chip.
The other end of the conductor lead joined to the common electrode of the I chip is overlapped and joined to the conductor wiring of the printed wiring board, and the other end of the conductor lead joined to the non-common electrode of the memory LSI chip. The conductor leads are branched into the number of stacked floors, leaving only one wire required depending on the number of stacked floors, and the other end of each branched conductor lead is kept electrically non-conductive. , which is connected to different conductor wirings corresponding to each floor,
The conductor wires connected to the common electrode and the non-common electrode are arranged at equal intervals, and the conductor wires connected to the common electrode are arranged at equal intervals. An IC characterized in that the spacing is larger than the spacing between conductor wirings.
Memory card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989082595U JPH0323482U (en) | 1989-07-13 | 1989-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989082595U JPH0323482U (en) | 1989-07-13 | 1989-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0323482U true JPH0323482U (en) | 1991-03-12 |
Family
ID=31629554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989082595U Pending JPH0323482U (en) | 1989-07-13 | 1989-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0323482U (en) |
-
1989
- 1989-07-13 JP JP1989082595U patent/JPH0323482U/ja active Pending
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