JPH0323026B2 - - Google Patents

Info

Publication number
JPH0323026B2
JPH0323026B2 JP9823084A JP9823084A JPH0323026B2 JP H0323026 B2 JPH0323026 B2 JP H0323026B2 JP 9823084 A JP9823084 A JP 9823084A JP 9823084 A JP9823084 A JP 9823084A JP H0323026 B2 JPH0323026 B2 JP H0323026B2
Authority
JP
Japan
Prior art keywords
memory
data
buffer
transmission
external device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9823084A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60241346A (ja
Inventor
Akira Jinsaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9823084A priority Critical patent/JPS60241346A/ja
Publication of JPS60241346A publication Critical patent/JPS60241346A/ja
Publication of JPH0323026B2 publication Critical patent/JPH0323026B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
JP9823084A 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム Granted JPS60241346A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9823084A JPS60241346A (ja) 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9823084A JPS60241346A (ja) 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム

Publications (2)

Publication Number Publication Date
JPS60241346A JPS60241346A (ja) 1985-11-30
JPH0323026B2 true JPH0323026B2 (OSRAM) 1991-03-28

Family

ID=14214157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9823084A Granted JPS60241346A (ja) 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム

Country Status (1)

Country Link
JP (1) JPS60241346A (OSRAM)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU5468299A (en) * 1998-08-06 2000-02-28 Cees Bastiaansen Melt-processible poly(tetrafluoroethylene)
US7631051B1 (en) * 2008-09-29 2009-12-08 Gene Fein Geolocation assisted data forwarding storage
US9203928B2 (en) 2008-03-20 2015-12-01 Callahan Cellular L.L.C. Data storage and retrieval
US8458285B2 (en) 2008-03-20 2013-06-04 Post Dahl Co. Limited Liability Company Redundant data forwarding storage

Also Published As

Publication number Publication date
JPS60241346A (ja) 1985-11-30

Similar Documents

Publication Publication Date Title
US6636926B2 (en) Shared memory multiprocessor performing cache coherence control and node controller therefor
Nowatzyk et al. The S3. mp scalable shared memory multiprocessor
KR100919386B1 (ko) 메모리 허브 구조를 가진 메모리 모듈들에 대한 메모리 액세스들을 제어하는 방법 및 시스템
US5574862A (en) Multiprocessing system with distributed input/output management
US5363484A (en) Multiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packets
KR970029014A (ko) 데이타 프로세싱 시스템 및 방법
JPH065527B2 (ja) 通信ネットワークアダプタ
JPH0158540B2 (OSRAM)
US6226685B1 (en) Traffic control circuits and method for multicast packet transmission
EP0489583A2 (en) Multiple processor cache control system
US5895496A (en) System for an method of efficiently controlling memory accesses in a multiprocessor computer system
US8447952B2 (en) Method for controlling access to regions of a memory from a plurality of processes and a communication module having a message memory for implementing the method
JPH0323026B2 (OSRAM)
JPH10262272A (ja) 時分割多重化通信媒体の簡単なインターフェース
US4618946A (en) Dual page memory system having storage elements which are selectively swapped between the pages
JPS5852264B2 (ja) マルチユニツト・システム
USRE38514E1 (en) System for and method of efficiently controlling memory accesses in a multiprocessor computer system
GB2221066A (en) Address translation for I/O controller
JP2710587B2 (ja) 情報処理システム
JP3178474B2 (ja) 通信制御装置
JP3323142B2 (ja) クロスバ装置、多段クロスバ装置及び情報処理装置
US6741602B1 (en) Work queue alias system and method allowing fabric management packets on all ports of a cluster adapter
JP2984594B2 (ja) マルチクラスタ情報処理システム
JP2969817B2 (ja) 情報処理システム
JPH04330541A (ja) 共通データ転送システム