JPH03224280A - Josephson device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a resistor having a required resistance value without using any resistor protective layer and, at the same time, to ensure a stable resistance value which is less in fluctuation by providing a specific high-melting point metallic layer between the connecting surfaces of prescribed layers. CONSTITUTION:When a Zr resistance layer 2 and layer 3 of a high-melting point metal, such as titanium, vanadium, tantalum, tungsten, etc., are successively formed on a substrate 1 in a vacuum atmosphere, no oxide film is formed on the surface of the layer 2, since the layer 2 is not exposed to the air. When the substrate 1 is carried into a deposition device in such state, an oxide film 4 is formed on the surface of the layer 3 by the air. A resistance body composed of the layer 2 is formed by removing the film 4 by Ar sputtering, depositing an Nb super-conducting layer 5, and removing the layers 5 and 3 by etching with a large selection ratio between the layers 5 and 3 to the layer 2. When the resistor is formed, the patterning layer 5a of the layer 5 and the layer 2 are connected with each other without forming any resistance protective layer. As a result, a resistor of a required resistance value can be obtained without using any resistance protective layer and, at the same time, a stable resistance value which is less in fluctuation can be ensured. Therefore, the design margin of the resistance can be decreased and the margin of a related circuit can be increased.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a Josephson element and a method for manufacturing the same, and particularly to a resistance element for a Josephson integrated circuit and a method for manufacturing the same. In its manufacturing method, it is possible to obtain a resistor with a desired value without using a resistor protective layer, and to ensure a stable resistance value with little variation, which in turn reduces the design margin of other circuit elements by keeping the design margin of the resistor small. [1] It is an object of the present invention to provide a Josephson device and a method for manufacturing the same that can increase the integration density by widening the zirconium resistor layer and the zirconium resistor layer formed on the substrate. In the Josephson element having a niobium superconducting layer, a refractory metal layer is provided on a connection surface between the zirconium resistance layer and the niobium superconducting layer.

FIELD OF THE INVENTION The present invention relates to a Josephson element and a method of manufacturing the same, and more particularly to a resistance element of a Josephson integrated circuit and a method of manufacturing the same.

In recent years, there have been many reports on the high-speed operation of integrated circuits using Nb/niobium/AjO and (aluminum oxide)/Nb Josephson junction elements, and these are expected to be used as future computer elements.

[Prior Art] As a conventional resistor for an integrated circuit using a Nb/AjOx/Nb dijisefson junction, M.

(molybdenum) and Zr (zirconium) are known.

When Mo is used as a resistor, SlO□ (Sili:
An MO thin film is deposited on an insulating film such as a 1-oxide film), patterned using a resist, and then deposited on the patterned MO film to connect the Mo resistor to Nb, which is a wiring metal. After providing a mask (referred to as a "resistance protection layer") with Sin, the portion of Sin that contacts the Mo resistor and Nb is selectively removed to form an opening, and Nb is deposited in the opening. was forming. Correspondingly, when Zr is used as a resistor, a high selection ratio can be obtained between Zr and Nb, so Nb is formed directly on the Zr resistor, and some of the Nb on the Zr resistor is in contact with Zr. It can be formed by removing Nb except for a portion. When Zr is used as a resistor in this way, there is an advantage that a resistive protective layer is not required.

By the way, in the production of integrated circuits, superconductors, resistors, and dielectrics are deposited using different apparatuses, and the following problems have occurred in connection with this.

[Problems to be Solved by the Invention] In the conventional method, at the contact portion where the Zr resistor is connected to the superconducting layer, Zr is once exposed to the atmosphere after the Zr film is formed and before the Nb film is formed. , an oxide film is formed on the Zr surface. This is because Zr is a metal that is much more easily oxidized than Mo or Nb. And this Zr
Oxide is a semiconductor at room temperature, but at extremely low temperatures, such as the absolute temperature of 4.2, where a Josephson device operates, its electrical properties become an insulator, so there is a high resistance between Zr and Nb. A problem arises in that layers are formed.

It is easy to apply the conventional technique of using MO as a resistor material and a dielectric resistance protection layer to Zr to create a Josephson element by providing a resistance protection layer on a Zr resistor. However, in this case, the advantage of the Josephson element fabrication method that makes use of selective etching of the resistive materials Zr and Nb and eliminates the need for a resistive protective layer cannot be utilized.

When using a Josephson device fabrication method that eliminates the need for a resistive protective layer, this high-low resistive layer between Zr and Nb is removed by sputter etching using Ar or the like before depositing Nb. The situation will be explained below with reference to FIG.

(2) After forming a Zr resistance layer 31 by depositing tf1 of Zr as a resistance material on a silicon substrate 30, it is processed into a desired shape by RIE using CC14 gas (see FIG. 6(a)). Next, the silicon substrate 30 is transferred from the RIE apparatus to an Nb deposition apparatus.

■After attaching the silicon substrate 3o to the Nb deposition apparatus and evacuating it to vacuum, the Ar pressure was set to 50 rrt Torr, and near! / ;Insert the board 30 so that it becomes the #i bucket.
By applying fEls force, the oxide layer 32 formed on the surface of the Zr resistance layer 31 is removed by sputter etching (see FIG. 6(b)).

■Depositing the Nb superconducting layer 33 (see Figure 6 (()))
.

■RIE using CF4 gas using resist as a mask
Processing is performed to pattern Nb superconductors #33a and 33b (see Fig. 6 (d>15)).

According to such a conventional manufacturing method, the oxide 1 pattern 32 was removed in the step (2) above, but since this Ar sputter etching has no selectivity between the Zr resistor 131 and the oxide film 32, the Zr resistor layer 31 It was also supposed to be spatsutae/ching. That is, since Ar sputter etching does not have etching selectivity, the Zr resistance layer 31 becomes thinner, increasing the resistance value, and also causes variations in the resistance value.

Therefore, the present invention provides a Josephson element using Nb as a superconducting material and Zr as a resistive material, and the J-method for manufacturing the same, in which a resistor with a desired value can be obtained without using a resistor protective layer, and is stable with less variation. The purpose of the present invention is to provide a Josephson element and a method for manufacturing the same, which can secure the desired resistance value and further reduce the design margin of the resistor to widen the design margin of other circuit elements and improve the degree of integration. do.

[0! Means for Solving the Problem] The above problem is solved by a Josephson element having a zirconium resistance layer formed on a substrate and a niobium superconducting layer connected to the zirconium resistance layer. This is achieved by a Josephson device characterized in that a refractory metal layer is provided on the full connection surface between the niobium superconducting layer and the niobium superconducting layer.

Moreover, in the above-mentioned element, the above-mentioned Josephson element is achieved, wherein the high melting point metal layer is formed of titanium, vanadium, tantalum, tungsten, or niobium.

The above-mentioned problems include a step of depositing a high melting point metal layer on the zirconium resistance layer without exposing the 1ltf zirconium resistance layer to the atmosphere after depositing the zirconium resistance layer on the substrate; After patterning the gold layer and the zirconium resistance layer into a predetermined shape and removing the oxide film that naturally grew on the high melting point metal layer -F, niobium! etching the niobium layer and the refractory metal layer selectively with respect to the zirconium resistive layer, the niobium layer being connected to the niobium layer through the refractory metal layer; This is achieved by a method for manufacturing a Josephson device characterized by forming a zirconium resistance layer.

Further, in the above manufacturing method, the high melting point gold 1rjJ
H, titanium, vanadium, tantalum, tungsten,
Alternatively, this can be achieved by a method of manufacturing a Josephson element characterized in that it is made of niobium.

Hereinafter, the principle of the present invention will be explained based on FIG.

FIG. 1 is a diagram explaining the principle of the present invention.

■ After depositing the Zr layer 2 on the substrate 1, in the same vacuum (Zr
(r) Depositing the high melting point metal layer 3 (in such a way that the surface of R112 is not oxidized). Subsequently, the Zr layer 2/high melting point metal layer 3 is processed into the shape of a desired resistance element (see FIG. 1(a)).
reference).

■To form a Josephson device, transfer the substrate l treated in (■) into the Nb/insulating material/Nb thin film deposition apparatus.At this time, without transferring the substrate 1 from (■) to the apparatus (■), is exposed to the atmosphere, and an oxide film 4 is formed on the surface of the high melting point metal layer 3. Therefore, in the Nb/insulating material/Nb deposition apparatus, the oxide 1!4 is removed by Ar sputter etching or the like (see FIG. 1(b)).

(2) Depositing the Nb layer 5 as a superconducting wiring layer (see FIG. 1(C)).

(2) The Nb layer 5 and the high melting point metal layer 3 are removed by etching with a high selection ratio between the NbJl 15 and the high melting point metal layer 3 and ZrH2, and a resistor made of ZrN2 is produced.

In this way, in the Josephson element having the Zr layer 2 as a resistor formed on the substrate 1 and the Nb layers 5a and 5b as superconductors connected to this Zr qJ 2, the Zr layer 2 A Josephson element is manufactured in which a high melting point metal layer 3 is provided on the connection plane between the Nb[5a and 5b] (see FIG. 1(d)).

[Function] In the present invention, the high melting point metal layer 3 is deposited on the ZrH2 which becomes the resistor without exposing it to the atmosphere, and then when the wafer is transferred to another deposition device, the high melting point metal layer 3 is deposited. In order to remove the oxide film 4 that naturally grows on the surface by sputter etching, the high melting point metal layer 3 and the N layer as the superconducting wiring layer above
The electrical contact with the b layers 5a and 5b becomes the contact between the high melting point metal layer/Nbl, and good contact can be obtained.

Further, when etching the oxide film 4 on the high melting point metal Fiii 13, the ZrNJ 2 serving as a resistor is not etched, so that fluctuations in the resistance value of the Zr layer 2 can be prevented.

Further, the Nb layer 5 and the high melting point metal layer 3 are etched away, and the Zr layer 2 as a resistor and the N as a superconductor connected to this ZrPfIJ2 via the high melting point metal ajef3 are etched.
When forming the b layers 5a and 5b, the etching rate of the Zr layer 2 can be made much smaller than that of the high melting point metal layer 3.
13 and Zr! It can be stopped at the interface of @2. Therefore, it is possible to prevent the Zr layer 2 serving as a resistor from being over-etched when etching the high melting point metal layer 3, and it is possible to reduce variations in the resistance value of the Zr layer 2.

L Implementation fM] The present invention will be specifically described below based on illustrative examples.

FIG. 2 is a sectional view showing a Josephson device according to an embodiment of the present invention.

In this example, a Nb layer is used as the high melting point metal 1t03 shown in FIG.

For example, on the Si substrate 10, a layer of N with a thickness of 200 to 300 nm is placed.
b Ground plane 71 (GPJt 11 is formed).

Then, on this Nbl ground layer ll, a thickness of 200 to 300
Dielectric layer (IIIM) 12 consisting of nm Sin
Zr resistance layer (R layer) 1 with a thickness of 100 nm through
3 is formed. Note that the thickness of this Zr resistance layer 13 can be changed depending on the resistance value to be set.

Further, on the Nb ground plane M11, an Nb lower electrode layer (8 layers>15a
, 15b, 15c are formed.

The Nb lower electrode layers 15a and 15b have a thickness of 10 to 2
The present embodiment is characterized in that they are each connected to a Zr resistance layer 13 via an Nb layer 14 as a Qnm high melting point metal layer. Further, the Nb lower electrode layer 15a is connected to the Nb ground plane layer 11 via a through pole opened in the dielectric layer 12.

Further, on the Nb lower electrode layer 15b, an Al Ox barrier NJ 16 with a thickness of about 6 m and an Nb upper electrode layer (5 layers) 17 with a thickness of 200 nITI are formed in this order, forming a Josephson junction.

and a Zr resistor rrA13 and a Nb lower electrode layer 15a.

A dielectric layer (I2M) 18 made of sio having a thickness of 3 Q O to 40 Q n sn is formed on the Nb upper electrode WA17. Further, on this dielectric layer 18, NbpJ with a thickness of 400 to 600 nm is formed.
An i-conducting interconnect 41 layer (WR layer) 19 is formed, and a dielectric layer 1
They are connected to the Nb upper electrode layer 17 and the Nb lower electrode layer 15c through contact holes opened at 8 and 1, respectively.

Next, a method of manufacturing the Josephson element shown in FIG. 2 will be explained using the process diagram of FIG. 3.

(2) A Nb ground plane fill is formed on the Si substrate 10 by sputtering. WAj'il of this Nb ground plane 111 is 2
00 to 300 nm. Subsequently, after forming a pattern with photoresist (not shown), RI using CF4 was performed.
E processing is performed to remove the influence of residual magnetism.
1° (see Figure 2(a)).

(2) A dielectric layer 12 of SiO□ is formed by sputtering.

The dielectric material 112 has a thickness of 200 to 300 nm (see FIG. 2(b)).

(2) A Zr resistance layer 13 is formed by sputtering.

The membrane knob of Zr resistive layer 13 is approximately 1100n.

After that, NbTm1 as a high melting point metal layer was formed in the same vacuum.
4 to a thickness of 10-20 nm. F4 Tregis)
- After forming a pattern with (not shown), RIE processing using CCL is performed to make the Zr resistance layer 13 the same size as that of the resistor, and at the same time make the Nb layer 14 the same size (second
(See figure (c)).

■ After forming the pattern of dielectric layer 12 with photoresist (not shown), R of dielectric #12 using CHFs.
IE processing is performed to open the opening 12- (see FIG. 2(d)).

(2) The oxide film 14- on the surface of the Nb layer 14 is removed by Ar sputter etching (see FIG. 2(e)). Incidentally, this step is carried out in the sputtering apparatus used in the next step (2) using Ar which is made to collide with the target.

■A Josephson junction of Nb/AI OK/Nb is formed using a sputtering method. That is, the Nb lower electrode layer 15, the Al0X barrier layer 16, the Nb upper electrode layer 1
Deposit r117 in sequence. At this time, the Nb lower electrode N1
The thickness of both 15 and Nb upper h pole layer 17 is approximately 2Q.
There is Q n m "C'. Also, AlOx barrier layer 1
The thickness of the six layers 6 is approximately 6 nm (see FIG. 2(f)).

■After forming a pattern for the upper t4 electrode layer with photoresist (not shown), RIE processing using CF4 is performed to form the Nb upper electrode Fi! 217 is removed, and then AlO is removed by Ar sputtering.
The x barrier layer is 16 layers thick and has a thickness of 6 (see FIG. 2(g)).

■After forming the pattern of the lower type GI layer with photoresist (not shown), use CF4 to form the Nb lower electrode layer 15.
RIE processing is performed to form Nb lower electrode layers 15a and 15b.
, 15c (see FIG. 2(h)).

(2) A dielectric layer 18 of SiO2 is formed by sputtering. The film thickness is 300 to 400 nm.

After forming a pattern of the dielectric layer 18 with a photoresist (not shown), RIE processing using CIIF is performed to open a contact opening 18- in the superconducting wiring layer (see FIG. 2(i)).

An ONb superconducting wiring layer 19 is formed by sputtering. The film thickness is 400 to 600 nm. After patterning with photoresist (not shown), R using CF4
IE processing is performed to pattern the Nb superconducting wiring layer 19 (see FIG. 2(J)).

As described above, the fabrication of the Josephson integrated circuit is completed through the steps (1) to (4) shown in FIGS. 2(a) to (J).

Here, unlike the conventional method, in the step (2) shown in FIG. 2(d), a coating with the Nb layer 14 is provided on the Zr resistance layer 13. During the RF sputter etching process, the Zr resistance layer 13
The surface is not scraped by Ar, and therefore, variations in resistance due to Ar sputter etching do not occur.

In addition, in the step (3) shown in FIG. 2(h), the etching of the Nb lower electrode layer 15 is completed in about 5 minutes. According to experiments, the etching rate of Zr by RIE using CF4 is 0.7 nm/min.

That is, by over-etching the NbT part $4[15 for about 2 minutes, for example, the Zr resistor 1/1J13 becomes 1.
4nmj, or it will not be possible to remove it. If the design value of the sheet resistance is 5Ω/hole, the required projection of the Zr resistive layer 13 is 1
It is 100n. At this point, the film thickness of the Zr resistance layer 13 is N
b 1.4 during over-etching of the lower electrode 7115
If it becomes thinner by nm, the sheet resistance value will be -1 of the M4 thickness.
, even considering that it is proportional to the square of the square, the increase in sheet resistance value is only 1.7% compared to when the Zr resistance layer 13 is deposited.Normally, the design margin is 110%, so this value is well within the design margin and is not a problem.

However, in this embodiment, since the Zr resistance layer 13 and the NbB layer 4 are in direct contact with each other, the resistance value of the Zr resistance layer 13 may vary depending on the number of devices. For example, 4f at room temperature
If left for J months, the resistance value of the Zr resistance layer 13 will be -0.52
% to -58%, and the dispersion may become worse.

Therefore, next, a Josephson element according to another embodiment that also solves this problem will be explained using FIG. 4.

FIG. 4 is a sectional view showing a Josephson device according to another embodiment of the present invention.

In this embodiment, an 'I'i (titanium) layer is used as the high MI+ metal layer 3 shown in FIG.

In this figure, since the overall structure of the Josephson element is the same as that of the above embodiment, the description will be limited to the resistive element part, which is the characteristic part of the invention, and the Nb ground plane layer (GP layer)
, dielectric NJ (1 layer), Nb lower electrode layer (B layer) constituting the Josephson junction, Al0X barrier layer and Nb
A description of the upper part t[1 (J1t4), etc. will be omitted.

For example, on the Si substrate 20, a Z layer with a thickness of 100 nm
An r resistance layer (R layer) 21 is formed. Further, on the SI substrate 20, Nb superconducting wiring layers 22a and 22b with a thickness of 200 nrrt are formed. And this Nb
The superconducting wiring layers 22a and 22b are connected via 'r' i PgIJ23 as a high melting point metal layer with a thickness of 70111,
A feature of this embodiment is that each of these is connected to the Zr resistance layer 21.

Next, a method of manufacturing the Josephson element shown in FIG. 4 will be explained using the process diagram of FIG. 5.

(2) A Zr resistance layer 21 is formed on the St substrate 20 by sputtering. The thickness of the Zr resistance layer 21 is approximately 1100 nm. Thereafter, in the same vacuum, one layer 23 as a high melting point metal layer is deposited to a depth of 7nrr+ (Fig. 5(a)
)reference).

■After forming a resistor pattern with photoresist 24, the Ti layer 23 and Zr
The resistive layer 21 is continuously processed into a desired shape, and the Zr resistive layer 21 is made to have the dimensions of a resistor (see FIG. 5(b)).

■In the Nb sputtering equipment, after removing the naturally grown oxide film (not shown) on the Ti layer 23 & surface by Ar sputter etching, etc., in the same equipment, using a sputtering method, Nb [conducting wiring M22] is removed. Form a film. Its thickness is 200 nm (see Figure 5(c)).

■After forming a superconducting wiring layer pattern with the photoresist 25, RIE processing is performed using CF to remove the Nb superconducting wiring layer 22 and ]j layer j layer 2, and forming the Nbfi conductive wiring layer 22a, 22b (Fig. 5(d))
reference).

As described above, the fabrication of the resistor element in the Josephson integrated circuit is completed by one culm of (1) to (4) shown in FIGS. 5(a) to (d).

In this way, this embodiment differs from the above embodiment in that the Zr resistor N413
and N b lower type '4f! While the NbB layer 4 as a high melting point metal layer is provided on the connection surface with the layers 15a and 15b, the Zr resistance layer 21 and the Nb superconducting wiring layer 22a and 22b
A '1'11 layer 3 as a high melting point metal layer is provided on the connection surface with the metal layer.

Therefore, in the same manner as in the above embodiment, when performing RF sputter etching of the oxide film naturally grown on the surface of the i layer 23 using Ar, the surface of the Zr resistance layer 21 is not scraped, so that the Zr resistance layer 21
There will be no variation in the resistance value, and
By removing the oxide film on the surface of the layer 23, the Ti layer 2
Good electrical:1 contact can be obtained between N.sub.3 and the Nb superconducting interconnects N.sub.22a, 22b.

In addition, Nb and I”i due to CF4 under certain conditions
The machining and cutting speeds of RIF of l- are 60 n each.
rrt/min and 50 nm/min, whereas the etching rate of Zr RIE is 0.7 n
m/m1n. Therefore, similarly to the above embodiment,
Nb superconducting wiring layer 22 and 'ri layer 2 layer 3r resistance layer 2
Since it is possible to perform etching with a high selection ratio with respect to Z.
Nb superconducting wiring layer 22 on r resistance layer 21 and 'l' i
By removing only the Nb superconducting wiring layer 22
a, 22b can be patterned, and an increase in the resistance value of the Zr resistor P#21 due to overetching can be sufficiently suppressed within the design margin.

And also, Nb superconducting wiring 7m22a, 22b and Z
By providing r' i
Electrical contact with the r resistance layer 21 is also improved.

Furthermore, in the above embodiment, the resistance value of the Zr resistance layer 13 fluctuates and its variation may become worse, whereas in this embodiment, the Since direct contact with the conductive wiring layers 22a and 22b is prevented, the resistance value of the Zr resistance layer 21 does not change over time as in the above embodiment, and a stable resistance element can be created. .

According to the inventor's experiments, Z
The resistance value of the r resistance layer 21 changes by only +2.3% at maximum, and compared to the fluctuation of -0.52% to -58% in the above embodiment, the resistance value changes over time and is stable. It shows.

In addition, instead of the '1゛i layer, the ■ (vanadium) layer, 1
' a (tantalum) W74 or W (tungsten)
Even if a high melting point metal layer such as a layer is used, the same as the above example]
−A Josephson element can be formed by
Further, the same effects as in the above embodiment can be achieved.

The same effect can also be achieved by using a [)t (platinum) layer, but unlike the above-mentioned high melting point metal layer, Cd,
Since continuous RIE processing cannot be performed with the Nb layer, it is necessary to perform etching separately.

[Effects of the Invention] As explained above, according to the present invention, by providing a high melting point metal layer on the connection surface between the zirconium resistance layer and the niobium superconducting layer, a desired value can be achieved without using a resistor protection layer. In addition to being able to obtain a resistor, it is also possible to suppress the variation in resistance value caused by conventional Ar sputter etching before depositing the Nb superconducting layer, and to realize a stable Zr resistance layer, which in turn improves the design margin of the resistor. It is possible to suppress the noise to a small value and widen the design margin of a circuit element with that performance.

This makes it possible to improve and stabilize the performance of the Josephson element and, in turn, increase the degree of integration of the Josephson integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a sectional view showing a Josephson device according to an embodiment of the present invention, FIG. 3 is a process diagram showing a method for manufacturing the Josephson device shown in FIG. FIG. 4 is a sectional view showing a Josephson device according to another embodiment of the present invention, FIG. 5 is a process diagram showing a method for manufacturing the Josephson device shown in FIG. 4, and FIG. 6 is a conventional method for manufacturing a Josephson device. FIG. In the figure, 1...substrate, 2...Zr layer, 3...high melting point metal layer, 4...oxide film, 5...・Nb layer, 10.20.30...Si substrate, 11...
...Nb ground plane layer, 11-... Clear, 12.18... Dielectric layer, 11 18-... Opening, 13.21.31----・-Zr resistance layer, 14...
...NbFl, 14'' 32...Oxide film, 15.15a, 15b, 15c=-----Nb lower electrode layer, 16...AIO, barrier layer, 17. ...Nb upper electrode layer, 19.22.22a, 22b, 33-...Nb superconducting wiring layer, 23...'ri layer, 24.25... Photoresist.

Claims (1)

[Claims] 1. In a Josephson element having a zirconium resistance layer formed on a substrate and a niobium superconducting layer connected to the zirconium resistance layer, the connection between the zirconium resistance layer and the niobium superconducting layer is A Josephson element characterized in that a high melting point metal layer is provided on a connecting surface between the two. 2. The device according to claim 1, wherein the high melting point metal layer is titanium, vanadium, tantalum,
A Josephson element characterized by being made of tungsten or niobium. 3. After depositing the zirconium resistance layer on the substrate, depositing a high melting point metal layer on the zirconium resistance layer without exposing the zirconium resistance layer to the atmosphere; and the high melting point metal layer and the zirconium resistance layer. a step of patterning the niobium layer into a predetermined shape; a step of depositing a niobium layer on the high melting point metal layer after removing an oxide film naturally grown on the high melting point metal layer; and a step of depositing a niobium layer on the high melting point metal layer; selectively etching the zirconium resistive layer with respect to the zirconium resistive layer to form the zirconium resistive layer connected to the niobium layer via the high melting point metal layer. Production method. 4. The manufacturing method according to claim 3, wherein the high melting point metal layer is made of titanium, vanadium, tantalum,
A method for manufacturing a Josephson element, characterized in that it is made of tungsten or niobium.