KR940001297B1 - Josephson integrated circuit having a resistance element - Google Patents

Abstract

No content.

Description

Josephson Integrated Circuit with Resistor

1A-1D show the manufacturing steps of a conventional resistance element used in a Josephson integrated circuit.

2a-2d illustrate an embodiment of the present invention.

3 is a structural diagram of a Josephson integrated circuit using the resistance element of the present invention, and

4A-4J show the manufacturing steps of the integrated circuit of FIG.

The present invention relates to a Josephson integrated circuit, in particular to a Josephson integrated circuit comprising a resistance element therein.

Intensive efforts are being made to develop ultrafast integrated circuits employing Josephson junctions.

Josephson junctions are generally formed by AlO _X tunneling barrier films sandwiched by a pair of niobium superconducting layers. Such Josephson integrated circuits generally include resistive elements, and molybdenum or zirconium is generally used as the resistive material forming the resistive element. Zirconium is particularly preferred as a resistive element because it exhibits a smaller etch rate than that of niobium used for superconducting interconnect patterns. Thus, the fabrication of a resistive element comprising patterning a metal layer of resistive material by etching is actually simple.

1A-1D show a conventional process for providing a zirconium resistance element.

A zirconium layer 11 functioning as a resistance band in FIG. 1A is first deposited on a silicon substrate by a sputtering process or the like, and then patterned to form a zirconium band having a desired resistance value. In this patterning fixation, the substrate 10 is removed from the deposition apparatus and transferred to the etching apparatus. During transport, the surface of the zirconium 11 is inevitably exposed to air, and an oxide film 11a of zirconium is formed on the surface of the zirconium layer 11. Oxides of zirconium generally exhibit semiconductor properties at room temperature but behave as insulators at cryogenic temperatures, such as 4.2 ° K, used to operate Josephson devices. In other words, the surface of the zirconium layer 11 is completely covered with a thermal zirconium oxide film. The thickness of the zirconium film 11a is about 2-3 nm, and the thickness of the zirconium band 11 can be 100 nm, depending on the desired resistance value of the resistance value. After transfer to the etching apparatus, the zirconium layer 11 is patterned by the reactive ion etching method RIC using carbon tetrachloride (CCl ₄ ) etching gas in the zirconium band as shown in FIG. 1A. It should be noted that the RIE method using CCl ₄ acts on zirconium and niobium at nearly the same etch rate.

Attached to this zirconium strip 11 is a niobium superconducting interconnect. This oxide film prevents electrical connection to the zirconium band 11, the structure of FIG. 1a is subjected to a sputter etching process, and the zirconium oxide layer 11a is removed by the impact of argon ions as shown in FIG. 1b. . This sputter etching process continues until almost the entire oxide layer 11a is removed.

After removal of the oxide layer 11a, the niobium layer 12 is attached to bury the zirconium band 11 below as shown in FIG. 1c, and the niobium layer 12 is shown in FIG. 1d. They are separated from each other and patterned in the first conductor piece 12a and the second conductor piece 12b with a zirconium band 11 therebetween. This patterning is performed by RIE method using carbon 4 fluorine (CF ₄ ) as an etching gas. In this way, the first and second conductor pieces 12a and 12b are electrically connected to the zirconium band 11. The RIE process selectively acts on niobium and the zirconium strip 11 remains almost intact even when the niobium layer 12 is patterned.

It will be immediately understood that this process in the above process is problematic in the process of FIG. 1B for removing the oxide film 11a. Since the impact of argon ions is indiscriminate regardless of the oxide film 11a or the zirconium band 11, there is a substantial risk that the zirconium band 11 itself undergoes a sputter etching process after the oxide film 11a is removed. . When this occurs, the resistance of the resistive element inevitably deviates from the designed resistance. It is extremely difficult to stop the sputter etching process at the moment when the upper surface of the zirconium band 11 is exposed at this moment. Moreover, the conventional structure of FIG. 1d has a problem that the resistance value of the resistance element varies with time as described later with respect to the effect of the present invention.

When molybdenum is used as the resistive band 11 instead of zirconium, a problem arises in the step 1d of patterning the niobium superconducting layer, since molybdenum has an etching rate that is nearly equal to that of niobium. Therefore, the patterning process of FIG. 1d often removes the molybdenum resistance band 11. In order to avoid this, it is necessary to protect a part of the surface of the band 11 corresponding to the portion exposed in the structure of FIG. 1d by a material such as silicon oxide which is not affected by the etching process. However, the provision of such a protective region is undesirable because a complicated deposition and patterning process is required between the steps of FIG. 1B and 1C.

It is therefore a general object of the present invention to provide a novel and useful Josephson integrated circuit which eliminates this problem.

It is still another object of the present invention to provide a Josephson integrated circuit including a zirconium resistance element which almost eliminates the resistance value of the zirconium element from changing with time.

Another object of the present invention includes a substrate comprising a Josephson junction, the substrate having an upper major surface and a lower major surface; A strip that is bounded by a lower major surface and an upper major surface and provided on an upper major surface of the substrate; A first refractory metal layer having a lower major surface and an upper major surface and provided on the first region of the upper major surface of the resistance band; A second refractory metal layer having a lower major surface and an upper major surface and provided on a second region of an upper major surface of the resistance band separated from the first region; A first superconducting connection pattern and a first superconducting connection pattern provided on an upper major surface of the substrate to cover an upper surface of the first refractory metal layer, and separated from the first superconducting connecting pattern and provided on an upper major surface of the substrate to It is to provide a Josephson integrated circuit composed of a second superconducting connection pattern covering the upper main surface. Refractory metals used as the first and second refractory metal layers include niobium, molybdenum, titanium, vanadium, tantalum, tungsten, platinum and palladium. It has been found that the variation of the resistance of the zirconium resistance band with time according to the present invention is sufficiently improved compared to the prior art.

Another object of the present invention is a method of manufacturing a Josephson integrated circuit comprising a Josephson junction and a resistance element formed on a substrate, the method comprising: forming a zirconium layer on a substrate of the Josephson integrated circuit; Forming a refractory metal layer of a refractory metal on the zirconium layer which exhibits an etching rate smaller than that of the zirconium when the etching process is applied, which is performed after the formation of the zirconium layer without exposing the zirconium layer to air. ; Patterning the zirconium layer and the refractory metal layer in a resistance band; Removing the oxide layer formed on the refractory metal layer from the resistance band in the patterning step; Forming a superconducting layer on the refractory metal layer; And patterning a superconducting layer on the refractory metal layer to form a superconducting connection pattern connected to the resistive strip, wherein the patterning of the superconductor layer forms part of the superconductor layer over the resistive strip and the refractory metal layer with respect to the zirconium layer forming the resistive strip. It is to provide a method for manufacturing a Josephson integrated circuit comprising a step made by an etching process to selectively remove.

In accordance with the present invention, the risk of the zirconium layer in the resistive strip removing the oxide layer is almost eliminated by providing a refractory metal layer protecting the zirconium layer, and undesirable changes in the thickness of the zirconium layer functioning as the resistive band are eliminated. This eliminates the uneven fluctuations in the resistance of the resistance band. Refractory metals used as refractory metal layers have an etch rate that is actually greater than the etch rate of zirconium, and the etching employed in patterning the superconducting layer does not harm the thickness of the zirconium resistance band.

Other objects and further features of the present invention will become apparent upon reading the following detailed description in conjunction with the accompanying drawings.

2A-2D show an embodiment of the present invention for fabricating a zirconium resistance element for use in a Josephson integrated circuit. In FIG. 2A, an insulating substrate 21, such as silicon oxide, is joined with an attachment chamber of a sputtering apparatus so that zirconium 22 is attached to the substrate by sputtering to a predetermined thickness such as 100 nm. By this, the air of the attachment chamber is usually removed and the thickness control of the zirconium 22 is obtained very precisely. Moreover, the refractory metal layer 23 uses the same sputtering apparatus and maintains the attachment chamber in the apparatus in a vacuum state, and is deposited to a thickness of about 10 nm on the zirconium layer 22 by sputtering immediately after attachment of the zirconium layer 22. . This can easily be done by rotating the stage holding the substrate 21 in the attachment chamber from a first position opposite the zirconium target to a second position opposite the target of the refractory metal. The refractory metal layer 23 is preferably made of a refractory metal which, when subjected to etching, exhibits an etching rate much higher than that of zirconium under the same etching conditions. Refractory metals include niobium, molybdenum, titanium, tantalum, tungsten, vanadium, palladium, platinum and the like. Thereby, selective removal of the refractory metal layer from the zirconium layer is made possible by the following description. Moreover, the use of metals other than niobium is particularly preferable for the reason that the resistance value of the obtained resistance element is stabilized against the change in resistance at the time described below. However, niobium is not removed from the material for the refractory metal used in the refractory metal layer 23.

After attachment of the refractory metal layer 23, the vacuum in the attachment chamber is broken and the substrate 21 is released from the sputtering apparatus. Subsequently, the substrate 21 is subjected to a photolithography pattern process using a carbon tetrachloride (CCl ₄ ) etching gas, whereby the zirconium layer 22 and the refractory metal layer 23 have the resistance band 200 shown in FIG. Patterned to form). It should be noted that the zirconium 22 and the refractory metal layer 23 actually have the same etch rate for the CCl ₄ etching gas. During this process, it will be appreciated that the surface of the refractory metal layer 23 is exposed to air. As a result, as shown in FIG. 2A, the oxide film 24 of the refractory metal which forms the layer 23 is formed. Therefore, the substrate 21 on which the resistance band 200 is formed is subjected to a sputter-etching process, where the oxide film 24 is removed by the collision of argon ions described in FIG. 2B. In an exemplary embodiment, a bias voltage of 200 volts is applied to form an argon plasma. A few minutes of sputter-etching is sufficient to remove the oxide film 24.

After removal of the oxide layer 24, the niobium or niobium alloy superconducting layer 25 is attached to the substrate 21 including the resistive band 200 with a thickness covering the resistive band immediately below.

As a result, the structure shown in FIG. 2C is obtained.

Next, the structure of FIG. 2c is subjected to another photolithographic pattern process, where the niobium layer 25 is subjected to CF ₄ etching gas to remove the resistive band 200 as shown in FIG. 2d, except at both ends thereof. Receive RIE process. As a result, the niobium superconducting layers 25 are separated from each other and patterned into a first pattern 25a and a second pattern 25b covering both ends of the resistance band 200. Moreover, a refractory metal layer 23 having an etching rate greater than or nearly equal to the etching rate of niobium subjected to CF ₄ etching gas is also simultaneously patterned into layers 23a and 23b, where layers 23a and 23b are first and second, respectively. Corresponding to the place where the second superconducting patterns 25a and 25b are covered, they are left at both ends of the resistance band 200. On the other hand, the zirconium layer 22, which actually has a smaller etching rate than in the case of niobium for the CF ₄ etching gas, remains almost intact. As a result, a current passage extending from the pattern 25a to the pattern 25b is formed through the zirconium 22 via the refractory metal layers 23a and 23b.

In the previous RIE process of FIG. 2D, the etching is automatically performed when the zirconium layer 22 is exposed as a result of the removal of the niobium layer 25 and the refractory metal layer 23 because of different etching rates between zirconium and other refractory metals. Care must be taken to stop. On the other hand, the thickness of the zirconium layer 22 in the resistor strip 200 is almost the same as the initial thickness of the previously patterned zirconium layer 22, and because of this, the resistor strip 200 provides a resistance value accurately designed in a Josephson integrated circuit. do. In the previous manufacturing process, the zirconium 22 in the structure of FIG. 2d has a thickness almost the same as that of the original as in FIG. 2a, although the sputter-etching process of FIG. 2b is applied. During the step of FIG. 2B, the zirconium layer 22 is protected from sputter-etching by the refractory metal layer 23, so that the thickness of the layer 22 does not change as long as the layer 23 is present over the layer 22. . This refractory metal layer 23 is almost selectively removed relative to zirconium 22 in the RIE process of FIG. 2d.

As already mentioned, the thickness of the zirconium layer hardly changes due to the reduced etch rate of zirconium relative to the CF ₄ etching gas. In the structure of FIG. 2d thus formed, the superconducting patterns 25a and 25b make reliable electrical contact with the upper major surfaces of the refractory metal layers 23a and 23b from which the oxide film was removed by the sputter-etching process of FIG. 2b. On the other hand, the side surface of the resistor strip 200 is still covered with the oxide film even after the step of FIG. This is not obtained. This is why the superconducting patterns 25a and 25b are provided to cover the upper major surface of the resistance band through the refractory metal layers 23a and 23b.

Next, the structure and manufacturing process of the Josephson integrated circuit in which the resistance band of the above embodiment is formed will be described. With respect to FIG. 3 showing a portion of the Josephson integrated circuit, the integrated circuit is formed on the silicon substrate 30 and the niobium ground plate 31 is formed on the silicon substrate 30 to a thickness of 200 to 300 nm. On the ground plate 31, a 200-300 nm thick silicon oxide dielectric layer 32 is provided, and a zirconium resistance band 33 is formed over the silicon oxide layer 12 to a thickness of about 100 nm. The thickness of this zirconium band 33 is changed as necessary depending on the required value of the resistance. On the niobium ground plate 31, all of the niobium, numerous lower electrodes 35a, 35b, 35c, are formed to a thickness of about 200 nm, where the electrodes 35a and 35b pass through the interfering niobium layer 34 through the zirconium band 33 Is electrically connected). Here, the silicon oxide 33 and the dielectric layer 32 correspond to the substrate 21, the zirconium band 33 corresponds to the zirconium layer 22, and the niobium layer 34 is attached to the refractory metal layers 23a and 23b. It will be understood that the electrodes 35a and 35b correspond to the superconducting patterns 25a and 25b of FIG. 2d, respectively.

In the structure of FIG. 3, the niobium electrode 35a is electrically contacted with the ground plate 31 through the contact hole 32 'formed in the dielectric layer 32. As shown in FIG. Furthermore, an annealing barrier layer 36 of AlO _X is formed on the niobium lower electrode 35b to a thickness of about 6 nm, and the tunnel barrier layer 36 is a Josephson junction with the lower electrode 35b and the upper electrode 32 of niobium. It forms on the tunnel barrier layer 36 to a thickness of 200 nm. Furthermore, a second dielectric layer 38 of silicon oxide is provided to cover the niobium lower electrodes 35a, 35b, 35c, the niobium upper electrode 17, and the zirconium resistance band 33 to a thickness of 400-600 nm.

The second dielectric layer 38 is provided with a contact hole exposing a portion of the upper electrode 37 and a portion of the lower electrode 35c, and another niobium superconducting connection pattern 39 is formed through the contact hole. ) Is provided over the second dielectric layer 38 for contact with the electrode 37.

In this Josephson integrated circuit, the resistive element is formed with the accurately controlled resistance value by adopting the structures and processes of FIGS. 2A-2D, thereby minimizing the change in operability in the obtained integrated circuit. Next, the Josephson integrated circuit fabrication process of FIG. 3 will be described with reference to FIGS. 4A-4J. By FIG. 4A, the niobium ground plate 31 is provided on the silicon substrate 30 by a sputtering process to a thickness of 200-300 nm. The ground plate 31 is continuously patterned by a photolithography pattern process using CF ₄ to form a moat 31 'to remove the remaining magnetic flux from the ground plate 31.

Next, a silicon oxide dielectric layer 12 is provided on the ground plate 31 by a sputtering process to a thickness of 200-300 nm as shown in FIG. 4B.

Furthermore, a zirconium resistance layer 13 is provided on the silicon oxide layer 12 by a sputtering process to a thickness of about 100 nm. After the zirconium layer 13 is formed, the niobium layer 14 is continuously arranged in the same arrangement chamber of the sputtering apparatus without breaking down the vacuum to a thickness of 10-20 nm. After the arrangement of the niobium layer 14, the substrate 300 is taken out of the arrangement chamber of the sputtering apparatus and subjected to the photolithography pattern process, where the zirconium band 33 and niobium are formed to form the resistance band shown in FIG. 4C. Layer 34 is simultaneously patterned by a RIE process employing a CCl ₄ etch gas. It will be appreciated that during this patterning process, niobium layer 34 is exposed to the atmosphere so that oxide layer 34 'is essentially formed on the exposed surface of layer 34.

Next, another lithographic pattern process is applied to the dielectric layer 12 and the layer 12 is subjected to the RIE etching process using CHF ₃ as the etching gas. Thus, contact holes 32 'are formed in the dielectric layer 12 as shown in FIG. 4D. Next, the structure of FIG. 4d is the reaction chamber of the sputtering apparatus and is subject to the sputter-etching process. As shown in FIG. 4e, the oxide film 34 'on the niobium layer 34 is removed by the explosion of argon ions. do. After removing the oxide film 34 ', a Josephson junction consisting of an AlO _X tunneling barrier layer sandwiched by a pair of niobium layers is formed in the same sputtering device. In particular, the niobium lower electrode 35, the AlO _X tunneling barrier layer 36 and the niobium upper electrode 37 are continuously formed in the attachment chamber at a thickness of the layers 35 and 37 set at about 200 nm while the layer 36 The thickness of is set to about 6 nm. Thus, the structure shown in FIG. 4f is obtained.

Furthermore, the structure of FIG. 4f is made by a photolithographic patterning process, where the upper electrode 37 controls the portion forming the Josephson junction and is removed by RIE treatment using CF ₄ for etching gas and the tunneling barrier layer ( 36 is mostly removed except for the portion located below the portion of the electrode 37 that is not etched. Thus, the structure shown in FIG. 4g is obtained.

Next, the lower electrode 35 is formed by a photolithography patterning process using an RIE process and CF ₄ etching gas to form the electrodes 35a, 35b and 35c as shown in FIG. 4h. Further, the silicon oxide insulating layer 18 is formed on the structure of FIG. 4H by the sputtering process to a thickness of 300-400 nm. The layer 38 is made by photolithographic patterning, whereby the connection holes 38 ′ of the layer 38 are formed by RIE treatment using a CHF ₃ etching gas. Thus, the structure of FIG. 4i is obtained.

Next, a niobium layer forming the superconductor interconnect layer 39 is provided on the structure of FIG. 4i by a sputtering process with a thickness of 400-600 nm. This layer is obtained by a RIE process using a CF ₄ etching gas and a patterned interconnect layer 39 is obtained as shown in FIG. 4j.

In a previous step, the Josephson integrated circuit of FIG. 3 is completed. In this device, the problem of unwanted etching of the zirconium layer does not occur in the step of FIG. 4e due to the niobium layer 34 protecting the zirconium band 33. Thus, the problem of resistance value change of the resistance element due to the uncontrollable etching corresponding to the conventional Josephson integrated circuit is successfully eliminated by the structure of the present invention.

After the etching process of FIG. 4h, etching is sufficient for 5 minutes to pattern the niobium electrode 35. It is experimentally found that the etch rate of zirconium by RIE treatment achieved using CF ₄ etching gas is about 0.7 nm / min. If the resistive element is designed to have a sheet resistance of 5 k? / ?, the thickness of the filled zirconium band 33 forming this sheet resistance is about 100 nm. In this case, for example, even when the effect of the layer thickness to change the sheet resistance with a power of -1.2 is considered, the increase in sheet resistance from the design value is removed by only about 1.7%. As is usual for designing resistors with a tolerance of 10%, this deviation does not have a significant impact on the operation of the Josephson integrated circuit.

In the previous first embodiment, it is found that the resistance of the resistive element may change as when niobium is used for the refractory metal layer 23 or 24. For example, if the integrated circuit of FIG. 3 stays at room temperature for four months, the resistance decreases from -0.52% to even -58%. This problem is successfully eliminated even when other metals such as titanium, vanadium, tantalum, tungsten, platinum or palladium are used in the refractory metal layer 23 or 24. Similar effects are obtained when molybdenum, vanadium, tantalum and tungsten are used in the refractory layer. Moreover, the use of precious metals such as palladium or platinum is possible even if these metals require additional etching processes.

Moreover, the present invention is not limited to the embodiments described herein, and various changes and modifications can be made without departing from the scope of the present invention.

Claims (8)

A substrate (21; 30-32) having an upper major surface and a lower major surface and on which an Josephson device 36 is formed; Resistances of zirconium (22; 23) having a lower major surface and an upper major surface and provided on the upper major surface of the substrate; First refractory metal layers 23a and 34 having a lower major surface and an upper major surface and provided on a first region of the upper major surface of the resistance band; Second refractory metal layers (23b; 34) having a lower major surface and an upper major surface and provided on a second region of the upper major surface of the resistance band separated from the first region; First superconducting connection patterns 25a and 35a provided on the upper major surface of the substrate to cover the upper surface of the first refractory metal layer; And a second superconducting connection pattern (25b; 35b) which is separated from the first superconducting connection pattern and is provided on the upper major surface of the substrate to cover the upper major surface of the second refractory metal layer. Josephson integrated circuit containing the device. 2. The Josephson device according to claim 1, wherein the first and second refractory metal layers (23a, 23b; 34) are made of a refractory metal which exhibits an etching rate greater than that of zirconium when applied to an etching process. A Josephson device according to claim 1, wherein said first and second refractory metal layers (23a, 23b; 34) comprise a refractory metal layer selected from the group consisting of titanium, vanadium, tantalum, tungsten, molybdenum and niobium. . CLAIMS What is claimed is: 1. A method of manufacturing a Josephson integrated circuit comprising a resistive element, comprising: forming a zirconium layer (22; 33) on a substrate (21; 30-32) of a Josephson integrated circuit; Forming a refractory metal layer (23; 34) of the refractory metal on the zirconium layer; This step occurs after the formation of the zirconium layer without exposing the zirconium layer to air; Patterning the zirconium layer and the refractory metal layer in a resistance band to form a resistance band 200; Removing an oxide layer (24a; 34 ') formed on the refractory metal layer at the end of the patterning step; Forming a superconducting layer mainly composed of niobium on the refractory metal layer and embedding a resistance band thereunder; And patterning a superconducting layer on the refractory metal shape to form a superconducting connection pattern connected to the resistive band, and the patterning of the superconductor layer etches the refractory metal layer and the superconductor layer, leaving a zirconium layer forming a resistive band with almost non-etching. Method of manufacturing a Josephson integrated circuit, characterized in that consisting of a step made by an etching process to selectively remove by. 5. The method according to claim 4, wherein the etching process used in the patterning of the superconducting layers (25,35) comprises a reaction ion etching process using a carbon tetrafluoride (CF ₄ ) etching gas. 5. A method according to claim 4, wherein the refractory metals (23a, 23b; 34) forming the refractory metal layer are selected from the group consisting of titanium, vanadium, tantalum, tungsten, molybdenum and niobium. 5. The Josephson method according to claim 4, wherein the patterning of the zirconium layers (22; 33) and the refractory metal layers (23, 34) for forming the resistance bands is performed by a reactive ion etching process using carbon fluorine etching gas. Integrated circuit manufacturing method. 5. The method of claim 4, wherein removing the oxide layer (24, 34 ') is a sputter etching process.