JPH05114758A - Manufacture of josephson integrated circuit - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a Josephson integrated circuit, where residual protrusions are prevented from being generated in an insulating film which protects a resistor by a very simple means that enables a layer where the resistor of high-melting point metal film is formed to be properly selected. CONSTITUTION:A first process where a ground plane 22 and an insulating film 23 are formed, a second process where a resistor 24 is formed, a third process where an insulating film 25 buried between the resistor 24 and the insulating film 23 is formed, a fourth process where an insulating film 25 electrode contact window is formed, a fifth process where an upper electrode 28, a tunnel barrier film 27 of the same pattern with the upper electrode 28, and a lower electrode 26 are formed to constitute a Josephson junction, a seventh process where an insulating film 29 provided with an electrode contact window is formed, and an eighth process where a wiring 30 brought into contact with the upper electrode 28 is formed are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a Josephson integrated circuit which is effective for improving the reliability of resistors incorporated in the Josephson integrated circuit.

The Josephson element is expected to be a constituent element of a high-speed computer because it can operate at high speed and consumes less power, and because it has high sensitivity to a magnetic field, it can be used as a medical SQUID. Application to the field is being promoted.

By the way, in the Josephson integrated circuit, a resistance film for interposing between the power supply line and the Josephson element is incorporated.
The accuracy of the resistance value of the resistance film affects the operating margin of the integrated circuit. Therefore, the reliability of the resistance film is immediately linked to the reliability of the integrated circuit.

In the future, in order to miniaturize the dimensions of the Josephson junction, wiring, etc. to achieve high integration and high speed operation of the integrated circuit, the reliability of the resistance value of the resistance film will become important. In order to improve the reliability of integrated circuits, a stable resistance film manufacturing technique must be developed.

[0005]

2. Description of the Related Art Generally, in a Josephson integrated circuit, a refractory metal such as molybdenum (Mo) is used for a resistance film. 13 to 17 are sectional side views of the essential parts of the Josephson integrated circuit in the process steps for explaining the conventional technique for manufacturing the Josephson integrated circuit, which will be described below with reference to these figures. explain.

See FIG. 13 13- (1) A ground plane 2 made of Nb is formed on a substrate 1 made of Si. 13- (2) An insulating film 3 made of SiO ₂ is formed to cover the entire surface of the ground plane 2.

See FIG. 14 14- (1) A refractory metal film 4 made of Mo or the like is formed on the insulating film 3. 14- (2) A resist film 5 having a required pattern is formed on the refractory metal film 4. 14- (3) The refractory metal film 4 is patterned using the resist film 5 as a mask.

15- (1) After removing the resist film 5, a resist film 6 having an opening 6A on the surface facing the refractory metal film 4 is newly formed. 15- (2) in the opening 6A also include forming an insulating film 7 made of SiO _x on the entire surface.

16- (1) By melting the resist film 5, only the insulating film 7 covering the surface of the refractory metal film 4 exposed in the opening 6A is left, and the others are formed together with the resist film 5. Remove. 16- (2) Lower electrode 8 made of Nb that contacts the edge of the refractory metal film 4 exposed from the periphery of the insulating film 7, AlO _x
A tunnel barrier film 9 of Nb and an upper electrode 10 of Nb are formed. 16- (3) The upper electrode 10, the tunnel barrier film 9 and the lower electrode 8 are patterned.

17- (1) SiO ₂ having an opening for exposing the upper surface of the upper electrode 10
An insulating film 11 made of is formed. 17- (2) The wiring 12 made of Nb is formed in contact with the surface of the upper electrode 10 through the opening formed in the insulating film 11.

In the above description of the steps, the refractory metal film 4 made of Mo or the like is formed by reactive ion etching (reactive) using a CF ₄ -based etching gas.
ion etching (RIE) method is applied, and thereafter, it is protected by an insulating film 7 formed by a lift-off method.

The reason why the refractory metal film 4 is protected by the insulating film 7 is that the lower electrode 8 and tunnel
In order to process the barrier film 9 and the upper electrode 10 etc., CF ₄ -based etching and
Since the RIE method using gas is applied, the refractory metal film 4 is prevented from being etched at that time and the film thickness is reduced to increase the resistance value. If the resistance value increases,
The operating margin of the integrated circuit is reduced, and the reliability is reduced.

[0013]

In the manufacturing process of the above Josephson integrated circuit, the lift-off method is applied to form the insulating film 7 for protecting the refractory metal film 4. Often a problem.

FIG. 18 is a sectional side view of a main part of a Josephson integrated circuit at a process step for explaining a problem when the lift-off method is applied, which is used in FIGS. 13 to 17. The same symbols as those used to represent the same parts or have the same meanings.

As is clear from the drawing, when the insulating film 7 is patterned by the lift-off method, the insulating film 7 does not have a good shape as shown in FIG. 15 and thereafter, and as shown in FIG. A residual protruding portion 7A, which is commonly called a "burr", is formed so as to be continuous with the edge of the film 7.

The presence of such a residual protruding portion 7A leads to a decrease in reliability as the subsequent steps are performed. For example, when the lower electrode 8 is formed, disconnection may occur at the residual protruding portion 7A, or even if the insulating film 11 is formed, the covering property is poor and a short circuit occurs.

Apart from the above-mentioned problem, a plurality of types of resistors having different resistance values are used in the Josephson integrated circuit. In that case, the resistance value differs by changing the length of the resistance film made of the same material. I'm getting resistance. In this case, the area occupied by the resistors tends to increase due to the layout, and the area of the entire integrated circuit also increases, making it difficult to manufacture a large-scale integrated circuit.

The present invention eliminates the generation of residual protruding portions in the insulating film for protecting the resistance by a very simple means of appropriately selecting the layer forming the resistance made of the refractory metal film, and Joseph The purpose is to eliminate the cause of reducing the reliability of the Son integrated circuit.

[0019]

FIG. 1 is a side sectional view showing a principal part of a Josephson integrated circuit for explaining the principle of the present invention. In the figure, 21 is a substrate made of, for example, Si, 22 is a ground plane made of, for example, Nb, 2
3 is a first-layer insulating film made of, for example, SiO ₂ , 24 is a resistor made of a refractory metal such as Mo, and 25 is, for example, S
A second insulating film made of iO ₂ , 26 is a lower electrode made of, for example, Nb, 27 is a tunnel barrier film made of, for example, AlO _x , 28 is an upper electrode made of, for example, Nb, 29
Is an insulating film made of, for example, SiO ₂ , and 30 is a wiring made of, for example, Nb.

As is apparent from the figure, in the Josephson integrated circuit of the present invention, the resistor 24 is formed between the first layer insulating film 23 and the second layer insulating film 25. Incidentally, in the conventional technique, as shown in FIGS. 15 to 17, the refractory metal film 4 corresponding to the resistor 24 is formed on the ground plane 2
And the lower electrode 8 are separated from each other on the insulating film 3. In the present invention, the insulating film 3 in the conventional Josephson integrated circuit is replaced by the first insulating film 23 and the second insulating film 25.
It is clear that there is a structure in which the resistor 24 is separated and the resistor 24 is sandwiched therebetween, and this structure brings many advantages.

From the above, in the method of manufacturing the Josephson integrated circuit according to the present invention, (1) a ground plane (eg, N substrate) is provided on the substrate (eg, Si substrate 21).
b) and the ground plane 22)
A step of sequentially forming a first insulating film (for example, a first-layer insulating film 23 made of SiO ₂ ) covering the plane, and then a resistor made of a refractory metal (for example, from Mo) on the first insulating film. Forming a resistor 24) that becomes
A step of forming a second insulating film (for example, a second layer insulating film 25 made of SiO ₂ ) so that the resistance made of the refractory metal is embedded between the first insulating film and the first insulating film; Selectively etching the second insulating film to form an electrode contact window at a position facing the edge of the resistor and at an appropriate position facing the ground plane; and then, the second step including the electrode contact window. A lower electrode film (eg, Nb film) and a tunnel barrier film (eg, AlO _x ) are formed on the insulating film.
Film) and an upper electrode film (eg, Nb film) in that order, and then patterning the upper electrode film, the tunnel barrier film, and the lower electrode film to form an upper electrode (eg, upper electrode 28 made of Nb). And a tunnel barrier film (for example, a tunnel barrier film 27 made of AlO _x ) having the same pattern as the upper electrode and a lower electrode (for example, N
b) forming a lower electrode 26) to obtain a Josephson junction, and then a third insulating film (for example, a third layer insulating film made of SiO ₂ ) having an electrode contact window facing the upper electrode. 29) and then a step of forming a wiring (for example, a wiring 30 made of Nb) that contacts the upper electrode through the electrode contact window, or ,

(2) In (1) above, at the same time when the third insulating film having an electrode contact window facing the upper electrode is formed, the lower electrode is in contact with the resistor or the ground plane at the same time. A step of forming an electrode contact window (for example, the electrode contact window 29A) also in a portion facing to, and then, at the same time when forming a wiring (for example, the wiring 30A) that contacts the upper electrode through the electrode contact window. Wiring (for example, wirings 30B, 30C, 30) that also contacts the lower electrode through the formed electrode contact window (for example, electrode contact window 29A).
D, etc.) is included, or

(3) In the above (1), a step of forming a resistor made of a refractory metal on the first insulating film and simultaneously forming a trap removing heater made of the same refractory metal is included. It is characterized by

[0024]

In the present invention, the resistance of the refractory metal is embedded in the insulating film that separates the ground plane from the lower electrode.

The first-layer insulation film ensures reliable insulation separation between the ground plane and the resistor.

The second layer insulating film protects the resistance,
It is possible to prevent the reliability of the integrated circuit from being lowered due to the damage of the resistance and the increase of the resistance value when the lower electrode and the Josephson junction are processed.

Since the residual protruding portion is not formed in the second-layer insulating film which protects the resistance, disconnection of the lower electrode or short circuit due to defective coverage of the insulating film does not occur.

Since the resistor and the lower electrode are electrically separated by the second-layer insulating film, there is no problem in terms of circuit even if the lower electrode is laid out so as to extend above the resistor. Therefore, the circuit can have a three-dimensional structure and the area can be reduced.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 to 10 are side sectional views showing a principal part of a Josephson integrated circuit in the process steps for explaining the first embodiment of the present invention. The description will be made with reference. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

See FIG. 2. 2- (1) By applying the sputtering method, the Si substrate 21
An Nb film having a thickness of, for example, 300 [nm] is formed on the surface of the. 2- (2) A resist film 31 having a pattern of a ground plane is formed by applying a resist process in a normal lithography technique.

2- (3) By applying the RIE method, the resist film 31 is used as an etching mask to pattern the Nb film formed in the step 2- (1) to form the ground plane 22. Form. The main conditions of RIE in this case are: etching gas: CF ₄ + (5 [%]) O ₂ gas pressure: 50 [mTorr] and high frequency power: 50 [W].

Referring to FIG. 3, 3- (1) By removing the resist film 31 and then applying a sputtering method, the first-layer insulating film 23 made of SiO ₂ having a thickness of 100 nm, for example, is formed on the entire surface. To form.

See FIG. 4 4- (1) By applying the sputtering method, a Mo film having a thickness of, for example, 50 [nm] is formed on the entire surface. The main conditions for sputtering in this case are Ar gas pressure: 8 [mTorr] and high frequency power: 500 [W]. 4- (2) A resist film 32 having a resistance pattern is formed by applying a resist process in a normal lithography technique.

4- (3) By applying the RIE method, the resist film 32 is used as an etching mask to pattern the Mo film formed in the step 4- (1) to form the resistor 24. .. The main conditions of RIE in this case are: etching gas: CF ₄ + (5 [%]) O ₂ gas pressure: 50 [mTorr] and high frequency power: 50 [W].

5 (1) In order to form an electrode contact window in the insulating film 23 by removing the resist film 32 and then applying a resist process in a normal lithography technique again. A resist film 33 having an opening 33A is formed. 5- (2) By applying the RIE method, the insulating film 23 is selectively etched using the resist film 33 as an etching mask, and the electrode contact window 23A is formed to expose a part of the ground plane 22. Let The main conditions of RIE in this case are: etching gas: CHF ₃ + (20 [%]) O ₂ gas pressure: 15 [mTorr] high frequency power: 100 [W].

See FIG. 6 6- (1) By removing the resist film 33 and then applying the sputtering method, the second layer insulating film 25 of SiO ₂ having a thickness of, for example, 200 nm is formed on the entire surface. To form. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and high frequency power: 11.2 [W / cm ² ]. 6- (2) A resist film 3 having an opening 34A for forming an electrode contact window with respect to the insulating film 25 by applying a resist process in an ordinary lithography technique.
4 is formed.

7- (1) By applying the RIE method, the insulating film 25 is selectively etched using the resist film 34 as an etching mask to form an electrode contact window to form the ground plane 2.
Part 2 and part of the resistor 24 are exposed. R in this case
The main conditions of the IE are: etching gas: CHF ₃ + (20 [%]) O ₂ gas pressure: 15 [mTorr], high frequency power: 100 [W].

7- (2) After removing the resist film 34, a Nb film having a thickness of, for example, 200 [nm] is formed on the entire surface by applying a sputtering method. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and direct current: 1.5 [A].

7- (3) An Al film having a thickness of, for example, 7 [nm] is formed on the entire surface by applying the sputtering method. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and direct current: 1.5 [A].

7- (4) The Al film is converted into an AlO _x film by leaving it in an oxygen atmosphere for, for example, 1 [hour] to form a tunnel barrier film 27. 7- (5) By applying the sputtering method, an Nb film having a thickness of, for example, 150 [nm] is formed on the entire surface. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and direct current: 1.5 [A].

7- (6) The resist film 35 having the pattern of the upper electrode is formed by applying the resist process in the ordinary lithography technique. 7- (7) By applying the RIE method, the resist film 35 is used as an etching mask to pattern the Nb film having a thickness of 150 [nm] formed in step 7- (5), and the upper part is formed. The electrode 28 is formed. The main conditions of RIE in this case are: etching gas: CF ₄ + (5 [%]) O ₂ gas pressure: 50 [mTorr] and high frequency power: 50 [W].

7- (8) Subsequently, by applying the sputter etching method, the resist film 35 is used as an etching mask, and A
to pattern the tunnel barrier film 27 made of lO _x. The main conditions of the sputter etching in this case are: etching gas: Ar Ar gas pressure: 10 [mTorr] and high frequency power: 100 [W].

See FIG. 8. 8- (1) After removing the resist film 35, the resist film 36 having the pattern of the lower electrode is formed by applying the resist process in the ordinary lithographic technique again. Form.

8- (2) By applying the RIE method, the resist film 35 is used as an etching mask to pattern the Nb film having a thickness of 200 nm formed in the step 7- (2). Then, the lower electrode 26 is formed. The main conditions of RIE in this case are: etching gas: CF ₄ + (5 [%]) O ₂ gas pressure: 50 [mTorr] and high frequency power: 50 [W].

See FIG. 9 9- (1) By removing the resist film 35 and then applying the sputtering method, the third layer insulating film 29 of SiO ₂ having a thickness of, for example, 300 nm is formed on the entire surface. To form. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and high frequency power: 11.2 [W / cm ² ].

9- (2) A resist film 3 having an opening 37A for forming an electrode contact window with respect to the insulating film 29 is formed by applying a resist process in an ordinary lithography technique.
Form 7. 9- (3) By applying the RIE method, the insulating film 29 is selectively etched using the resist film 37 as an etching mask, and the electrode contact window 29A is formed to expose a part of the upper electrode 28. .. The main conditions of RIE in this case are: etching gas: CHF ₃ + (20 [%]) O ₂ gas pressure: 15 [mTorr] high frequency power: 100 [W].

10- (1) After removing the resist film 37, a sputtering method is applied to form an Nb film having a thickness of, for example, 500 nm on the entire surface. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and direct current: 1.5 [A]. 10- (2) A resist film 38 having a wiring pattern is formed by applying a resist process in a normal lithography technique.

10- (3) By applying the RIE method, the resist film 38 is used as an etching mask to pattern the Nb film having a thickness of 500 nm formed in the step 10- (1). Then, the wiring 30 is formed. The main conditions of RIE in this case are: etching gas: CF ₄ + (5 [%]) O ₂ gas pressure: 50 [mTorr] and high frequency power: 50 [W]. 10- (4) The resist film 38 is removed, and then a normal technique is applied to complete the Josephson integrated circuit.

FIG. 11 and FIG. 12 are sectional side views of the essential parts of the Josephson integrated circuit in the process steps for explaining the second embodiment of the present invention. Refer to these figures below. I will explain. The same symbols as those used in FIGS. 1 to 10 represent the same parts or have the same meanings.

In this embodiment, from the beginning of the process in the first embodiment to 8- (2), that is, after the upper electrode 28 is formed, the Nb film is patterned to form the lower electrode 26.
Since the steps up to the formation of are completely the same, the description thereof will be omitted, and description will be given from the next step.

11- (1) By removing the resist film 35 and then applying a sputtering method, the third layer insulating film 29 of SiO ₂ having a thickness of, for example, 300 [nm] is formed on the entire surface. To form. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and high frequency power: 11.2 [W / cm ² ].

11- (2) The resist film 3 having an opening 37A for forming an electrode contact window for the insulating film 29 is formed by applying a resist process in a general lithography technique.
Form 7.

11- (3) By applying the RIE method, the insulating film 29 is selectively etched using the resist film 37 as an etching mask to form an electrode contact window 29A, and a part of the upper electrode 28 is formed. Also, a part of the lower electrode 26 is exposed. The main conditions of RIE in this case are: etching gas: CHF ₃ + (20 [%]) O ₂ gas pressure: 15 [mTorr] high frequency power: 100 [W].

See FIG. 12 12- (1) After removing the resist film 37, a sputtering method is applied to form an Nb film with a thickness of, for example, 500 nm on the entire surface. The main conditions for sputtering in this case are Ar gas pressure: 10 [mTorr] and direct current: 1.5 [A].

12- (2) A resist film 38 having a wiring pattern is formed by applying a resist process in an ordinary lithography technique. 12- (3) By applying the RIE method, the resist film 38 is used as an etching mask to pattern the Nb film having a thickness of 500 nm formed in the step 12- (1), and wiring is performed. 30A, 30B, 30C, 30D, etc. are formed. The main conditions of RIE in this case are: etching gas: CF ₄ + (5 [%]) O ₂ gas pressure: 50 [mTorr] and high frequency power: 50 [W].

12- (4) The resist film 38 is removed, and then a normal technique is applied to complete the Josephson integrated circuit. According to the second embodiment, the wiring in the step portion can be thickly reinforced as compared with the first embodiment.

Further, not limited to this, in the present invention,
Many modifications can be made. For example, the first-layer insulating film 23 made of SiO ₂ formed in 3- (1), 6- (1), and 9- (1) of the above-mentioned process, Since the surfaces of the second-layer insulating film 25 and the third-layer insulating film 29 can be flattened by applying a bias sputtering method, the surface of the second-layer insulating film 25 and the third-layer insulating film 29 can be planarized. Is effective in preventing the formation of a wire and preventing disconnection, and in the step 4- (3) described above, the resistor 24 is formed by patterning the Mo film. It is also possible to incorporate a trap removal heater consisting of a film.

[0058]

In the method for manufacturing the Josephson integrated circuit according to the present invention, the step of forming the ground plane and the first insulating film, the step of forming the resistor made of refractory metal, and the step of forming the resistor are performed. Forming a second insulating film to be embedded between the first insulating film, forming an electrode contact window in the second insulating film, forming a lower electrode film, a tunnel barrier film and an upper electrode film And a step of patterning to form an upper electrode, a tunnel barrier film and a lower electrode having the same pattern as the upper electrode to obtain a Josephson junction, and a third insulating film having an electrode contact window. And a step of forming a wiring that contacts the upper electrode.

By adopting the above configuration, the ground plane and the resistor are reliably separated by the first insulating film, and the resistor is protected by the second insulating film, so that the lower electrode and the Josephson junction are connected. It prevents the deterioration of the reliability of the integrated circuit due to the damage of the resistance and the increase of the resistance value when processing such as, and since the residual protruding part is not formed in the second insulating film, the disconnection of the lower electrode Alternatively, a short circuit or the like due to defective coverage of the insulating film does not occur, and furthermore, since the resistor and the lower electrode are electrically separated by the second insulating film, the lower electrode crawls above the resistor. Even if such a layout is adopted, no problem occurs in terms of the circuit, so that the circuit can be made into a three-dimensional structure and the area can be reduced.

[Brief description of drawings]

FIG. 1 is a cutaway side view of an essential part of a Josephson integrated circuit for explaining the principle of the present invention.

FIG. 2 is a side sectional view of a main part of a Josephson integrated circuit in a process main part for explaining a first embodiment of the present invention.

FIG. 3 is a side sectional view of a main part of a Josephson integrated circuit in a process main part for explaining a first embodiment of the present invention.

FIG. 4 is a side sectional view of a main part of a Josephson integrated circuit in a process key point for explaining a first embodiment of the present invention.

FIG. 5 is a side sectional view of a main part of a Josephson integrated circuit in a process main part for explaining the first embodiment of the present invention.

FIG. 6 is a side sectional view showing a principal part of a Josephson integrated circuit in a process main part for explaining a first embodiment of the present invention.

FIG. 7 is a side sectional view showing a principal part of a Josephson integrated circuit at a process step for explaining the first embodiment of the present invention.

FIG. 8 is a side sectional view of a main part of a Josephson integrated circuit in a process main part for explaining the first embodiment of the present invention.

FIG. 9 is a side sectional view showing a principal part of a Josephson integrated circuit in a process main part for explaining a first embodiment of the present invention.

FIG. 10 is a side sectional view showing a principal part of a Josephson integrated circuit in a process main part for explaining the first embodiment of the present invention.

FIG. 11 is a cutaway side view of a main part of a Josephson integrated circuit in a process main part for explaining a second embodiment.

FIG. 12 is a side sectional view of a main part of a Josephson integrated circuit in a process main part for explaining a second embodiment.

FIG. 13 is a fragmentary side view of a Josephson integrated circuit at a process step for explaining a conventional technique for manufacturing a Josephson integrated circuit.

FIG. 14 is a fragmentary side view of the Josephson integrated circuit at a process step for explaining the conventional technique for manufacturing the Josephson integrated circuit.

FIG. 15 is a fragmentary side view of the Josephson integrated circuit at a process step for explaining the conventional technique for manufacturing the Josephson integrated circuit.

FIG. 16 is a fragmentary side view of a Josephson integrated circuit in a process key point for explaining a conventional technique for manufacturing a Josephson integrated circuit.

FIG. 17 is a fragmentary side view of the Josephson integrated circuit at a process step for explaining the conventional technique for manufacturing the Josephson integrated circuit.

FIG. 18 is a cutaway side view of a main part of a Josephson integrated circuit in a process key part for explaining a problem when the lift-off method is applied.

[Explanation of symbols]

21 substrate made of Si 22 ground plane made of Nb 23 first layer insulating film made of SiO ₂ 23A electrode contact window 24 resistor made of refractory metal such as Mo 25 second layer made of SiO ₂ Insulating film 26 Lower electrode made of Nb 27 For example, tunnel barrier film made of AlO _x 28 Upper electrode made of Nb 29 For example, insulating film made of SiO ₂ 29A Electrode contact window 30 Wiring made of Nb 31 Resist film 32 Resist film 33 resist film 33A opening 34 resist film 34A opening 35 resist film 36 resist film 36A opening 37 resist film 37A opening 38 resist film

Claims (3)

[Claims] 1. A step of sequentially forming a ground plane and a first insulating film covering the ground plane on a substrate, and then forming a resistor made of a refractory metal on the first insulating film. A step of forming a second insulating film so as to fill the resistor made of the refractory metal with the first insulating film, and then selectively etching the second insulating film And forming an electrode contact window at a position facing the edge of the resistor and at a suitable position facing the ground plane, and then forming a lower electrode film and a tunnel on the second insulating film including the electrode contact window. A step of forming a barrier film and an upper electrode film in that order, and then a patterning of the upper electrode film, the tunnel barrier film and the lower electrode film to form a pattern of the upper electrode and the upper electrode. Forming a channel barrier film and a lower electrode to obtain a Josephson junction, then forming a third insulating film having an electrode contact window facing the upper electrode, and then forming the electrode contact window And a step of forming a wiring contacting the upper electrode through the method of manufacturing a Josephson integrated circuit. 2. When forming a third insulating film having an electrode contact window facing the upper electrode, at the same time, an electrode contact window is also provided at a portion facing the portion where the lower electrode is in contact with the resistor or the ground plane. And a step of forming a wiring that also contacts the lower electrode through the electrode contact window formed at the same time as forming a wiring that contacts the upper electrode through the electrode contact window. The method of manufacturing a Josephson integrated circuit according to claim 1, wherein 3. A step of forming a resistor made of a refractory metal on the first insulating film and at the same time forming a trap removing heater made of the same refractory metal. 1. A method for manufacturing a Josephson integrated circuit according to 1.